URL
https://opencores.org/ocsvn/minsoc/minsoc/trunk
Subversion Repositories minsoc
Compare Revisions
- This comparison shows the changes necessary to convert path
/minsoc/trunk/rtl
- from Rev 163 to Rev 173
- ↔ Reverse comparison
Rev 163 → Rev 173
/verilog/xilinx_dcm.v
31,6 → 31,8
`define XILINX_DCM_SP |
`elsif SPARTAN3A |
`define XILINX_DCM_SP |
`elsif SPARTAN6 |
`define XILINX_DCM_SP |
`endif // !SPARTAN3E/SPARTAN3A |
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`ifdef VIRTEX4 |
/verilog/minsoc_xilinx_internal_jtag.v
251,7 → 251,39
assign pause_dr_o = 1'b0; |
assign run_test_idle_o = 1'b0; |
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//----------------------------------------------------------------------- |
`else |
`ifdef SPARTAN6 |
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wire capture_dr_o; |
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BSCAN_SPARTAN6 #( |
.JTAG_CHAIN(1) // Chain number. |
) |
BSCAN_SPARTAN6_inst ( |
.CAPTURE(capture_dr_o), // 1-bit Scan Data Register Capture instruction. |
.DRCK(drck), // 1-bit Scan Clock instruction. DRCK is a gated version of TCTCK, it toggles during the CAPTUREDR and SHIFTDR states. |
.RESET(test_logic_reset_o), // 1-bit Scan register reset instruction. |
.RUNTEST(), // 1-bit Asserted when TAP controller is in Run Test Idle state. Make sure is the same name as BSCAN primitive used in Spartan products. |
.SEL(debug_select_o), // 1-bit Scan mode Select instruction. |
.SHIFT(shift_dr_o), // 1-bit Scan Chain Shift instruction. |
.TCK(tck_o), // 1-bit Scan Clock. Fabric connection to TAP Clock pin. |
.TDI(tdi_o), // 1-bit Scan Chain Output. Mirror of TDI input pin to FPGA. |
.TMS(), // 1-bit Test Mode Select. Fabric connection to TAP. |
.UPDATE(update_dr_o), // 1-bit Scan Register Update instruction. |
.TDO(debug_tdo_i) // 1-bit Scan Chain Input. |
); |
// End of BSCAN_SPARTAN6_inst instantiation |
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assign pause_dr_o = 1'b0; |
assign run_test_idle_o = 1'b0; |
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`else |
`ifdef VIRTEX |
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// Note that this version is missing three outputs. |
436,6 → 468,8
`endif |
`endif |
`endif |
`endif // !`ifdef SPARTAN3 |
`endif // !`ifdef SPARTAN2 |
`endif |
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endmodule |
/verilog/minsoc_onchip_ram.v
176,7 → 176,9
`define MINSOC_XILINX_RAMB16 |
`elsif VIRTEX5 |
`define MINSOC_XILINX_RAMB16 |
`endif // !SPARTAN3/SPARTAN3E/SPARTAN3A/VIRTEX2/VIRTEX4/VIRTEX5 |
`elsif SPARTAN6 |
`define MINSOC_XILINX_RAMB16 |
`endif // !SPARTAN3/SPARTAN3E/SPARTAN3A/VIRTEX2/VIRTEX4/VIRTEX5/SPARTAN6 |
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// |