OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /minsoc/trunk/sw/drivers
    from Rev 149 to Rev 158
    ↔ Reverse comparison
  •

Rev 149 → Rev 158

/eth.c
1,5 → 1,5
#include <board.h>
#include <support.h>
#include "interconnect.h"
#include "eth.h"
 
int eth_tx_done;
/uart.h
117,7 → 117,7
#define UART_EFR_ENI 0x10 /* Enhanced Interrupt */
 
 
void uart_init(void);
void uart_init(unsigned long);
void uart_putc(char);
char uart_getc(void);
void uart_print_str(char *);
/interconnect.h
0,0 → 1,17
#ifndef _INTERCONNECT_H_
#define _INTERCONNECT_H_
 
#define UART_BASE 0x90000000
#define UART_IRQ 2
#define ETH_BASE 0x92000000
#define ETH_IRQ 4
#define I2C_BASE 0x9D000000
#define I2C_IRQ 3
#define CAN_BASE 0x94000000
#define CAN_IRQ 5
#define JSP_BASE 0x9E000000
#define JSP_IRQ 6
 
#define SPI_BASE 0xa0000000
 
#endif
/can.c
1,5 → 1,5
#include <board.h>
#include <support.h>
#include "interconnect.h"
#include "can.h"
 
int can_rx_done, can_tx_done;
/uart.c
6,47 → 6,49
 
#define WAIT_FOR_XMITR \
do { \
lsr = REG8(UART_BASE + UART_LSR); \
lsr = REG8(uart_base + UART_LSR); \
} while ((lsr & BOTH_EMPTY) != BOTH_EMPTY)
 
#define WAIT_FOR_THRE \
do { \
lsr = REG8(UART_BASE + UART_LSR); \
lsr = REG8(uart_base + UART_LSR); \
} while ((lsr & UART_LSR_THRE) != UART_LSR_THRE)
 
#define CHECK_FOR_CHAR (REG8(UART_BASE + UART_LSR) & UART_LSR_DR)
#define CHECK_FOR_CHAR (REG8(uart_base + UART_LSR) & UART_LSR_DR)
 
#define WAIT_FOR_CHAR \
do { \
lsr = REG8(UART_BASE + UART_LSR); \
lsr = REG8(uart_base + UART_LSR); \
} while ((lsr & UART_LSR_DR) != UART_LSR_DR)
 
#define UART_TX_BUFF_LEN 32
#define UART_TX_BUFF_MASK (UART_TX_BUFF_LEN -1)
 
static unsigned long uart_base = 0;
 
char tx_buff[UART_TX_BUFF_LEN];
volatile int tx_level, rx_level;
 
void uart_init(void)
void uart_init(unsigned long base)
{
int divisor;
 
uart_base = base;
/* Reset receiver and transmiter */
/* Set RX interrupt for each byte */
REG8(UART_BASE + UART_FCR) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_1;
REG8(uart_base + UART_FCR) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_1;
 
/* Enable RX interrupt */
REG8(UART_BASE + UART_IER) = UART_IER_RDI | UART_IER_THRI;
REG8(uart_base + UART_IER) = UART_IER_RDI | UART_IER_THRI;
 
/* Set 8 bit char, 1 stop bit, no parity */
REG8(UART_BASE + UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP | UART_LCR_PARITY);
REG8(uart_base + UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP | UART_LCR_PARITY);
 
/* Set baud rate */
divisor = IN_CLK/(16 * UART_BAUD_RATE);
REG8(UART_BASE + UART_LCR) |= UART_LCR_DLAB;
REG8(UART_BASE + UART_DLM) = (divisor >> 8) & 0x000000ff;
REG8(UART_BASE + UART_DLL) = divisor & 0x000000ff;
REG8(UART_BASE + UART_LCR) &= ~(UART_LCR_DLAB);
REG8(uart_base + UART_LCR) |= UART_LCR_DLAB;
REG8(uart_base + UART_DLM) = (divisor >> 8) & 0x000000ff;
REG8(uart_base + UART_DLL) = divisor & 0x000000ff;
REG8(uart_base + UART_LCR) &= ~(UART_LCR_DLAB);
 
return;
}
56,7 → 58,7
unsigned char lsr;
 
WAIT_FOR_THRE;
REG8(UART_BASE + UART_TX) = c;
REG8(uart_base + UART_TX) = c;
WAIT_FOR_XMITR;
}
 
65,7 → 67,7
char uart_getc()
{
char c;
c = REG8(UART_BASE + UART_RX);
c = REG8(uart_base + UART_RX);
return c;
}
 
74,7 → 76,7
{
char lala;
unsigned char interrupt_id;
interrupt_id = REG8(UART_BASE + UART_IIR);
interrupt_id = REG8(uart_base + UART_IIR);
if ( interrupt_id & UART_IIR_RDI )
{
lala = uart_getc();
/i2c.c
1,5 → 1,5
#include <board.h>
#include <support.h>
#include "interconnect.h"
#include "i2c.h"
 
int i2c_rd_done, i2c_wr_done;

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