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URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /minsoc/trunk
    from Rev 103 to Rev 104
    Reverse comparison

Rev 103 → Rev 104

/sim/run/generate_bench
1,2 → 1,2
#!/bin/sh
iverilog -c ../../prj/sim/minsoc.src -o minsoc_bench
iverilog -c ../../prj/sim/minsoc_verilog.src -o minsoc_bench
/sim/modelsim/compile_design.bat
1,4 → 1,5
@echo off
vlog -incr -work minsoc -f ../../prj/sim/minsoc.src
vlog -incr -work minsoc -f ../../prj/sim/minsoc_verilog.src
::vcom -work minsoc -f ../../prj/sim/minsoc_vhdl.src
echo Finished...
set /p exit=Press ENTER to close this window...
/sim/modelsim/compile_design.sh
1,3 → 1,4
#!/bin/bash
 
vlog -incr -work minsoc -f ../../prj/sim/minsoc.src
vlog -incr -work minsoc -f ../../prj/sim/minsoc_verilog.src
#vcom -work minsoc -f ../../prj/sim/minsoc_vhdl.src
/prj/scripts/simprj.sh File deleted
prj/scripts/simprj.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: prj/scripts/simvhdl.sh =================================================================== --- prj/scripts/simvhdl.sh (nonexistent) +++ prj/scripts/simvhdl.sh (revision 104) @@ -0,0 +1,43 @@ +#!/bin/bash + +#system workings +MINSOC_DIR=`pwd`/.. + +PROJECT=$1 +OUTPUT=$2 + +if [ ! -f $PROJECT ] +then + echo "Unexistent project file." + exit 1 +fi + +if [ -z "$OUTPUT" ] +then + echo "Second argument should be the destintion file for the file and directory inclusions." + exit 1 +fi +echo -n "" > $OUTPUT + +source $PROJECT + +for file in "${PROJECT_SRC[@]}" +do + FOUND=0 + + for dir in "${PROJECT_DIR[@]}" + do + if [ -f $MINSOC_DIR/$dir/$file ] + then + echo "$MINSOC_DIR/$dir/$file" >> $OUTPUT + FOUND=1 + break + fi + done + + if [ $FOUND != 1 ] + then + echo "FILE NOT FOUND" + exit 1 + fi +done
prj/scripts/simvhdl.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: prj/scripts/simverilog.sh =================================================================== --- prj/scripts/simverilog.sh (nonexistent) +++ prj/scripts/simverilog.sh (revision 104) @@ -0,0 +1,48 @@ +#!/bin/bash + +#system workings +MINSOC_DIR=`pwd`/.. + +PROJECT=$1 +OUTPUT=$2 + +if [ ! -f $PROJECT ] +then + echo "Unexistent project file." + exit 1 +fi + +if [ -z "$OUTPUT" ] +then + echo "Second argument should be the destintion file for the file and directory inclusions." + exit 1 +fi +echo -n "" > $OUTPUT + +source $PROJECT + +for dir in "${PROJECT_DIR[@]}" +do + echo "+incdir+$MINSOC_DIR/$dir" >> $OUTPUT +done + +for file in "${PROJECT_SRC[@]}" +do + FOUND=0 + + for dir in "${PROJECT_DIR[@]}" + do + if [ -f $MINSOC_DIR/$dir/$file ] + then + echo "$MINSOC_DIR/$dir/$file" >> $OUTPUT + FOUND=1 + break + fi + done + + if [ $FOUND != 1 ] + then + echo "FILE NOT FOUND" + exit 1 + fi +done
prj/scripts/simverilog.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: prj/Makefile =================================================================== --- prj/Makefile (revision 103) +++ prj/Makefile (revision 104) @@ -1,5 +1,7 @@ -PROJECTS = minsoc_bench.prj minsoc_top.prj or1200_top.prj adbg_top.prj jtag_top.prj uart_top.prj ethmac.prj altera_virtual_jtag.prj +VERILOG_PROJECTS = minsoc_bench.prj minsoc_top.prj or1200_top.prj adbg_top.prj jtag_top.prj uart_top.prj ethmac.prj +VHDL_PROJECTS = altera_virtual_jtag.prj +PROJECTS = $(VERILOG_PROJECTS) $(VHDL_PROJECTS) SRC_DIR = src SCRIPTS_DIR = scripts @@ -7,15 +9,16 @@ XILINX_DIR = xilinx ALTERA_DIR = altera -SIMULATION_FILES = $(addprefix $(SIMULATION_DIR)/, $(addsuffix .src, $(basename $(PROJECTS)))) +SIM_VERILOG_FILES = $(addprefix $(SIMULATION_DIR)/, $(addsuffix .verilog, $(basename $(VERILOG_PROJECTS)))) +SIM_VHDL_FILES = $(addprefix $(SIMULATION_DIR)/, $(addsuffix .vhdl, $(basename $(VHDL_PROJECTS)))) XILINX_PRJ_FILES = $(addprefix $(XILINX_DIR)/, $(addsuffix .prj, $(basename $(PROJECTS)))) XILINX_XST_FILES = $(addprefix $(XILINX_DIR)/, $(addsuffix .xst, $(basename $(PROJECTS)))) ALTERA_PRJ_FILES = $(addprefix $(ALTERA_DIR)/, $(addsuffix .prj, $(basename $(PROJECTS)))) -all: $(SIMULATION_DIR)/minsoc.src $(XILINX_PRJ_FILES) $(XILINX_XST_FILES) $(ALTERA_PRJ_FILES) +all: $(SIMULATION_DIR)/minsoc_verilog.src $(SIMULATION_DIR)/minsoc_vhdl.src $(XILINX_PRJ_FILES) $(XILINX_XST_FILES) $(ALTERA_PRJ_FILES) clean: - rm -rf $(SIMULATION_DIR)/*.src $(XILINX_DIR)/*.prj $(XILINX_DIR)/*.xst $(ALTERA_DIR)/*.prj + rm -rf $(SIMULATION_DIR)/*.verilog $(SIMULATION_DIR)/*.vhdl $(SIMULATION_DIR)/*.src $(XILINX_DIR)/*.prj $(XILINX_DIR)/*.xst $(ALTERA_DIR)/*.prj $(XILINX_DIR)/minsoc_top.xst: $(SRC_DIR)/minsoc_top.prj bash $(SCRIPTS_DIR)/xilinxxst.sh $^ $@ minsoc_top.prj minsoc_top topmodule @@ -32,9 +35,15 @@ $(ALTERA_DIR)/%.prj: $(SRC_DIR)/%.prj bash $(SCRIPTS_DIR)/altprj.sh $^ $@ -$(SIMULATION_DIR)/minsoc.src: $(SIMULATION_FILES) - cat $(SIMULATION_FILES) > $(SIMULATION_DIR)/minsoc.src +$(SIMULATION_DIR)/minsoc_verilog.src: $(SIM_VERILOG_FILES) + cat $(SIM_VERILOG_FILES) > $(SIMULATION_DIR)/minsoc_verilog.src -$(SIMULATION_DIR)/%.src: $(SRC_DIR)/%.prj - bash $(SCRIPTS_DIR)/simprj.sh $^ $@ +$(SIMULATION_DIR)/minsoc_vhdl.src: $(SIM_VHDL_FILES) + cat $(SIM_VHDL_FILES) > $(SIMULATION_DIR)/minsoc_vhdl.src +$(SIMULATION_DIR)/%.verilog: $(SRC_DIR)/%.prj + bash $(SCRIPTS_DIR)/simverilog.sh $^ $@ + +$(SIMULATION_DIR)/%.vhdl: $(SRC_DIR)/%.prj + bash $(SCRIPTS_DIR)/simvhdl.sh $^ $@ +

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