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/bench/verilog/eth_phy_defines.v
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bench/verilog/eth_phy_defines.v
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Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: bench/verilog/eth_phy.v
===================================================================
--- bench/verilog/eth_phy.v (revision 16)
+++ bench/verilog/eth_phy.v (nonexistent)
@@ -1,1459 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// File name: eth_phy.v ////
-//// ////
-//// This file is part of the Ethernet IP core project ////
-//// http://www.opencores.org/projects/ethmac/ ////
-//// ////
-//// Author(s): ////
-//// - Tadej Markovic, tadej@opencores.org ////
-//// ////
-//// All additional information is available in the README.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2002 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: eth_phy.v,v $
-// Revision 1.8 2003/01/22 19:40:09 tadejm
-// Backup version. Not fully working.
-//
-// Revision 1.7 2002/10/18 13:58:22 tadejm
-// Some code changed due to bug fixes.
-//
-// Revision 1.6 2002/10/09 13:16:51 tadejm
-// Just back-up; not completed testbench and some testcases are not
-// wotking properly yet.
-//
-// Revision 1.5 2002/09/18 17:55:08 tadej
-// Bug repaired in eth_phy device
-//
-// Revision 1.3 2002/09/13 14:50:15 mohor
-// Bug in MIIM fixed.
-//
-// Revision 1.2 2002/09/13 12:29:14 mohor
-// Headers changed.
-//
-// Revision 1.1 2002/09/13 11:57:20 mohor
-// New testbench. Thanks to Tadej M - "The Spammer".
-//
-//
-//
-
-`include "timescale.v"
-`include "eth_phy_defines.v"
-`include "tb_eth_defines.v"
-module eth_phy // This PHY model simulate simplified Intel LXT971A PHY
-(
- // COMMON
- m_rst_n_i,
-
- // MAC TX
- mtx_clk_o,
- mtxd_i,
- mtxen_i,
- mtxerr_i,
-
- // MAC RX
- mrx_clk_o,
- mrxd_o,
- mrxdv_o,
- mrxerr_o,
-
- mcoll_o,
- mcrs_o,
-
- // MIIM
- mdc_i,
- md_io,
-
- // SYSTEM
- phy_log
-);
-
-//////////////////////////////////////////////////////////////////////
-//
-// Input/output signals
-//
-//////////////////////////////////////////////////////////////////////
-
-// MAC miscellaneous signals
-input m_rst_n_i;
-// MAC TX signals
-output mtx_clk_o;
-input [3:0] mtxd_i;
-input mtxen_i;
-input mtxerr_i;
-// MAC RX signals
-output mrx_clk_o;
-output [3:0] mrxd_o;
-output mrxdv_o;
-output mrxerr_o;
-// MAC common signals
-output mcoll_o;
-output mcrs_o;
-// MAC management signals
-input mdc_i;
-inout md_io;
-// SYSTEM
-input [31:0] phy_log;
-
-
-//////////////////////////////////////////////////////////////////////
-//
-// PHY management (MIIM) REGISTER definitions
-//
-//////////////////////////////////////////////////////////////////////
-//
-// Supported registers:
-//
-// Addr | Register Name
-//--------------------------------------------------------------------
-// 0 | Control reg. |
-// 1 | Status reg. #1 |--> normal operation
-// 2 | PHY ID reg. 1 |
-// 3 | PHY ID reg. 2 |
-//----------------------
-// Addr | Data MEMORY |--> for testing
-//
-//--------------------------------------------------------------------
-//
-// Control register
-reg control_bit15; // self clearing bit
-reg [14:10] control_bit14_10;
-reg control_bit9; // self clearing bit
-reg [8:0] control_bit8_0;
-// Status register
-wire [15:9] status_bit15_9 = `SUPPORTED_SPEED_AND_PORT;
-wire status_bit8 = `EXTENDED_STATUS;
-wire status_bit7 = 1'b0; // reserved
-reg [6:0] status_bit6_0;
-// PHY ID register 1
-wire [15:0] phy_id1 = `PHY_ID1;
-// PHY ID register 2
-wire [15:0] phy_id2 = {`PHY_ID2, `MAN_MODEL_NUM, `MAN_REVISION_NUM};
-//--------------------------------------------------------------------
-//
-// Data MEMORY
-reg [15:0] data_mem [0:31]; // 32 locations of 16-bit data width
-//
-//////////////////////////////////////////////////////////////////////
-
-
-//////////////////////////////////////////////////////////////////////
-//
-// PHY clocks - RX & TX
-//
-//////////////////////////////////////////////////////////////////////
-
-reg mtx_clk_o;
-reg mrx_clk_o;
-
-// random generator for a RX period when link is down
-real rx_link_down_halfperiod;
-
-always@(status_bit6_0[2])
-begin
- if (!status_bit6_0[2]) // Link is down
- begin
- #1 rx_link_down_halfperiod = ({$random} % 243) + 13;
- `ifdef VERBOSE
- #1 $fdisplay(phy_log, " (%0t)(%m)MAC RX clock is %f MHz while ethernet link is down!",
- $time, (1000/(rx_link_down_halfperiod*2)) );
- `endif
- end
-end
-
-`ifdef VERBOSE
-always@(status_bit6_0[2])
-begin
- if (!status_bit6_0[2]) // Link is down
- #1 $fdisplay(phy_log, " (%0t)(%m)Ethernet link is down!", $time);
- else
- #1 $fdisplay(phy_log, " (%0t)(%m)Ethernet link is up!", $time);
-end
-`endif
-
-// speed selection signal eth_speed: 1'b1 - 100 Mbps, 1'b0 - 10 Mbps
-wire eth_speed;
-
-assign eth_speed = ( (control_bit14_10[13]) && !((`LED_CFG1) && (`LED_CFG2)) );
-
-`ifdef VERBOSE
-always@(eth_speed)
-begin
- if (eth_speed)
- #1 $fdisplay(phy_log, " (%0t)(%m)PHY configured to 100 Mbps!", $time);
- else
- #1 $fdisplay(phy_log, " (%0t)(%m)PHY configured tp 10 Mbps!", $time);
-end
-`endif
-
-// different clock calculation between RX and TX, so that there is alsways a litle difference
-/*initial
-begin
- set_mrx_equal_mtx = 1; // default
-end*/
-
-always
-begin
- mtx_clk_o = 0;
- #7;
- forever
- begin
- if (eth_speed) // 100 Mbps - 25 MHz, 40 ns
- begin
- #20 mtx_clk_o = ~mtx_clk_o;
- end
- else // 10 Mbps - 2.5 MHz, 400 ns
- begin
- #200 mtx_clk_o = ~mtx_clk_o;
- end
- end
-end
-
-always
-begin
- // EQUAL mrx_clk to mtx_clk
- mrx_clk_o = 0;
- #7;
- forever
- begin
- if (eth_speed) // 100 Mbps - 25 MHz, 40 ns
- begin
- #20 mrx_clk_o = ~mrx_clk_o;
- end
- else // 10 Mbps - 2.5 MHz, 400 ns
- begin
- #200 mrx_clk_o = ~mrx_clk_o;
- end
- end
- // DIFFERENT mrx_clk than mtx_clk
-/* mrx_clk_diff_than_mtx = 1;
- #3;
- forever
- begin
- if (status_bit6_0[2]) // Link is UP
- begin
- if (eth_speed) // 100 Mbps - 25 MHz, 40 ns
- begin
- //#(((1/0.025001)/2))
- #19.99 mrx_clk_diff_than_mtx = ~mrx_clk_diff_than_mtx; // period is calculated from frequency in GHz
- end
- else // 10 Mbps - 2.5 MHz, 400 ns
- begin
- //#(((1/0.0024999)/2))
- #200.01 mrx_clk_diff_than_mtx = ~mrx_clk_diff_than_mtx; // period is calculated from frequency in GHz
- end
- end
- else // Link is down
- begin
- #(rx_link_down_halfperiod) mrx_clk_diff_than_mtx = ~mrx_clk_diff_than_mtx; // random frequency between 2 MHz and 40 MHz
- end
- end*/
-// // set output mrx_clk
-// if (set_mrx_equal_mtx)
-// mrx_clk_o = mrx_clk_equal_to_mtx;
-// else
-// mrx_clk_o = mrx_clk_diff_than_mtx;
-end
-
-// set output mrx_clk
-//assign mrx_clk_o = set_mrx_equal_mtx ? mrx_clk_equal_to_mtx : mrx_clk_diff_than_mtx ;
-
-//////////////////////////////////////////////////////////////////////
-//
-// PHY management (MIIM) interface
-//
-//////////////////////////////////////////////////////////////////////
-reg respond_to_all_phy_addr; // PHY will respond to all phy addresses
-reg no_preamble; // PHY responds to frames without preamble
-
-integer md_transfer_cnt; // counter countes the value of whole data transfer
-reg md_transfer_cnt_reset; // for reseting the counter
-reg md_io_reg; // registered input
-reg md_io_output; // registered output
-reg md_io_rd_wr; // op-code latched (read or write)
-reg md_io_enable; // output enable
-reg [4:0] phy_address; // address of PHY device
-reg [4:0] reg_address; // address of a register
-reg md_get_phy_address; // for shifting PHY address in
-reg md_get_reg_address; // for shifting register address in
-reg [15:0] reg_data_in; // data to be written in a register
-reg md_get_reg_data_in; // for shifting data in
-reg md_put_reg_data_in; // for storing data into a selected register
-reg [15:0] reg_data_out; // data to be read from a register
-reg md_put_reg_data_out; // for registering data from a selected register
-
-wire [15:0] register_bus_in; // data bus to a selected register
-reg [15:0] register_bus_out; // data bus from a selected register
-
-initial
-begin
- md_io_enable = 1'b0;
- respond_to_all_phy_addr = 1'b0;
- no_preamble = 1'b0;
-end
-
-// tristate output
-assign #1 md_io = (m_rst_n_i && md_io_enable) ? md_io_output : 1'bz ;
-
-// registering input
-always@(posedge mdc_i or negedge m_rst_n_i)
-begin
- if (!m_rst_n_i)
- md_io_reg <= #1 0;
- else
- md_io_reg <= #1 md_io;
-end
-
-// getting (shifting) PHY address, Register address and Data in
-// putting Data out and shifting
-always@(posedge mdc_i or negedge m_rst_n_i)
-begin
- if (!m_rst_n_i)
- begin
- phy_address <= 0;
- reg_address <= 0;
- reg_data_in <= 0;
- reg_data_out <= 0;
- md_io_output <= 0;
- end
- else
- begin
- if (md_get_phy_address)
- begin
- phy_address[4:1] <= phy_address[3:0]; // correct address is `ETH_PHY_ADDR
- phy_address[0] <= md_io;
- end
- if (md_get_reg_address)
- begin
- reg_address[4:1] <= reg_address[3:0];
- reg_address[0] <= md_io;
- end
- if (md_get_reg_data_in)
- begin
- reg_data_in[15:1] <= reg_data_in[14:0];
- reg_data_in[0] <= md_io;
- end
- if (md_put_reg_data_out)
- begin
- reg_data_out <= register_bus_out;
- end
- if (md_io_enable)
- begin
- md_io_output <= reg_data_out[15];
- reg_data_out[15:1] <= reg_data_out[14:0];
- reg_data_out[0] <= 1'b0;
- end
- end
-end
-
-assign #1 register_bus_in = reg_data_in; // md_put_reg_data_in - allows writing to a selected register
-
-// counter for transfer to and from MIIM
-always@(posedge mdc_i or negedge m_rst_n_i)
-begin
- if (!m_rst_n_i)
- begin
- if (no_preamble)
- md_transfer_cnt <= 33;
- else
- md_transfer_cnt <= 1;
- end
- else
- begin
- if (md_transfer_cnt_reset)
- begin
- if (no_preamble)
- md_transfer_cnt <= 33;
- else
- md_transfer_cnt <= 1;
- end
- else if (md_transfer_cnt < 64)
- begin
- md_transfer_cnt <= md_transfer_cnt + 1'b1;
- end
- else
- begin
- if (no_preamble)
- md_transfer_cnt <= 33;
- else
- md_transfer_cnt <= 1;
- end
- end
-end
-
-// MIIM transfer control
-always@(m_rst_n_i or md_transfer_cnt or md_io_reg or md_io_rd_wr or
- phy_address or respond_to_all_phy_addr or no_preamble)
-begin
- #1;
- while ((m_rst_n_i) && (md_transfer_cnt <= 64))
- begin
- // reset the signal - put registered data in the register (when write)
- // check preamble
- if (md_transfer_cnt < 33)
- begin
- #4 md_put_reg_data_in = 1'b0;
- if (md_io_reg !== 1'b1)
- begin
- #1 md_transfer_cnt_reset = 1'b1;
- end
- else
- begin
- #1 md_transfer_cnt_reset = 1'b0;
- end
- end
-
- // check start bits
- else if (md_transfer_cnt == 33)
- begin
- if (no_preamble)
- begin
- #4 md_put_reg_data_in = 1'b0;
- if (md_io_reg === 1'b0)
- begin
- #1 md_transfer_cnt_reset = 1'b0;
- end
- else
- begin
- #1 md_transfer_cnt_reset = 1'b1;
- //if ((md_io_reg !== 1'bz) && (md_io_reg !== 1'b1))
- if (md_io_reg !== 1'bz)
- begin
- // ERROR - start !
- `ifdef VERBOSE
- $fdisplay(phy_log, "*E (%0t)(%m)MIIM - wrong first start bit (without preamble)", $time);
- `endif
- #10 $stop;
- end
- end
- end
- else // with preamble
- begin
- #4 ;
- `ifdef VERBOSE
- $fdisplay(phy_log, " (%0t)(%m)MIIM - 32-bit preamble received", $time);
- `endif
- // check start bit only if md_transfer_cnt_reset is inactive, because if
- // preamble suppression was changed start bit should not be checked
- if ((md_io_reg !== 1'b0) && (md_transfer_cnt_reset == 1'b0))
- begin
- // ERROR - start !
- `ifdef VERBOSE
- $fdisplay(phy_log, "*E (%0t)(%m)MIIM - wrong first start bit", $time);
- `endif
- #10 $stop;
- end
- end
- end
-
- else if (md_transfer_cnt == 34)
- begin
- #4;
- if (md_io_reg !== 1'b1)
- begin
- // ERROR - start !
- #1;
- `ifdef VERBOSE
- if (no_preamble)
- $fdisplay(phy_log, "*E (%0t)(%m)MIIM - wrong second start bit (without preamble)", $time);
- else
- $fdisplay(phy_log, "*E (%0t)(%m)MIIM - wrong second start bit", $time);
- `endif
- #10 $stop;
- end
- else
- begin
- `ifdef VERBOSE
- if (no_preamble)
- #1 $fdisplay(phy_log, " (%0t)(%m)MIIM - 2 start bits received (without preamble)", $time);
- else
- #1 $fdisplay(phy_log, " (%0t)(%m)MIIM - 2 start bits received", $time);
- `endif
- end
- end
-
- // register the op-code (rd / wr)
- else if (md_transfer_cnt == 35)
- begin
- #4;
- if (md_io_reg === 1'b1)
- begin
- #1 md_io_rd_wr = 1'b1;
- end
- else
- begin
- #1 md_io_rd_wr = 1'b0;
- end
- end
-
- else if (md_transfer_cnt == 36)
- begin
- #4;
- if ((md_io_reg === 1'b0) && (md_io_rd_wr == 1'b1))
- begin
- #1 md_io_rd_wr = 1'b1; // reading from PHY registers
- `ifdef VERBOSE
- $fdisplay(phy_log, " (%0t)(%m)MIIM - op-code for READING from registers", $time);
- `endif
- end
- else if ((md_io_reg === 1'b1) && (md_io_rd_wr == 1'b0))
- begin
- #1 md_io_rd_wr = 1'b0; // writing to PHY registers
- `ifdef VERBOSE
- $fdisplay(phy_log, " (%0t)(%m)MIIM - op-code for WRITING to registers", $time);
- `endif
- end
- else
- begin
- // ERROR - wrong opcode !
- `ifdef VERBOSE
- #1 $fdisplay(phy_log, "*E (%0t)(%m)MIIM - wrong OP-CODE", $time);
- `endif
- #10 $stop;
- end
- // set the signal - get PHY address
- begin
- #1 md_get_phy_address = 1'b1;
- end
- end
-
- // reset the signal - get PHY address
- else if (md_transfer_cnt == 41)
- begin
- #4 md_get_phy_address = 1'b0;
- // set the signal - get register address
- #1 md_get_reg_address = 1'b1;
- end
-
- // reset the signal - get register address
- // set the signal - put register data to output register
- else if (md_transfer_cnt == 46)
- begin
- #4 md_get_reg_address = 1'b0;
- #1 md_put_reg_data_out = 1'b1;
- end
-
- // reset the signal - put register data to output register
- // set the signal - enable md_io as output when read
- else if (md_transfer_cnt == 47)
- begin
- #4 md_put_reg_data_out = 1'b0;
- if (md_io_rd_wr) //read
- begin
- if (md_io_reg !== 1'bz)
- begin
- // ERROR - turn around !
- `ifdef VERBOSE
- #1 $fdisplay(phy_log, "*E (%0t)(%m)MIIM - wrong turn-around cycle before reading data out", $time);
- `endif
- #10 $stop;
- end
- if ((phy_address === `ETH_PHY_ADDR) || respond_to_all_phy_addr) // check the PHY address
- begin
- #1 md_io_enable = 1'b1;
- `ifdef VERBOSE
- $fdisplay(phy_log, " (%0t)(%m)MIIM - received correct PHY ADDRESS: %x", $time, phy_address);
- `endif
- end
- else
- begin
- `ifdef VERBOSE
- #1 $fdisplay(phy_log, "*W (%0t)(%m)MIIM - received different PHY ADDRESS: %x", $time, phy_address);
- `endif
- end
- end
- else // write
- begin
- #1 md_io_enable = 1'b0;
- // check turn around cycle when write on clock 47
- if (md_io_reg !== 1'b1)
- begin
- // ERROR - turn around !
- `ifdef VERBOSE
- #1 $fdisplay(phy_log, "*E (%0t)(%m)MIIM - wrong 1. turn-around cycle before writing data in",
- $time);
- `endif
- #10 $stop;
- end
- end
- end
-
- // set the signal - get register data in when write
- else if (md_transfer_cnt == 48)
- begin
- #4;
- if (!md_io_rd_wr) // write
- begin
- #1 md_get_reg_data_in = 1'b1;
- // check turn around cycle when write on clock 48
- if (md_io_reg !== 1'b0)
- begin
- // ERROR - turn around !
- `ifdef VERBOSE
- #1 $fdisplay(phy_log, "*E (%0t)(%m)MIIM - wrong 2. turn-around cycle before writing data in",
- $time);
- `endif
- #10 $stop;
- end
- end
- else // read
- begin
- #1 md_get_reg_data_in = 1'b0;
- end
- end
-
- // reset the signal - enable md_io as output when read
- // reset the signal - get register data in when write
- // set the signal - put registered data in the register when write
- else if (md_transfer_cnt == 64)
- begin
- #1 md_io_enable = 1'b0;
- #4 md_get_reg_data_in = 1'b0;
- if (!md_io_rd_wr) // write
- begin
- if ((phy_address === `ETH_PHY_ADDR) || respond_to_all_phy_addr) // check the PHY address
- begin
- #1 md_put_reg_data_in = 1'b1;
- `ifdef VERBOSE
- $fdisplay(phy_log, " (%0t)(%m)MIIM - received correct PHY ADDRESS: %x", $time, phy_address);
- $fdisplay(phy_log, " (%0t)(%m)MIIM - WRITING to register %x COMPLETED!", $time, reg_address);
- `endif
- end
- else
- begin
- `ifdef VERBOSE
- #1 $fdisplay(phy_log, "*W (%0t)(%m)MIIM - received different PHY ADDRESS: %x", $time, phy_address);
- $fdisplay(phy_log, "*W (%0t)(%m)MIIM - NO WRITING to register %x !", $time, reg_address);
- `endif
- end
- end
- else // read
- begin
- `ifdef VERBOSE
- if ((phy_address === `ETH_PHY_ADDR) || respond_to_all_phy_addr) // check the PHY address
- #1 $fdisplay(phy_log, " (%0t)(%m)MIIM - READING from register %x COMPLETED!",
- $time, reg_address);
- else
- #1 $fdisplay(phy_log, "*W (%0t)(%m)MIIM - NO READING from register %x !", $time, reg_address);
- `endif
- end
- end
-
- // wait for one clock period
- @(posedge mdc_i)
- #1;
- end
-end
-
-//====================================================================
-//
-// PHY management (MIIM) REGISTERS
-//
-//====================================================================
-//
-// Supported registers (normal operation):
-//
-// Addr | Register Name
-//--------------------------------------------------------------------
-// 0 | Control reg.
-// 1 | Status reg. #1
-// 2 | PHY ID reg. 1
-// 3 | PHY ID reg. 2
-//----------------------
-// Addr | Data MEMORY |--> for testing
-//
-//--------------------------------------------------------------------
-//
-// Control register
-// reg control_bit15; // self clearing bit
-// reg [14:10] control_bit14_10;
-// reg control_bit9; // self clearing bit
-// reg [8:0] control_bit8_0;
-// Status register
-// wire [15:9] status_bit15_9 = `SUPPORTED_SPEED_AND_PORT;
-// wire status_bit8 = `EXTENDED_STATUS;
-// wire status_bit7 = 1'b0; // reserved
-// reg [6:0] status_bit6_0 = `DEFAULT_STATUS;
-// PHY ID register 1
-// wire [15:0] phy_id1 = `PHY_ID1;
-// PHY ID register 2
-// wire [15:0] phy_id2 = {`PHY_ID2, `MAN_MODEL_NUM, `MAN_REVISION_NUM};
-//--------------------------------------------------------------------
-//
-// Data MEMORY
-// reg [15:0] data_mem [0:31]; // 32 locations of 16-bit data width
-//
-//====================================================================
-
-//////////////////////////////////////////////////////////////////////
-//
-// PHY management (MIIM) REGISTER control
-//
-//////////////////////////////////////////////////////////////////////
-
-// wholy writable registers for walking ONE's on data, phy and reg. addresses
-reg registers_addr_data_test_operation;
-
-// Non writable status registers
-initial // always
-begin
- #1 status_bit6_0[6] = no_preamble;
- status_bit6_0[5] = 1'b0;
- status_bit6_0[3] = 1'b1;
- status_bit6_0[0] = 1'b1;
-end
-always@(posedge mrx_clk_o)
-begin
- status_bit6_0[4] <= #1 1'b0;
- status_bit6_0[1] <= #1 1'b0;
-end
-initial
-begin
- status_bit6_0[2] = 1'b1;
- registers_addr_data_test_operation = 0;
-end
-
-// Reading from a selected registers
-always@(reg_address or registers_addr_data_test_operation or md_put_reg_data_out or
- control_bit15 or control_bit14_10 or control_bit9 or control_bit8_0 or
- status_bit15_9 or status_bit8 or status_bit7 or status_bit6_0 or
- phy_id1 or phy_id2)
-begin
- if (registers_addr_data_test_operation) // test operation
- begin
- if (md_put_reg_data_out) // read enable
- begin
- register_bus_out = #1 data_mem[reg_address];
- end
- end
- else // normal operation
- begin
- if (md_put_reg_data_out) // read enable
- begin
- case (reg_address)
- 5'h0: register_bus_out = #1 {control_bit15, control_bit14_10, control_bit9, control_bit8_0};
- 5'h1: register_bus_out = #1 {status_bit15_9, status_bit8, status_bit7, status_bit6_0};
- 5'h2: register_bus_out = #1 phy_id1;
- 5'h3: register_bus_out = #1 phy_id2;
- default: register_bus_out = #1 16'hDEAD;
- endcase
- end
- end
-end
-
-// Self clear control signals
-reg self_clear_d0;
-reg self_clear_d1;
-reg self_clear_d2;
-reg self_clear_d3;
-// Self clearing control
-always@(posedge mdc_i or negedge m_rst_n_i)
-begin
- if (!m_rst_n_i)
- begin
- self_clear_d0 <= #1 0;
- self_clear_d1 <= #1 0;
- self_clear_d2 <= #1 0;
- self_clear_d3 <= #1 0;
- end
- else
- begin
- self_clear_d0 <= #1 md_put_reg_data_in;
- self_clear_d1 <= #1 self_clear_d0;
- self_clear_d2 <= #1 self_clear_d1;
- self_clear_d3 <= #1 self_clear_d2;
- end
-end
-
-// Writing to a selected register
-always@(posedge mdc_i or negedge m_rst_n_i)
-begin
- if ((!m_rst_n_i) || (control_bit15))
- begin
- if (!registers_addr_data_test_operation) // normal operation
- begin
- control_bit15 <= #1 0;
- control_bit14_10 <= #1 {1'b0, (`LED_CFG1 || `LED_CFG2), `LED_CFG1, 2'b0};
- control_bit9 <= #1 0;
- control_bit8_0 <= #1 {`LED_CFG3, 8'b0};
- end
- end
- else
- begin
- if (registers_addr_data_test_operation) // test operation
- begin
- if (md_put_reg_data_in)
- begin
- data_mem[reg_address] <= #1 register_bus_in[15:0];
- end
- end
- else // normal operation
- begin
- // bits that are normaly written
- if (md_put_reg_data_in)
- begin
- case (reg_address)
- 5'h0:
- begin
- control_bit14_10 <= #1 register_bus_in[14:10];
- control_bit8_0 <= #1 register_bus_in[8:0];
- end
- default:
- begin
- end
- endcase
- end
- // self cleared bits written
- if ((md_put_reg_data_in) && (reg_address == 5'h0))
- begin
- control_bit15 <= #1 register_bus_in[15];
- control_bit9 <= #1 register_bus_in[9];
- end
- else if (self_clear_d3) // self cleared bits cleared
- begin
- control_bit15 <= #1 1'b0;
- control_bit9 <= #1 1'b0;
- end
- end
- end
-end
-
-//////////////////////////////////////////////////////////////////////
-//
-// PHY <-> MAC control (RX and TX clocks are at the begining)
-//
-//////////////////////////////////////////////////////////////////////
-
-// CARRIER SENSE & COLLISION
-
-// MAC common signals
-reg mcoll_o;
-reg mcrs_o;
-// Internal signals controling Carrier sense & Collision
- // MAC common signals generated when appropriate transfer
-reg mcrs_rx;
-reg mcrs_tx;
- // delayed mtxen_i signal for generating delayed tx carrier sense
-reg mtxen_d1;
-reg mtxen_d2;
-reg mtxen_d3;
-reg mtxen_d4;
-reg mtxen_d5;
-reg mtxen_d6;
- // collision signal set or rest within task for controling collision
-reg task_mcoll;
- // carrier sense signal set or rest within task for controling carrier sense
-reg task_mcrs;
-reg task_mcrs_lost;
- // do not generate collision in half duplex - not normal operation
-reg no_collision_in_half_duplex;
- // generate collision in full-duplex mode also - not normal operation
-reg collision_in_full_duplex;
- // do not generate carrier sense in half duplex mode - not normal operation
-reg no_carrier_sense_in_tx_half_duplex;
-reg no_carrier_sense_in_rx_half_duplex;
- // generate carrier sense during TX in full-duplex mode also - not normal operation
-reg carrier_sense_in_tx_full_duplex;
- // do not generate carrier sense during RX in full-duplex mode - not normal operation
-reg no_carrier_sense_in_rx_full_duplex;
- // on RX: delay after carrier sense signal; on TX: carrier sense delayed (delay is one clock period)
-reg real_carrier_sense;
-
-initial
-begin
- mcrs_rx = 0;
- mcrs_tx = 0;
- task_mcoll = 0;
- task_mcrs = 0;
- task_mcrs_lost = 0;
- no_collision_in_half_duplex = 0;
- collision_in_full_duplex = 0;
- no_carrier_sense_in_tx_half_duplex = 0;
- no_carrier_sense_in_rx_half_duplex = 0;
- carrier_sense_in_tx_full_duplex = 0;
- no_carrier_sense_in_rx_full_duplex = 0;
- real_carrier_sense = 0;
-end
-
-// Collision
-always@(m_rst_n_i or control_bit8_0 or collision_in_full_duplex or
- mcrs_rx or mcrs_tx or task_mcoll or no_collision_in_half_duplex
- )
-begin
- if (!m_rst_n_i)
- mcoll_o = 0;
- else
- begin
- if (control_bit8_0[8]) // full duplex
- begin
- if (collision_in_full_duplex) // collision is usually not asserted in full duplex
- begin
- mcoll_o = ((mcrs_rx && mcrs_tx) || task_mcoll);
- `ifdef VERBOSE
- if (mcrs_rx && mcrs_tx)
- $fdisplay(phy_log, " (%0t)(%m) Collision set in FullDuplex!", $time);
- if (task_mcoll)
- $fdisplay(phy_log, " (%0t)(%m) Collision set in FullDuplex from TASK!", $time);
- `endif
- end
- else
- begin
- mcoll_o = task_mcoll;
- `ifdef VERBOSE
- if (task_mcoll)
- $fdisplay(phy_log, " (%0t)(%m) Collision set in FullDuplex from TASK!", $time);
- `endif
- end
- end
- else // half duplex
- begin
- mcoll_o = ((mcrs_rx && mcrs_tx && !no_collision_in_half_duplex) ||
- task_mcoll);
- `ifdef VERBOSE
- if (mcrs_rx && mcrs_tx)
- $fdisplay(phy_log, " (%0t)(%m) Collision set in HalfDuplex!", $time);
- if (task_mcoll)
- $fdisplay(phy_log, " (%0t)(%m) Collision set in HalfDuplex from TASK!", $time);
- `endif
- end
- end
-end
-
-// Carrier sense
-always@(m_rst_n_i or control_bit8_0 or carrier_sense_in_tx_full_duplex or
- no_carrier_sense_in_rx_full_duplex or
- no_carrier_sense_in_tx_half_duplex or
- no_carrier_sense_in_rx_half_duplex or
- mcrs_rx or mcrs_tx or task_mcrs or task_mcrs_lost
- )
-begin
- if (!m_rst_n_i)
- mcrs_o = 0;
- else
- begin
- if (control_bit8_0[8]) // full duplex
- begin
- if (carrier_sense_in_tx_full_duplex) // carrier sense is usually not asserted during TX in full duplex
- mcrs_o = ((mcrs_rx && !no_carrier_sense_in_rx_full_duplex) ||
- mcrs_tx || task_mcrs) && !task_mcrs_lost;
- else
- mcrs_o = ((mcrs_rx && !no_carrier_sense_in_rx_full_duplex) ||
- task_mcrs) && !task_mcrs_lost;
- end
- else // half duplex
- begin
- mcrs_o = ((mcrs_rx && !no_carrier_sense_in_rx_half_duplex) ||
- (mcrs_tx && !no_carrier_sense_in_tx_half_duplex) ||
- task_mcrs) && !task_mcrs_lost;
- end
- end
-end
-
-// MAC TX CONTROL (RECEIVING AT PHY)
-
-// storage memory for TX data received from MAC
-reg [7:0] tx_mem [0:4194303]; // 4194304 locations (22 address lines) of 8-bit data width
-reg [31:0] tx_mem_addr_in; // address for storing to TX memory
-reg [7:0] tx_mem_data_in; // data for storing to TX memory
-reg [31:0] tx_cnt; // counts nibbles
-
-// control data of a TX packet for upper layer of testbench
-reg tx_preamble_ok;
-reg tx_sfd_ok;
-// if there is a drible nibble, then tx packet is not byte aligned!
-reg tx_byte_aligned_ok;
-// complete length of TX packet (Bytes) received (without preamble and SFD)
-reg [31:0] tx_len;
-// complete length of TX packet (Bytes) received (without preamble and SFD) untill MTxErr signal was set first
-reg [31:0] tx_len_err;
-
-// TX control
-always@(posedge mtx_clk_o)
-begin
- // storing data and basic checking of frame
- if (!m_rst_n_i)
- begin
- tx_cnt <= 0;
- tx_preamble_ok <= 0;
- tx_sfd_ok <= 0;
- tx_len <= 0;
- tx_len_err <= 0;
- end
- else
- begin
- if (!mtxen_i)
- begin
- tx_cnt <= 0;
- end
- else
- begin
- // tx nibble counter
- tx_cnt <= tx_cnt + 1;
- // set initial values and check first preamble nibble
- if (tx_cnt == 0)
- begin
- `ifdef VERBOSE
- $fdisplay(phy_log, " (%0t)(%m) TX frame started with tx_en set!", $time);
- `endif
- if (mtxd_i == 4'h5)
- tx_preamble_ok <= 1;
- else
- tx_preamble_ok <= 0;
- tx_sfd_ok <= 0;
- tx_byte_aligned_ok <= 0;
- tx_len <= 0;
- tx_len_err <= 0;
-// tx_mem_addr_in <= 0;
- end
-
- // check preamble
- if ((tx_cnt > 0) && (tx_cnt <= 13))
- begin
- if ((tx_preamble_ok != 1) || (mtxd_i != 4'h5))
- tx_preamble_ok <= 0;
- end
- // check SFD
- if (tx_cnt == 14)
- begin
- `ifdef VERBOSE
- if (tx_preamble_ok == 1)
- $fdisplay(phy_log, " (%0t)(%m) TX frame preamble OK!", $time);
- else
- $fdisplay(phy_log, "*E (%0t)(%m) TX frame preamble NOT OK!", $time);
- `endif
- if (mtxd_i == 4'h5)
- tx_sfd_ok <= 1;
- else
- tx_sfd_ok <= 0;
- end
- if (tx_cnt == 15)
- begin
- if ((tx_sfd_ok != 1) || (mtxd_i != 4'hD))
- tx_sfd_ok <= 0;
- end
-
- // control for storing addresses, type/length, data and FCS to TX memory
- if (tx_cnt > 15)
- begin
- if (tx_cnt == 16)
- begin
- `ifdef VERBOSE
- if (tx_sfd_ok == 1)
- $fdisplay(phy_log, " (%0t)(%m) TX frame SFD OK!", $time);
- else
- $fdisplay(phy_log, "*E (%0t)(%m) TX frame SFD NOT OK!", $time);
- `endif
- end
-
- if (tx_cnt[0] == 0)
- begin
- tx_mem_data_in[3:0] <= mtxd_i; // storing LSB nibble
- tx_byte_aligned_ok <= 0; // if transfer will stop after this, then there was drible nibble
- end
- else
- begin
- tx_mem[tx_mem_addr_in[21:0]] <= {mtxd_i, tx_mem_data_in[3:0]}; // storing data into tx memory
- tx_len <= tx_len + 1; // enlarge byte length counter
- tx_byte_aligned_ok <= 1; // if transfer will stop after this, then transfer is byte alligned
- tx_mem_addr_in <= tx_mem_addr_in + 1'b1;
- end
-
- if (mtxerr_i)
- tx_len_err <= tx_len;
- end
- end
- end
-
- // generating CARRIER SENSE for TX with or without delay
- if (!m_rst_n_i)
- begin
- mcrs_tx <= 0;
- mtxen_d1 <= 0;
- mtxen_d2 <= 0;
- mtxen_d3 <= 0;
- mtxen_d4 <= 0;
- mtxen_d5 <= 0;
- mtxen_d6 <= 0;
- end
- else
- begin
- mtxen_d1 <= mtxen_i;
- mtxen_d2 <= mtxen_d1;
- mtxen_d3 <= mtxen_d2;
- mtxen_d4 <= mtxen_d3;
- mtxen_d5 <= mtxen_d4;
- mtxen_d6 <= mtxen_d5;
- if (real_carrier_sense)
- mcrs_tx <= mtxen_d6;
- else
- mcrs_tx <= mtxen_i;
- end
-end
-
-`ifdef VERBOSE
-reg frame_started;
-
-initial
-begin
- frame_started = 0;
-end
-always@(posedge mtxen_i)
-begin
- frame_started <= 1;
-end
-always@(negedge mtxen_i)
-begin
- if (frame_started)
- begin
- $fdisplay(phy_log, " (%0t)(%m) TX frame ended with tx_en reset!", $time);
- frame_started <= 0;
- end
-end
-
-always@(posedge mrxerr_o)
-begin
- $fdisplay(phy_log, " (%0t)(%m) RX frame ERROR signal was set!", $time);
-end
-`endif
-
-//////////////////////////////////////////////////////////////////////
-//
-// Tasks for PHY <-> MAC transactions
-//
-//////////////////////////////////////////////////////////////////////
-
-initial
-begin
- tx_mem_addr_in = 0;
-end
-
-// setting the address of tx_mem, to set the starting point of tx packet
-task set_tx_mem_addr;
- input [31:0] tx_mem_address;
-begin
- #1 tx_mem_addr_in = tx_mem_address;
-end
-endtask // set_tx_mem_addr
-
-// storage memory for RX data to be transmited to MAC
-reg [7:0] rx_mem [0:4194303]; // 4194304 locations (22 address lines) of 8-bit data width
-
-// MAC RX signals
-reg [3:0] mrxd_o;
-reg mrxdv_o;
-reg mrxerr_o;
-
-initial
-begin
- mrxd_o = 0;
- mrxdv_o = 0;
- mrxerr_o = 0;
- mcrs_rx = 0;
-end
-
-task send_rx_packet;
- input [(8*8)-1:0] preamble_data; // preamble data to be sent - correct is 64'h0055_5555_5555_5555
- input [3:0] preamble_len; // length of preamble in bytes - max is 4'h8, correct is 4'h7
- input [7:0] sfd_data; // SFD data to be sent - correct is 8'hD5
- input [31:0] start_addr; // start address
- input [31:0] len; // length of frame in Bytes (without preamble and SFD)
- input plus_drible_nibble; // if length is longer for one nibble
- integer rx_cnt;
- reg [31:0] rx_mem_addr_in; // address for reading from RX memory
- reg [7:0] rx_mem_data_out; // data for reading from RX memory
-begin
- @(posedge mrx_clk_o);
- // generating CARRIER SENSE for TX with or without delay
- if (real_carrier_sense)
- #1 mcrs_rx = 1;
- else
- #1 mcrs_rx = 0;
- @(posedge mrx_clk_o);
- #1 mcrs_rx = 1;
- #1 mrxdv_o = 1;
- `ifdef VERBOSE
- $fdisplay(phy_log, " (%0t)(%m) RX frame started with rx_dv set!", $time);
- `endif
- // set initial rx memory address
- rx_mem_addr_in = start_addr;
-
- // send preamble
- for (rx_cnt = 0; (rx_cnt < (preamble_len << 1)) && (rx_cnt < 16); rx_cnt = rx_cnt + 1)
- begin
- #1 mrxd_o = preamble_data[3:0];
- #1 preamble_data = preamble_data >> 4;
- @(posedge mrx_clk_o);
- end
-
- // send SFD
- for (rx_cnt = 0; rx_cnt < 2; rx_cnt = rx_cnt + 1)
- begin
- #1 mrxd_o = sfd_data[3:0];
- #1 sfd_data = sfd_data >> 4;
- @(posedge mrx_clk_o);
- end
- `ifdef VERBOSE
- $fdisplay(phy_log, " (%0t)(%m) RX frame preamble and SFD sent!", $time);
- `endif
- // send packet's addresses, type/length, data and FCS
- for (rx_cnt = 0; rx_cnt < len; rx_cnt = rx_cnt + 1)
- begin
- #1;
- rx_mem_data_out = rx_mem[rx_mem_addr_in[21:0]];
- mrxd_o = rx_mem_data_out[3:0];
- @(posedge mrx_clk_o);
- #1;
- mrxd_o = rx_mem_data_out[7:4];
- rx_mem_addr_in = rx_mem_addr_in + 1;
- @(posedge mrx_clk_o);
- #1;
- end
- if (plus_drible_nibble)
- begin
- rx_mem_data_out = rx_mem[rx_mem_addr_in[21:0]];
- mrxd_o = rx_mem_data_out[3:0];
- @(posedge mrx_clk_o);
- end
- `ifdef VERBOSE
- $fdisplay(phy_log, " (%0t)(%m) RX frame addresses, type/length, data and FCS sent!", $time);
- `endif
- #1 mcrs_rx = 0;
- #1 mrxdv_o = 0;
- @(posedge mrx_clk_o);
- `ifdef VERBOSE
- $fdisplay(phy_log, " (%0t)(%m) RX frame ended with rx_dv reset!", $time);
- `endif
-end
-endtask // send_rx_packet
-
-
-
-task GetDataOnMRxD;
- input [15:0] Len;
- input [31:0] TransferType;
- integer tt;
-
- begin
- @ (posedge mrx_clk_o);
- #1 mrxdv_o=1'b1;
-
- for(tt=0; tt<15; tt=tt+1)
- begin
- mrxd_o=4'h5; // preamble
- @ (posedge mrx_clk_o);
- #1;
- end
-
- mrxd_o=4'hd; // SFD
-
- for(tt=1; tt<(Len+1); tt=tt+1)
- begin
- @ (posedge mrx_clk_o);
- #1;
- if(TransferType == `UNICAST_XFR && tt == 1)
- mrxd_o = 4'h0; // Unicast transfer
- else if(TransferType == `BROADCAST_XFR && tt < 7)
- mrxd_o = 4'hf;
- else
- mrxd_o = tt[3:0]; // Multicast transfer
-
- @ (posedge mrx_clk_o);
- #1;
-
- if(TransferType == `BROADCAST_XFR && tt == 6)
- mrxd_o = 4'he;
- else
-
- if(TransferType == `BROADCAST_XFR && tt < 7)
- mrxd_o = 4'hf;
- else
- mrxd_o = tt[7:4];
- end
-
- @ (posedge mrx_clk_o);
- #1;
- mrxdv_o = 1'b0;
- end
-endtask // GetDataOnMRxD
-
-
-//////////////////////////////////////////////////////////////////////
-//
-// Tastks for controling PHY statuses and rx error
-//
-//////////////////////////////////////////////////////////////////////
-
-// Link control tasks
-task link_up_down;
- input test_op;
-begin
- #1 status_bit6_0[2] = test_op; // 1 - link up; 0 - link down
-end
-endtask
-
-// RX error
-task rx_err;
- input test_op;
-begin
- #1 mrxerr_o = test_op; // 1 - RX error set; 0 - RX error reset
-end
-endtask
-
-//////////////////////////////////////////////////////////////////////
-//
-// Tastks for controling PHY carrier sense and collision
-//
-//////////////////////////////////////////////////////////////////////
-
-// Collision
-task collision;
- input test_op;
-begin
- #1 task_mcoll = test_op;
-end
-endtask
-
-// Carrier sense
-task carrier_sense;
- input test_op;
-begin
- #1 task_mcrs = test_op;
-end
-endtask
-
-// Carrier sense lost - higher priority than Carrier sense task
-task carrier_sense_lost;
- input test_op;
-begin
- #1 task_mcrs_lost = test_op;
-end
-endtask
-
-// No collision detection in half duplex
-task no_collision_hd_detect;
- input test_op;
-begin
- #1 no_collision_in_half_duplex = test_op;
-end
-endtask
-
-// Collision detection in full duplex also
-task collision_fd_detect;
- input test_op;
-begin
- #1 collision_in_full_duplex = test_op;
-end
-endtask
-
-// No carrier sense detection at TX in half duplex
-task no_carrier_sense_tx_hd_detect;
- input test_op;
-begin
- #1 no_carrier_sense_in_tx_half_duplex = test_op;
-end
-endtask
-
-// No carrier sense detection at RX in half duplex
-task no_carrier_sense_rx_hd_detect;
- input test_op;
-begin
- #1 no_carrier_sense_in_rx_half_duplex = test_op;
-end
-endtask
-
-// Carrier sense detection at TX in full duplex also
-task carrier_sense_tx_fd_detect;
- input test_op;
-begin
- #1 carrier_sense_in_tx_full_duplex = test_op;
-end
-endtask
-
-// No carrier sense detection at RX in full duplex
-task no_carrier_sense_rx_fd_detect;
- input test_op;
-begin
- #1 no_carrier_sense_in_rx_full_duplex = test_op;
-end
-endtask
-
-// Set real delay on carrier sense signal (and therefor collision signal)
-task carrier_sense_real_delay;
- input test_op;
-begin
- #1 real_carrier_sense = test_op;
-end
-endtask
-
-//////////////////////////////////////////////////////////////////////
-//
-// Tastks for controling PHY management test operation
-//
-//////////////////////////////////////////////////////////////////////
-
-// Set registers to test operation and respond to all phy addresses
-task test_regs;
- input test_op;
-begin
- #1 registers_addr_data_test_operation = test_op;
- respond_to_all_phy_addr = test_op;
-end
-endtask
-
-// Clears data memory for testing the MII
-task clear_test_regs;
- integer i;
-begin
- for (i = 0; i < 32; i = i + 1)
- begin
- #1 data_mem[i] = 16'h0;
- end
-end
-endtask
-
-// Accept frames with preamble suppresed
-task preamble_suppresed;
- input test_op;
-begin
- #1 no_preamble = test_op;
- md_transfer_cnt_reset = 1'b1;
- @(posedge mdc_i);
- #1 md_transfer_cnt_reset = 1'b0;
-end
-endtask
-
-
-
-
-
-endmodule
-
bench/verilog/eth_phy.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: bench/verilog/tb_eth_defines.v
===================================================================
--- bench/verilog/tb_eth_defines.v (revision 16)
+++ bench/verilog/tb_eth_defines.v (nonexistent)
@@ -1,216 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// tb_eth_defines.v ////
-//// ////
-//// This file is part of the Ethernet IP core project ////
-//// http://www.opencores.org/projects/ethmac/ ////
-//// ////
-//// Author(s): ////
-//// - Igor Mohor (igorM@opencores.org) ////
-//// ////
-//// All additional information is available in the Readme.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2001, 2002 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: tb_eth_defines.v,v $
-// Revision 1.11 2003/06/13 11:55:20 mohor
-// Define file in eth_cop.v is changed to eth_defines.v. Some defines were
-// moved from tb_eth_defines.v to eth_defines.v.
-//
-// Revision 1.10 2002/11/19 20:27:46 mohor
-// Temp version.
-//
-// Revision 1.9 2002/10/09 13:16:51 tadejm
-// Just back-up; not completed testbench and some testcases are not
-// wotking properly yet.
-//
-// Revision 1.8 2002/09/13 18:41:45 mohor
-// Rearanged testcases
-//
-// Revision 1.7 2002/09/13 12:29:14 mohor
-// Headers changed.
-//
-// Revision 1.6 2002/09/13 11:57:20 mohor
-// New testbench. Thanks to Tadej M - "The Spammer".
-//
-// Revision 1.3 2002/07/19 13:57:53 mohor
-// Testing environment also includes traffic cop, memory interface and host
-// interface.
-//
-// Revision 1.2 2002/05/03 10:22:17 mohor
-// TX_BUF_BASE changed.
-//
-// Revision 1.1 2002/03/19 12:53:54 mohor
-// Some defines that are used in testbench only were moved to tb_eth_defines.v
-// file.
-//
-//
-//
-//
-
-
-
-//`define VERBOSE // if log files of device modules are written
-
-`define MULTICAST_XFR 0
-`define UNICAST_XFR 1
-`define BROADCAST_XFR 2
-`define UNICAST_WRONG_XFR 3
-
-`define ETH_BASE 32'hd0000000
-`define ETH_WIDTH 32'h800
-`define MEMORY_BASE 32'h2000
-`define MEMORY_WIDTH 32'h10000
-`define TX_BUF_BASE `MEMORY_BASE
-`define RX_BUF_BASE `MEMORY_BASE + 32'h8000
-`define TX_BD_BASE `ETH_BASE + 32'h00000400
-`define RX_BD_BASE `ETH_BASE + 32'h00000600
-
-/* Tx BD */
-`define ETH_TX_BD_READY 32'h8000 /* Tx BD Ready */
-`define ETH_TX_BD_IRQ 32'h4000 /* Tx BD IRQ Enable */
-`define ETH_TX_BD_WRAP 32'h2000 /* Tx BD Wrap (last BD) */
-`define ETH_TX_BD_PAD 32'h1000 /* Tx BD Pad Enable */
-`define ETH_TX_BD_CRC 32'h0800 /* Tx BD CRC Enable */
-
-`define ETH_TX_BD_UNDERRUN 32'h0100 /* Tx BD Underrun Status */
-`define ETH_TX_BD_RETRY 32'h00F0 /* Tx BD Retry Status */
-`define ETH_TX_BD_RETLIM 32'h0008 /* Tx BD Retransmission Limit Status */
-`define ETH_TX_BD_LATECOL 32'h0004 /* Tx BD Late Collision Status */
-`define ETH_TX_BD_DEFER 32'h0002 /* Tx BD Defer Status */
-`define ETH_TX_BD_CARRIER 32'h0001 /* Tx BD Carrier Sense Lost Status */
-
-/* Rx BD */
-`define ETH_RX_BD_EMPTY 32'h8000 /* Rx BD Empty */
-`define ETH_RX_BD_IRQ 32'h4000 /* Rx BD IRQ Enable */
-`define ETH_RX_BD_WRAP 32'h2000 /* Rx BD Wrap (last BD) */
-
-`define ETH_RX_BD_MISS 32'h0080 /* Rx BD Miss Status */
-`define ETH_RX_BD_OVERRUN 32'h0040 /* Rx BD Overrun Status */
-`define ETH_RX_BD_INVSIMB 32'h0020 /* Rx BD Invalid Symbol Status */
-`define ETH_RX_BD_DRIBBLE 32'h0010 /* Rx BD Dribble Nibble Status */
-`define ETH_RX_BD_TOOLONG 32'h0008 /* Rx BD Too Long Status */
-`define ETH_RX_BD_SHORT 32'h0004 /* Rx BD Too Short Frame Status */
-`define ETH_RX_BD_CRCERR 32'h0002 /* Rx BD CRC Error Status */
-`define ETH_RX_BD_LATECOL 32'h0001 /* Rx BD Late Collision Status */
-
-
-
-/* Register space */
-`define ETH_MODER `ETH_BASE + 32'h00 /* Mode Register */
-`define ETH_INT `ETH_BASE + 32'h04 /* Interrupt Source Register */
-`define ETH_INT_MASK `ETH_BASE + 32'h08 /* Interrupt Mask Register */
-`define ETH_IPGT `ETH_BASE + 32'h0C /* Back to Bak Inter Packet Gap Register */
-`define ETH_IPGR1 `ETH_BASE + 32'h10 /* Non Back to Back Inter Packet Gap Register 1 */
-`define ETH_IPGR2 `ETH_BASE + 32'h14 /* Non Back to Back Inter Packet Gap Register 2 */
-`define ETH_PACKETLEN `ETH_BASE + 32'h18 /* Packet Length Register (min. and max.) */
-`define ETH_COLLCONF `ETH_BASE + 32'h1C /* Collision and Retry Configuration Register */
-`define ETH_TX_BD_NUM `ETH_BASE + 32'h20 /* Transmit Buffer Descriptor Number Register */
-`define ETH_CTRLMODER `ETH_BASE + 32'h24 /* Control Module Mode Register */
-`define ETH_MIIMODER `ETH_BASE + 32'h28 /* MII Mode Register */
-`define ETH_MIICOMMAND `ETH_BASE + 32'h2C /* MII Command Register */
-`define ETH_MIIADDRESS `ETH_BASE + 32'h30 /* MII Address Register */
-`define ETH_MIITX_DATA `ETH_BASE + 32'h34 /* MII Transmit Data Register */
-`define ETH_MIIRX_DATA `ETH_BASE + 32'h38 /* MII Receive Data Register */
-`define ETH_MIISTATUS `ETH_BASE + 32'h3C /* MII Status Register */
-`define ETH_MAC_ADDR0 `ETH_BASE + 32'h40 /* MAC Individual Address Register 0 */
-`define ETH_MAC_ADDR1 `ETH_BASE + 32'h44 /* MAC Individual Address Register 1 */
-`define ETH_HASH_ADDR0 `ETH_BASE + 32'h48 /* Hash Register 0 */
-`define ETH_HASH_ADDR1 `ETH_BASE + 32'h4C /* Hash Register 1 */
-`define ETH_TX_CTRL `ETH_BASE + 32'h50 /* Tx Control Register */
-
-
-/* MODER Register */
-`define ETH_MODER_RXEN 32'h00000001 /* Receive Enable */
-`define ETH_MODER_TXEN 32'h00000002 /* Transmit Enable */
-`define ETH_MODER_NOPRE 32'h00000004 /* No Preamble */
-`define ETH_MODER_BRO 32'h00000008 /* Reject Broadcast */
-`define ETH_MODER_IAM 32'h00000010 /* Use Individual Hash */
-`define ETH_MODER_PRO 32'h00000020 /* Promiscuous (receive all) */
-`define ETH_MODER_IFG 32'h00000040 /* Min. IFG not required */
-`define ETH_MODER_LOOPBCK 32'h00000080 /* Loop Back */
-`define ETH_MODER_NOBCKOF 32'h00000100 /* No Backoff */
-`define ETH_MODER_EXDFREN 32'h00000200 /* Excess Defer */
-`define ETH_MODER_FULLD 32'h00000400 /* Full Duplex */
-`define ETH_MODER_RST 32'h00000800 /* Reset MAC */
-`define ETH_MODER_DLYCRCEN 32'h00001000 /* Delayed CRC Enable */
-`define ETH_MODER_CRCEN 32'h00002000 /* CRC Enable */
-`define ETH_MODER_HUGEN 32'h00004000 /* Huge Enable */
-`define ETH_MODER_PAD 32'h00008000 /* Pad Enable */
-`define ETH_MODER_RECSMALL 32'h00010000 /* Receive Small */
-
-/* Interrupt Source Register */
-`define ETH_INT_TXB 32'h00000001 /* Transmit Buffer IRQ */
-`define ETH_INT_TXE 32'h00000002 /* Transmit Error IRQ */
-`define ETH_INT_RXB 32'h00000004 /* Receive Buffer IRQ */
-`define ETH_INT_RXE 32'h00000008 /* Receive Error IRQ */
-`define ETH_INT_BUSY 32'h00000010 /* Busy IRQ */
-`define ETH_INT_TXC 32'h00000020 /* Transmit Control Frame IRQ */
-`define ETH_INT_RXC 32'h00000040 /* Received Control Frame IRQ */
-
-/* Interrupt Mask Register */
-`define ETH_INT_MASK_TXB 32'h00000001 /* Transmit Buffer IRQ Mask */
-`define ETH_INT_MASK_TXE 32'h00000002 /* Transmit Error IRQ Mask */
-`define ETH_INT_MASK_RXF 32'h00000004 /* Receive Frame IRQ Mask */
-`define ETH_INT_MASK_RXE 32'h00000008 /* Receive Error IRQ Mask */
-`define ETH_INT_MASK_BUSY 32'h00000010 /* Busy IRQ Mask */
-`define ETH_INT_MASK_TXC 32'h00000020 /* Transmit Control Frame IRQ Mask */
-`define ETH_INT_MASK_RXC 32'h00000040 /* Received Control Frame IRQ Mask */
-
-/* Control Module Mode Register */
-`define ETH_CTRLMODER_PASSALL 32'h00000001 /* Pass Control Frames */
-`define ETH_CTRLMODER_RXFLOW 32'h00000002 /* Receive Control Flow Enable */
-`define ETH_CTRLMODER_TXFLOW 32'h00000004 /* Transmit Control Flow Enable */
-
-/* MII Mode Register */
-`define ETH_MIIMODER_CLKDIV 32'h000000FF /* Clock Divider */
-`define ETH_MIIMODER_NOPRE 32'h00000100 /* No Preamble */
-`define ETH_MIIMODER_RST 32'h00000200 /* MIIM Reset */
-
-/* MII Command Register */
-`define ETH_MIICOMMAND_SCANSTAT 32'h00000001 /* Scan Status */
-`define ETH_MIICOMMAND_RSTAT 32'h00000002 /* Read Status */
-`define ETH_MIICOMMAND_WCTRLDATA 32'h00000004 /* Write Control Data */
-
-/* MII Address Register */
-`define ETH_MIIADDRESS_FIAD 32'h0000001F /* PHY Address */
-`define ETH_MIIADDRESS_RGAD 32'h00001F00 /* RGAD Address */
-
-/* MII Status Register */
-`define ETH_MIISTATUS_LINKFAIL 0 /* Link Fail bit */
-`define ETH_MIISTATUS_BUSY 1 /* MII Busy bit */
-`define ETH_MIISTATUS_NVALID 2 /* Data in MII Status Register is invalid bit */
-
-/* TX Control Register */
-`define ETH_TX_CTRL_TXPAUSERQ 32'h10000 /* Send PAUSE request */
-
-
-`define TIME $display(" Time: %0t", $time)
bench/verilog/tb_eth_defines.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: bench/verilog/minsoc_bench_defines.v
===================================================================
--- bench/verilog/minsoc_bench_defines.v (revision 16)
+++ bench/verilog/minsoc_bench_defines.v (revision 17)
@@ -8,13 +8,15 @@
//~set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER)
`define FREQ 25000000
-
`define CLK_PERIOD (1000000000/`FREQ)
-`define VPI_DEBUG
+`define ETH_PHY_FREQ 25000000
+`define ETH_PHY_PERIOD (1000000000/`ETH_PHY_FREQ) //40ns
`define UART_BAUDRATE 115200
+`define VPI_DEBUG
+
//`define VCD_OUTPUT
//`define START_UP //pass firmware over spi to or1k_startup
/bench/verilog/minsoc_bench.v
6,6 → 6,7
|
reg clock, reset; |
|
//Debug interface |
wire dbg_tms_i; |
wire dbg_tck_i; |
wire dbg_tdi_i; |
13,26 → 14,29
wire jtag_vref; |
wire jtag_gnd; |
|
//SPI wires |
wire spi_mosi; |
reg spi_miso; |
wire spi_sclk; |
wire [1:0] spi_ss; |
|
//UART wires |
wire uart_stx; |
reg uart_srx; |
|
wire eth_col; |
wire eth_crs; |
//ETH wires |
reg eth_col; |
reg eth_crs; |
wire eth_trst; |
wire eth_tx_clk; |
reg eth_tx_clk; |
wire eth_tx_en; |
wire eth_tx_er; |
wire [3:0] eth_txd; |
wire eth_rx_clk; |
wire eth_rx_dv; |
wire eth_rx_er; |
wire [3:0] eth_rxd; |
wire eth_fds_mdint; |
reg eth_rx_clk; |
reg eth_rx_dv; |
reg eth_rx_er; |
reg [3:0] eth_rxd; |
reg eth_fds_mdint; |
wire eth_mdc; |
wire eth_mdio; |
|
39,8 → 43,12
// |
// TASKS registers to communicate with interfaces |
// |
reg [7:0] tx_data [0:1518]; //receive buffer |
reg [31:0] data_in [1023:0]; //send buffer |
`ifdef ETHERNET |
reg [7:0] eth_rx_data [0:1535]; //receive buffer ETH (max packet 1536) |
reg [7:0] eth_tx_data [0:1535]; //send buffer ETH (max packet 1536) |
localparam ETH_HDR = 14; |
localparam ETH_PAYLOAD_MAX_LENGTH = 1518;//only able to send up to 1536 bytes with header (14 bytes) and CRC (4 bytes) |
`endif |
|
|
// |
54,10 → 62,21
initial begin |
reset = 1'b0; |
clock = 1'b0; |
|
uart_srx = 1'b1; |
|
eth_col = 1'b0; |
eth_crs = 1'b0; |
eth_fds_mdint = 1'b1; |
eth_rx_er = 1'b0; |
|
eth_tx_clk = 1'b0; |
eth_rx_clk = 1'b0; |
eth_rxd = 4'h0; |
eth_rx_dv = 1'b0; |
|
|
//dual and two port rams from FPGA memory instances have to be initialized to |
//0 |
//dual and two port rams from FPGA memory instances have to be initialized to 0 |
init_fpga_memory(); |
|
load_file = 1'b0; |
117,10 → 136,38
$display("Loaded firmware:"); |
$display("%s", file_name); |
`endif |
|
|
// |
// Testbench START |
// |
|
fork |
begin |
`ifdef ETHERNET |
get_mac(); |
|
if ( { eth_rx_data[ETH_HDR] , eth_rx_data[ETH_HDR+1] , eth_rx_data[ETH_HDR+2] , eth_rx_data[ETH_HDR+3] } == 32'hFF2B4050 ) |
$display("eth-nocache firmware started."); |
`endif |
end |
begin |
#2000000; |
`ifdef UART |
uart_send(8'h41); //Character A |
`endif |
`ifdef ETHERNET |
eth_tx_data[ETH_HDR+0] = 8'hBA; |
eth_tx_data[ETH_HDR+1] = 8'h87; |
eth_tx_data[ETH_HDR+2] = 8'hAA; |
eth_tx_data[ETH_HDR+3] = 8'hBB; |
eth_tx_data[ETH_HDR+4] = 8'hCC; |
eth_tx_data[ETH_HDR+5] = 8'hDD; |
|
send_mac(6); |
`endif |
end |
join |
|
end |
|
190,37 → 237,7
assign dbg_tms_i = 1; |
`endif |
|
`ifdef ETHERNET |
eth_phy my_phy // This PHY model simulate simplified Intel LXT971A PHY |
( |
// COMMON |
.m_rst_n_i(1'b1), |
|
// MAC TX |
.mtx_clk_o(eth_tx_clk), |
.mtxd_i(eth_txd), |
.mtxen_i(eth_tx_en), |
.mtxerr_i(eth_tx_er), |
|
// MAC RX |
.mrx_clk_o(eth_rx_clk), |
.mrxd_o(eth_rxd), |
.mrxdv_o(eth_rx_dv), |
.mrxerr_o(eth_rx_er), |
|
.mcoll_o(eth_col), |
.mcrs_o(eth_crs), |
|
// MIIM |
.mdc_i(eth_mdc), |
.md_io(eth_mdio), |
|
// SYSTEM |
.phy_log() |
); |
`endif // !ETHERNET |
|
|
// |
// Regular clocking and output |
// |
255,10 → 272,27
`endif |
//~SPI START_UP |
|
//UART Monitor (prints uart output on the terminal) |
//UART |
`ifdef UART |
parameter UART_TX_WAIT = (`FREQ / `UART_BAUDRATE) * `CLK_PERIOD; |
localparam UART_TX_WAIT = (`FREQ / `UART_BAUDRATE) * `CLK_PERIOD; |
|
task uart_send; |
input [7:0] data; |
integer i; |
begin |
uart_srx = 1'b0; |
#UART_TX_WAIT; |
for ( i = 0; i < 8 ; i = i + 1 ) begin |
uart_srx = data[i]; |
#UART_TX_WAIT; |
end |
uart_srx = 1'b0; |
#UART_TX_WAIT; |
uart_srx = 1'b1; |
end |
endtask |
|
//UART Monitor (prints uart output on the terminal) |
// Something to trigger the task |
always @(posedge clock) |
uart_decoder; |
291,8 → 325,9
$write("%c", tx_byte); |
end |
endtask |
//~UART Monitor |
`endif // !UART |
//~UART Monitor |
//~UART |
|
|
// |
301,7 → 336,7
//MAC_DATA |
// |
`ifdef ETHERNET |
reg [31:0] crc32_result; |
reg [31:0] crc32_result; |
|
task get_mac; |
integer conta; |
309,13 → 344,16
begin |
conta = 0; |
LSB = 1; |
@ ( posedge eth_tx_en); |
@ ( posedge eth_tx_en); |
|
repeat (16) @ (negedge eth_tx_clk); //8 bytes, preamble (7 bytes) + start of frame (1 byte) |
|
while ( eth_tx_en == 1'b1 ) begin |
@ (negedge eth_tx_clk) begin |
if ( LSB == 1'b1 ) |
tx_data[conta][3:0] = eth_txd; |
eth_rx_data[conta][3:0] = eth_txd; |
else begin |
tx_data[conta][7:4] = eth_txd; |
eth_rx_data[conta][7:4] = eth_txd; |
conta = conta + 1; |
end |
LSB = ~LSB; |
324,119 → 362,127
end |
endtask |
|
task send_mac; |
input [11:0] command; |
input [31:0] param1; |
input [31:0] param2; |
input [223:0] data; |
|
task send_mac; //only able to send up to 1536 bytes with header (14 bytes) and CRC (4 bytes) |
input [31:0] length; //ETH_PAYLOAD_MAX_LENGTH 1518 |
integer conta; |
begin |
if ( length <= ETH_PAYLOAD_MAX_LENGTH ) begin |
//DEST MAC |
eth_tx_data[0] = 8'h55; |
eth_tx_data[1] = 8'h47; |
eth_tx_data[2] = 8'h34; |
eth_tx_data[3] = 8'h22; |
eth_tx_data[4] = 8'h88; |
eth_tx_data[5] = 8'h92; |
|
begin |
//DEST MAC |
my_phy.rx_mem[0] = 8'h55; |
my_phy.rx_mem[1] = 8'h47; |
my_phy.rx_mem[2] = 8'h34; |
my_phy.rx_mem[3] = 8'h22; |
my_phy.rx_mem[4] = 8'h88; |
my_phy.rx_mem[5] = 8'h92; |
//SOURCE MAC |
eth_tx_data[6] = 8'h3D; |
eth_tx_data[7] = 8'h4F; |
eth_tx_data[8] = 8'h1A; |
eth_tx_data[9] = 8'hBE; |
eth_tx_data[10] = 8'h68; |
eth_tx_data[11] = 8'h72; |
|
//SOURCE MAC |
my_phy.rx_mem[6] = 8'h00; |
my_phy.rx_mem[7] = 8'h00; |
my_phy.rx_mem[8] = 8'hC0; |
my_phy.rx_mem[9] = 8'h41; |
my_phy.rx_mem[10] = 8'h36; |
my_phy.rx_mem[11] = 8'hD3; |
//LEN |
eth_tx_data[12] = length[7:4]; |
eth_tx_data[13] = length[3:0]; |
|
//LEN |
my_phy.rx_mem[12] = 8'h00; |
my_phy.rx_mem[13] = 8'h04; |
//DATA input by task caller |
|
//DATA |
my_phy.rx_mem[14] = 8'hFF; |
my_phy.rx_mem[15] = 8'hFA; |
my_phy.rx_mem[16] = command[11:4]; |
my_phy.rx_mem[17] = { command[3:0] , 4'h7 }; |
//PAD |
for ( conta = length+14; conta < 60; conta = conta + 1 ) begin |
eth_tx_data[conta] = 8'h00; |
end |
|
my_phy.rx_mem[18] = 8'hAA; |
my_phy.rx_mem[19] = 8'hAA; |
gencrc32(conta); |
|
//parameter 1 |
my_phy.rx_mem[20] = param1[31:24]; |
my_phy.rx_mem[21] = param1[23:16]; |
my_phy.rx_mem[22] = param1[15:8]; |
my_phy.rx_mem[23] = param1[7:0]; |
eth_tx_data[conta] = crc32_result[31:24]; |
eth_tx_data[conta+1] = crc32_result[23:16]; |
eth_tx_data[conta+2] = crc32_result[15:8]; |
eth_tx_data[conta+3] = crc32_result[7:0]; |
|
//parameter 2 |
my_phy.rx_mem[24] = param2[31:24]; |
my_phy.rx_mem[25] = param2[23:16]; |
my_phy.rx_mem[26] = param2[15:8]; |
my_phy.rx_mem[27] = param2[7:0]; |
|
//data |
my_phy.rx_mem[28] = data[223:216]; |
my_phy.rx_mem[29] = data[215:208]; |
my_phy.rx_mem[30] = data[207:200]; |
my_phy.rx_mem[31] = data[199:192]; |
my_phy.rx_mem[32] = data[191:184]; |
my_phy.rx_mem[33] = data[183:176]; |
my_phy.rx_mem[34] = data[175:168]; |
my_phy.rx_mem[35] = data[167:160]; |
my_phy.rx_mem[36] = data[159:152]; |
my_phy.rx_mem[37] = data[151:144]; |
my_phy.rx_mem[38] = data[143:136]; |
my_phy.rx_mem[39] = data[135:128]; |
my_phy.rx_mem[40] = data[127:120]; |
my_phy.rx_mem[41] = data[119:112]; |
my_phy.rx_mem[42] = data[111:104]; |
my_phy.rx_mem[43] = data[103:96]; |
my_phy.rx_mem[44] = data[95:88]; |
my_phy.rx_mem[45] = data[87:80]; |
my_phy.rx_mem[46] = data[79:72]; |
my_phy.rx_mem[47] = data[71:64]; |
my_phy.rx_mem[48] = data[63:56]; |
my_phy.rx_mem[49] = data[55:48]; |
my_phy.rx_mem[50] = data[47:40]; |
my_phy.rx_mem[51] = data[39:32]; |
my_phy.rx_mem[52] = data[31:24]; |
my_phy.rx_mem[53] = data[23:16]; |
my_phy.rx_mem[54] = data[15:8]; |
my_phy.rx_mem[55] = data[7:0]; |
|
//PAD |
for ( conta = 56; conta < 60; conta = conta + 1 ) begin |
my_phy.rx_mem[conta] = 8'h00; |
end |
|
gencrc32; |
|
my_phy.rx_mem[60] = crc32_result[31:24]; |
my_phy.rx_mem[61] = crc32_result[23:16]; |
my_phy.rx_mem[62] = crc32_result[15:8]; |
my_phy.rx_mem[63] = crc32_result[7:0]; |
|
my_phy.send_rx_packet( 64'h0055_5555_5555_5555, 4'h7, 8'hD5, 32'h0000_0000, 32'h0000_0040, 1'b0 ); |
send_rx_packet( 64'h0055_5555_5555_5555, 4'h7, 8'hD5, 32'h0000_0000, conta+4, 1'b0 ); |
end |
else |
$display("Warning: Ethernet packet is to big to be sent."); |
end |
|
endtask |
|
task send_rx_packet; |
input [(8*8)-1:0] preamble_data; // preamble data to be sent - correct is 64'h0055_5555_5555_5555 |
input [3:0] preamble_len; // length of preamble in bytes - max is 4'h8, correct is 4'h7 |
input [7:0] sfd_data; // SFD data to be sent - correct is 8'hD5 |
input [31:0] start_addr; // start address |
input [31:0] len; // length of frame in Bytes (without preamble and SFD) |
input plus_drible_nibble; // if length is longer for one nibble |
integer rx_cnt; |
reg [31:0] eth_tx_data_addr_in; // address for reading from RX memory |
reg [7:0] eth_tx_data_data_out; // data for reading from RX memory |
begin |
@(posedge eth_rx_clk); |
#1 eth_rx_dv = 1; |
|
// set initial rx memory address |
eth_tx_data_addr_in = start_addr; |
|
// send preamble |
for (rx_cnt = 0; (rx_cnt < (preamble_len << 1)) && (rx_cnt < 16); rx_cnt = rx_cnt + 1) |
begin |
#1 eth_rxd = preamble_data[3:0]; |
#1 preamble_data = preamble_data >> 4; |
@(posedge eth_rx_clk); |
end |
|
// send SFD |
for (rx_cnt = 0; rx_cnt < 2; rx_cnt = rx_cnt + 1) |
begin |
#1 eth_rxd = sfd_data[3:0]; |
#1 sfd_data = sfd_data >> 4; |
@(posedge eth_rx_clk); |
end |
|
// send packet's addresses, type/length, data and FCS |
for (rx_cnt = 0; rx_cnt < len; rx_cnt = rx_cnt + 1) |
begin |
#1; |
eth_tx_data_data_out = eth_tx_data[eth_tx_data_addr_in[21:0]]; |
eth_rxd = eth_tx_data_data_out[3:0]; |
@(posedge eth_rx_clk); |
#1; |
eth_rxd = eth_tx_data_data_out[7:4]; |
eth_tx_data_addr_in = eth_tx_data_addr_in + 1; |
@(posedge eth_rx_clk); |
#1; |
end |
if (plus_drible_nibble) |
begin |
eth_tx_data_data_out = eth_tx_data[eth_tx_data_addr_in[21:0]]; |
eth_rxd = eth_tx_data_data_out[3:0]; |
@(posedge eth_rx_clk); |
end |
|
#1 eth_rx_dv = 0; |
@(posedge eth_rx_clk); |
|
end |
endtask // send_rx_packet |
|
//CRC32 |
parameter [31:0] CRC32_POLY = 32'h04C11DB7; |
localparam [31:0] CRC32_POLY = 32'h04C11DB7; |
|
task gencrc32; |
task gencrc32; |
input [31:0] crc32_length; |
|
integer byte, bit; |
reg msb; |
reg [7:0] current_byte; |
reg [31:0] temp; |
|
integer crc32_length; |
|
begin |
crc32_length = 60; |
crc32_result = 32'hffffffff; |
for (byte = 0; byte < crc32_length; byte = byte + 1) begin |
current_byte = my_phy.rx_mem[byte]; |
current_byte = eth_tx_data[byte]; |
for (bit = 0; bit < 8; bit = bit + 1) begin |
msb = crc32_result[31]; |
crc32_result = crc32_result << 1; |
457,7 → 503,17
crc32_result = ~{temp[7:0], temp[15:8], temp[23:16], temp[31:24]}; |
end |
endtask |
//~CRC32 |
//~CRC32 |
|
//Generate tx and rx clocks |
always begin |
#((`ETH_PHY_PERIOD)/2) eth_tx_clk <= ~eth_tx_clk; |
end |
always begin |
#((`ETH_PHY_PERIOD)/2) eth_rx_clk <= ~eth_rx_clk; |
end |
//~Generate tx and rx clocks |
|
`endif // !ETHERNET |
//~MAC_DATA |
|
/bench/verilog/sim_lib/fpga_memory_primitives.v
647,7 → 647,7
|
endmodule |
// |
// XILINX_RAM32X1D |
// ~XILINX_RAM32X1D |
// |
|
|
697,5 → 697,5
|
endmodule |
// |
// USE_RAM16X1D_FOR_RAM32X1D |
// ~USE_RAM16X1D_FOR_RAM32X1D |
// |
/rtl/verilog/minsoc_top.v
697,6 → 697,7
`else |
assign wb_us_dat_o = 32'h0000_0000; |
assign wb_us_ack_o = 1'b0; |
|
assign pic_ints[`APP_INT_UART] = 1'b0; |
`endif |
|
766,6 → 767,7
assign wb_em_dat_o = 32'h0000_0000; |
assign wb_em_cyc_o = 1'b0; |
assign wb_em_stb_o = 1'b0; |
|
assign pic_ints[`APP_INT_ETH] = 1'b0; |
`endif |
|
/doc/minsoc.pdf
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/doc/minsoc.odt
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/sim/run/generate_bench
1,2 → 1,2
#!/bin/bash |
iverilog -c ../bin/minsoc_model_fast.txt -o minsoc_bench |
iverilog -c ../bin/minsoc_model.txt -o minsoc_bench |
/sim/bin/minsoc_memory_fast.txt
File deleted
sim/bin/minsoc_memory_fast.txt
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: sim/bin/minsoc_memory_complete.txt
===================================================================
--- sim/bin/minsoc_memory_complete.txt (revision 16)
+++ sim/bin/minsoc_memory_complete.txt (nonexistent)
@@ -1,137 +0,0 @@
-+incdir+../../bench/verilog
-+incdir+../../bench/verilog/vpi
-+incdir+../../bench/verilog/sim_lib
-+incdir+../../rtl/verilog
-+incdir+../../rtl/verilog/minsoc_startup
-+incdir+../../rtl/verilog/or1200/rtl/verilog
-+incdir+../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog
-+incdir+../../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog
-+incdir+../../rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_rtl
-+incdir+../../rtl/verilog/uart16550/rtl/verilog
-+incdir+../../rtl/verilog/ethmac/rtl/verilog
-../../bench/verilog/minsoc_bench_defines.v
-../../bench/verilog/minsoc_bench.v
-#../../bench/verilog/minsoc_memory_model.v
-../../bench/verilog/tb_eth_defines.v
-../../bench/verilog/eth_phy_defines.v
-../../bench/verilog/eth_phy.v
-../../bench/verilog/vpi/dbg_comm_vpi.v
-../../bench/verilog/sim_lib/fpga_memory_primitives.v
-../../rtl/verilog/minsoc_top.v
-../../rtl/verilog/minsoc_startup/spi_top.v
-../../rtl/verilog/minsoc_startup/spi_defines.v
-../../rtl/verilog/minsoc_startup/spi_shift.v
-../../rtl/verilog/minsoc_startup/spi_clgen.v
-../../rtl/verilog/minsoc_startup/OR1K_startup_generic.v
-../../rtl/verilog/minsoc_tc_top.v
-../../rtl/verilog/minsoc_onchip_ram.v
-../../rtl/verilog/minsoc_clock_manager.v
-../../rtl/verilog/minsoc_onchip_ram_top.v
-../../rtl/verilog/minsoc_defines.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_spram_512x20.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x24.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_du.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32_bw.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_rf.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_alu.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_top.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_lsu.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_dc_top.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_cpu.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_gmultp2_32x32.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_immu_top.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_dpram_256x32.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_tt.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_iwb_biu.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_rfram_generic.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_dc_tag.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x8.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_ic_tag.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x14.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_spram_32x24.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_dpram_32x32.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_xcv_ram32x8d.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x8.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_mem2reg.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_pm.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_spram_256x21.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_operandmuxes.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_pic.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_cfgr.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_if.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_qmem_top.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_genpc.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_defines.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_wbmux.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_ic_ram.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_tlb.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_sb_fifo.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_sprs.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_tpram_32x32.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_ctrl.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_sb.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_mult_mac.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_ic_fsm.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_amultp2_32x32.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_reg2mem.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_except.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_top.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_ic_top.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_dc_ram.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32_bw.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_freeze.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_spram_128x32.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_dc_fsm.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_wb_biu.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x22.v
-../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_biu.v
-../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_module.v
-../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v
-../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_defines.v
-../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_defines.v
-../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_crc32.v
-../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_biu.v
-../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_defines.v
-../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_status_reg.v
-../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_top.v
-../../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog/tap_top.v
-../../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog/tap_defines.v
-../../rtl/verilog/uart16550/rtl/verilog/uart_top.v
-../../rtl/verilog/uart16550/rtl/verilog/uart_sync_flops.v
-../../rtl/verilog/uart16550/rtl/verilog/uart_transmitter.v
-../../rtl/verilog/uart16550/rtl/verilog/uart_debug_if.v
-../../rtl/verilog/uart16550/rtl/verilog/uart_wb.v
-../../rtl/verilog/uart16550/rtl/verilog/uart_receiver.v
-../../rtl/verilog/uart16550/rtl/verilog/uart_tfifo.v
-../../rtl/verilog/uart16550/rtl/verilog/uart_regs.v
-../../rtl/verilog/uart16550/rtl/verilog/uart_rfifo.v
-../../rtl/verilog/uart16550/rtl/verilog/uart_defines.v
-../../rtl/verilog/uart16550/rtl/verilog/raminfr.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_cop.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_registers.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_rxethmac.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_miim.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_top.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_rxaddrcheck.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_outputcontrol.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_rxstatem.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_txethmac.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_wishbone.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_maccontrol.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_txstatem.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_defines.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_spram_256x32.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_shiftreg.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_clockgen.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_crc.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_rxcounters.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_macstatus.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_random.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_register.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_fifo.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_receivecontrol.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_transmitcontrol.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_txcounters.v
sim/bin/minsoc_memory_complete.txt
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: sim/bin/minsoc_model_fast.txt
===================================================================
--- sim/bin/minsoc_model_fast.txt (revision 16)
+++ sim/bin/minsoc_model_fast.txt (nonexistent)
@@ -1,137 +0,0 @@
-+incdir+../../bench/verilog
-+incdir+../../bench/verilog/vpi
-+incdir+../../bench/verilog/sim_lib
-+incdir+../../rtl/verilog
-+incdir+../../rtl/verilog/minsoc_startup
-+incdir+../../rtl/verilog/or1200/rtl/verilog
-+incdir+../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog
-+incdir+../../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog
-+incdir+../../rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_rtl
-+incdir+../../rtl/verilog/uart16550/rtl/verilog
-+incdir+../../rtl/verilog/ethmac/rtl/verilog
-../../bench/verilog/minsoc_bench_defines.v
-../../bench/verilog/minsoc_bench.v
-../../bench/verilog/minsoc_memory_model.v
-#../../bench/verilog/tb_eth_defines.v
-#../../bench/verilog/eth_phy_defines.v
-#../../bench/verilog/eth_phy.v
-../../bench/verilog/vpi/dbg_comm_vpi.v
-../../bench/verilog/sim_lib/fpga_memory_primitives.v
-../../rtl/verilog/minsoc_top.v
-../../rtl/verilog/minsoc_startup/spi_top.v
-../../rtl/verilog/minsoc_startup/spi_defines.v
-../../rtl/verilog/minsoc_startup/spi_shift.v
-../../rtl/verilog/minsoc_startup/spi_clgen.v
-../../rtl/verilog/minsoc_startup/OR1K_startup_generic.v
-../../rtl/verilog/minsoc_tc_top.v
-../../rtl/verilog/minsoc_onchip_ram.v
-../../rtl/verilog/minsoc_clock_manager.v
-#../../rtl/verilog/minsoc_onchip_ram_top.v
-../../rtl/verilog/minsoc_defines.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_spram_512x20.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x24.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_du.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32_bw.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_rf.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_alu.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_top.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_lsu.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_dc_top.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_cpu.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_gmultp2_32x32.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_immu_top.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_dpram_256x32.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_tt.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_iwb_biu.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_rfram_generic.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_dc_tag.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x8.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_ic_tag.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x14.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_spram_32x24.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_dpram_32x32.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_xcv_ram32x8d.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x8.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_mem2reg.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_pm.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_spram_256x21.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_operandmuxes.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_pic.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_cfgr.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_if.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_qmem_top.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_genpc.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_defines.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_wbmux.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_ic_ram.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_tlb.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_sb_fifo.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_sprs.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_tpram_32x32.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_ctrl.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_sb.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_mult_mac.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_ic_fsm.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_amultp2_32x32.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_reg2mem.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_except.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_top.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_ic_top.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_dc_ram.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32_bw.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_freeze.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_spram_128x32.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_dc_fsm.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_wb_biu.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x22.v
-../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_biu.v
-../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_module.v
-../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v
-../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_defines.v
-../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_defines.v
-../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_crc32.v
-../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_biu.v
-../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_defines.v
-../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_status_reg.v
-../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_top.v
-../../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog/tap_top.v
-../../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog/tap_defines.v
-../../rtl/verilog/uart16550/rtl/verilog/uart_top.v
-../../rtl/verilog/uart16550/rtl/verilog/uart_sync_flops.v
-../../rtl/verilog/uart16550/rtl/verilog/uart_transmitter.v
-../../rtl/verilog/uart16550/rtl/verilog/uart_debug_if.v
-../../rtl/verilog/uart16550/rtl/verilog/uart_wb.v
-../../rtl/verilog/uart16550/rtl/verilog/uart_receiver.v
-../../rtl/verilog/uart16550/rtl/verilog/uart_tfifo.v
-../../rtl/verilog/uart16550/rtl/verilog/uart_regs.v
-../../rtl/verilog/uart16550/rtl/verilog/uart_rfifo.v
-../../rtl/verilog/uart16550/rtl/verilog/uart_defines.v
-../../rtl/verilog/uart16550/rtl/verilog/raminfr.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_cop.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_registers.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_rxethmac.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_miim.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_top.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_rxaddrcheck.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_outputcontrol.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_rxstatem.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_txethmac.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_wishbone.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_maccontrol.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_txstatem.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_defines.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_spram_256x32.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_shiftreg.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_clockgen.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_crc.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_rxcounters.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_macstatus.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_random.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_register.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_fifo.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_receivecontrol.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_transmitcontrol.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_txcounters.v
sim/bin/minsoc_model_fast.txt
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: sim/bin/minsoc_model_complete.txt
===================================================================
--- sim/bin/minsoc_model_complete.txt (revision 16)
+++ sim/bin/minsoc_model_complete.txt (nonexistent)
@@ -1,137 +0,0 @@
-+incdir+../../bench/verilog
-+incdir+../../bench/verilog/vpi
-+incdir+../../bench/verilog/sim_lib
-+incdir+../../rtl/verilog
-+incdir+../../rtl/verilog/minsoc_startup
-+incdir+../../rtl/verilog/or1200/rtl/verilog
-+incdir+../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog
-+incdir+../../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog
-+incdir+../../rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_rtl
-+incdir+../../rtl/verilog/uart16550/rtl/verilog
-+incdir+../../rtl/verilog/ethmac/rtl/verilog
-../../bench/verilog/minsoc_bench_defines.v
-../../bench/verilog/minsoc_bench.v
-../../bench/verilog/minsoc_memory_model.v
-../../bench/verilog/tb_eth_defines.v
-../../bench/verilog/eth_phy_defines.v
-../../bench/verilog/eth_phy.v
-../../bench/verilog/vpi/dbg_comm_vpi.v
-../../bench/verilog/sim_lib/fpga_memory_primitives.v
-../../rtl/verilog/minsoc_top.v
-../../rtl/verilog/minsoc_startup/spi_top.v
-../../rtl/verilog/minsoc_startup/spi_defines.v
-../../rtl/verilog/minsoc_startup/spi_shift.v
-../../rtl/verilog/minsoc_startup/spi_clgen.v
-../../rtl/verilog/minsoc_startup/OR1K_startup_generic.v
-../../rtl/verilog/minsoc_tc_top.v
-../../rtl/verilog/minsoc_onchip_ram.v
-../../rtl/verilog/minsoc_clock_manager.v
-#../../rtl/verilog/minsoc_onchip_ram_top.v
-../../rtl/verilog/minsoc_defines.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_spram_512x20.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x24.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_du.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32_bw.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_rf.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_alu.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_top.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_lsu.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_dc_top.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_cpu.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_gmultp2_32x32.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_immu_top.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_dpram_256x32.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_tt.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_iwb_biu.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_rfram_generic.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_dc_tag.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x8.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_ic_tag.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x14.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_spram_32x24.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_dpram_32x32.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_xcv_ram32x8d.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x8.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_mem2reg.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_pm.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_spram_256x21.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_operandmuxes.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_pic.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_cfgr.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_if.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_qmem_top.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_genpc.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_defines.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_wbmux.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_ic_ram.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_tlb.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_sb_fifo.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_sprs.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_tpram_32x32.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_ctrl.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_sb.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_mult_mac.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_ic_fsm.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_amultp2_32x32.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_reg2mem.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_except.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_top.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_ic_top.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_dc_ram.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32_bw.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_freeze.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_spram_128x32.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_dc_fsm.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_wb_biu.v
-../../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x22.v
-../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_biu.v
-../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_module.v
-../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v
-../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_defines.v
-../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_defines.v
-../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_crc32.v
-../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_biu.v
-../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_defines.v
-../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_status_reg.v
-../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_top.v
-../../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog/tap_top.v
-../../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog/tap_defines.v
-../../rtl/verilog/uart16550/rtl/verilog/uart_top.v
-../../rtl/verilog/uart16550/rtl/verilog/uart_sync_flops.v
-../../rtl/verilog/uart16550/rtl/verilog/uart_transmitter.v
-../../rtl/verilog/uart16550/rtl/verilog/uart_debug_if.v
-../../rtl/verilog/uart16550/rtl/verilog/uart_wb.v
-../../rtl/verilog/uart16550/rtl/verilog/uart_receiver.v
-../../rtl/verilog/uart16550/rtl/verilog/uart_tfifo.v
-../../rtl/verilog/uart16550/rtl/verilog/uart_regs.v
-../../rtl/verilog/uart16550/rtl/verilog/uart_rfifo.v
-../../rtl/verilog/uart16550/rtl/verilog/uart_defines.v
-../../rtl/verilog/uart16550/rtl/verilog/raminfr.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_cop.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_registers.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_rxethmac.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_miim.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_top.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_rxaddrcheck.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_outputcontrol.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_rxstatem.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_txethmac.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_wishbone.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_maccontrol.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_txstatem.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_defines.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_spram_256x32.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_shiftreg.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_clockgen.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_crc.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_rxcounters.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_macstatus.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_random.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_register.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_fifo.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_receivecontrol.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_transmitcontrol.v
-../../rtl/verilog/ethmac/rtl/verilog/eth_txcounters.v
sim/bin/minsoc_model_complete.txt
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: sim/bin/minsoc_model.txt
===================================================================
--- sim/bin/minsoc_model.txt (nonexistent)
+++ sim/bin/minsoc_model.txt (revision 17)
@@ -0,0 +1,137 @@
++incdir+../../bench/verilog
++incdir+../../bench/verilog/vpi
++incdir+../../bench/verilog/sim_lib
++incdir+../../rtl/verilog
++incdir+../../rtl/verilog/minsoc_startup
++incdir+../../rtl/verilog/or1200/rtl/verilog
++incdir+../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog
++incdir+../../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog
++incdir+../../rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_rtl
++incdir+../../rtl/verilog/uart16550/rtl/verilog
++incdir+../../rtl/verilog/ethmac/rtl/verilog
+../../bench/verilog/minsoc_bench_defines.v
+../../bench/verilog/minsoc_bench.v
+../../bench/verilog/minsoc_memory_model.v
+#../../bench/verilog/tb_eth_defines.v
+#../../bench/verilog/eth_phy_defines.v
+#../../bench/verilog/eth_phy.v
+../../bench/verilog/vpi/dbg_comm_vpi.v
+../../bench/verilog/sim_lib/fpga_memory_primitives.v
+../../rtl/verilog/minsoc_top.v
+../../rtl/verilog/minsoc_startup/spi_top.v
+../../rtl/verilog/minsoc_startup/spi_defines.v
+../../rtl/verilog/minsoc_startup/spi_shift.v
+../../rtl/verilog/minsoc_startup/spi_clgen.v
+../../rtl/verilog/minsoc_startup/OR1K_startup_generic.v
+../../rtl/verilog/minsoc_tc_top.v
+../../rtl/verilog/minsoc_onchip_ram.v
+../../rtl/verilog/minsoc_clock_manager.v
+#../../rtl/verilog/minsoc_onchip_ram_top.v
+../../rtl/verilog/minsoc_defines.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_spram_512x20.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x24.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_du.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32_bw.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_rf.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_alu.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_top.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_lsu.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_dc_top.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_cpu.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_gmultp2_32x32.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_immu_top.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_dpram_256x32.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_tt.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_iwb_biu.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_rfram_generic.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_dc_tag.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x8.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_ic_tag.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x14.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_spram_32x24.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_dpram_32x32.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_xcv_ram32x8d.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x8.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_mem2reg.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_pm.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_spram_256x21.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_operandmuxes.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_pic.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_cfgr.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_if.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_qmem_top.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_genpc.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_defines.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_wbmux.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_ic_ram.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_tlb.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_sb_fifo.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_sprs.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_tpram_32x32.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_ctrl.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_sb.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_mult_mac.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_ic_fsm.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_amultp2_32x32.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_reg2mem.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_except.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_top.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_ic_top.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_dc_ram.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32_bw.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_freeze.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_spram_128x32.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_dc_fsm.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_wb_biu.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x22.v
+../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_biu.v
+../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_module.v
+../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v
+../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_defines.v
+../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_defines.v
+../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_crc32.v
+../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_biu.v
+../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_defines.v
+../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_status_reg.v
+../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_top.v
+../../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog/tap_top.v
+../../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog/tap_defines.v
+../../rtl/verilog/uart16550/rtl/verilog/uart_top.v
+../../rtl/verilog/uart16550/rtl/verilog/uart_sync_flops.v
+../../rtl/verilog/uart16550/rtl/verilog/uart_transmitter.v
+../../rtl/verilog/uart16550/rtl/verilog/uart_debug_if.v
+../../rtl/verilog/uart16550/rtl/verilog/uart_wb.v
+../../rtl/verilog/uart16550/rtl/verilog/uart_receiver.v
+../../rtl/verilog/uart16550/rtl/verilog/uart_tfifo.v
+../../rtl/verilog/uart16550/rtl/verilog/uart_regs.v
+../../rtl/verilog/uart16550/rtl/verilog/uart_rfifo.v
+../../rtl/verilog/uart16550/rtl/verilog/uart_defines.v
+../../rtl/verilog/uart16550/rtl/verilog/raminfr.v
+../../rtl/verilog/ethmac/rtl/verilog/eth_cop.v
+../../rtl/verilog/ethmac/rtl/verilog/eth_registers.v
+../../rtl/verilog/ethmac/rtl/verilog/eth_rxethmac.v
+../../rtl/verilog/ethmac/rtl/verilog/eth_miim.v
+../../rtl/verilog/ethmac/rtl/verilog/eth_top.v
+../../rtl/verilog/ethmac/rtl/verilog/eth_rxaddrcheck.v
+../../rtl/verilog/ethmac/rtl/verilog/eth_outputcontrol.v
+../../rtl/verilog/ethmac/rtl/verilog/eth_rxstatem.v
+../../rtl/verilog/ethmac/rtl/verilog/eth_txethmac.v
+../../rtl/verilog/ethmac/rtl/verilog/eth_wishbone.v
+../../rtl/verilog/ethmac/rtl/verilog/eth_maccontrol.v
+../../rtl/verilog/ethmac/rtl/verilog/eth_txstatem.v
+../../rtl/verilog/ethmac/rtl/verilog/eth_defines.v
+../../rtl/verilog/ethmac/rtl/verilog/eth_spram_256x32.v
+../../rtl/verilog/ethmac/rtl/verilog/eth_shiftreg.v
+../../rtl/verilog/ethmac/rtl/verilog/eth_clockgen.v
+../../rtl/verilog/ethmac/rtl/verilog/eth_crc.v
+../../rtl/verilog/ethmac/rtl/verilog/eth_rxcounters.v
+../../rtl/verilog/ethmac/rtl/verilog/eth_macstatus.v
+../../rtl/verilog/ethmac/rtl/verilog/eth_random.v
+../../rtl/verilog/ethmac/rtl/verilog/eth_register.v
+../../rtl/verilog/ethmac/rtl/verilog/eth_fifo.v
+../../rtl/verilog/ethmac/rtl/verilog/eth_receivecontrol.v
+../../rtl/verilog/ethmac/rtl/verilog/eth_transmitcontrol.v
+../../rtl/verilog/ethmac/rtl/verilog/eth_txcounters.v
sim/bin/minsoc_model.txt
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: sim/bin/minsoc_memory.txt
===================================================================
--- sim/bin/minsoc_memory.txt (nonexistent)
+++ sim/bin/minsoc_memory.txt (revision 17)
@@ -0,0 +1,137 @@
++incdir+../../bench/verilog
++incdir+../../bench/verilog/vpi
++incdir+../../bench/verilog/sim_lib
++incdir+../../rtl/verilog
++incdir+../../rtl/verilog/minsoc_startup
++incdir+../../rtl/verilog/or1200/rtl/verilog
++incdir+../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog
++incdir+../../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog
++incdir+../../rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_rtl
++incdir+../../rtl/verilog/uart16550/rtl/verilog
++incdir+../../rtl/verilog/ethmac/rtl/verilog
+../../bench/verilog/minsoc_bench_defines.v
+../../bench/verilog/minsoc_bench.v
+#../../bench/verilog/minsoc_memory_model.v
+#../../bench/verilog/tb_eth_defines.v
+#../../bench/verilog/eth_phy_defines.v
+#../../bench/verilog/eth_phy.v
+../../bench/verilog/vpi/dbg_comm_vpi.v
+../../bench/verilog/sim_lib/fpga_memory_primitives.v
+../../rtl/verilog/minsoc_top.v
+../../rtl/verilog/minsoc_startup/spi_top.v
+../../rtl/verilog/minsoc_startup/spi_defines.v
+../../rtl/verilog/minsoc_startup/spi_shift.v
+../../rtl/verilog/minsoc_startup/spi_clgen.v
+../../rtl/verilog/minsoc_startup/OR1K_startup_generic.v
+../../rtl/verilog/minsoc_tc_top.v
+../../rtl/verilog/minsoc_onchip_ram.v
+../../rtl/verilog/minsoc_clock_manager.v
+../../rtl/verilog/minsoc_onchip_ram_top.v
+../../rtl/verilog/minsoc_defines.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_spram_512x20.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x24.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_du.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32_bw.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_rf.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_alu.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_top.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_lsu.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_dc_top.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_cpu.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_gmultp2_32x32.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_immu_top.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_dpram_256x32.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_tt.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_iwb_biu.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_rfram_generic.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_dc_tag.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x8.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_ic_tag.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x14.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_spram_32x24.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_dpram_32x32.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_xcv_ram32x8d.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x8.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_mem2reg.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_pm.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_spram_256x21.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_operandmuxes.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_pic.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_cfgr.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_if.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_qmem_top.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_genpc.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_defines.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_wbmux.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_ic_ram.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_tlb.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_sb_fifo.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_sprs.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_tpram_32x32.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_ctrl.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_sb.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_mult_mac.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_ic_fsm.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_amultp2_32x32.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_reg2mem.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_except.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_top.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_ic_top.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_dc_ram.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32_bw.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_freeze.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_spram_128x32.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_dc_fsm.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_wb_biu.v
+../../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x22.v
+../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_biu.v
+../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_module.v
+../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v
+../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_defines.v
+../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_defines.v
+../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_crc32.v
+../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_biu.v
+../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_defines.v
+../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_status_reg.v
+../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_top.v
+../../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog/tap_top.v
+../../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog/tap_defines.v
+../../rtl/verilog/uart16550/rtl/verilog/uart_top.v
+../../rtl/verilog/uart16550/rtl/verilog/uart_sync_flops.v
+../../rtl/verilog/uart16550/rtl/verilog/uart_transmitter.v
+../../rtl/verilog/uart16550/rtl/verilog/uart_debug_if.v
+../../rtl/verilog/uart16550/rtl/verilog/uart_wb.v
+../../rtl/verilog/uart16550/rtl/verilog/uart_receiver.v
+../../rtl/verilog/uart16550/rtl/verilog/uart_tfifo.v
+../../rtl/verilog/uart16550/rtl/verilog/uart_regs.v
+../../rtl/verilog/uart16550/rtl/verilog/uart_rfifo.v
+../../rtl/verilog/uart16550/rtl/verilog/uart_defines.v
+../../rtl/verilog/uart16550/rtl/verilog/raminfr.v
+../../rtl/verilog/ethmac/rtl/verilog/eth_cop.v
+../../rtl/verilog/ethmac/rtl/verilog/eth_registers.v
+../../rtl/verilog/ethmac/rtl/verilog/eth_rxethmac.v
+../../rtl/verilog/ethmac/rtl/verilog/eth_miim.v
+../../rtl/verilog/ethmac/rtl/verilog/eth_top.v
+../../rtl/verilog/ethmac/rtl/verilog/eth_rxaddrcheck.v
+../../rtl/verilog/ethmac/rtl/verilog/eth_outputcontrol.v
+../../rtl/verilog/ethmac/rtl/verilog/eth_rxstatem.v
+../../rtl/verilog/ethmac/rtl/verilog/eth_txethmac.v
+../../rtl/verilog/ethmac/rtl/verilog/eth_wishbone.v
+../../rtl/verilog/ethmac/rtl/verilog/eth_maccontrol.v
+../../rtl/verilog/ethmac/rtl/verilog/eth_txstatem.v
+../../rtl/verilog/ethmac/rtl/verilog/eth_defines.v
+../../rtl/verilog/ethmac/rtl/verilog/eth_spram_256x32.v
+../../rtl/verilog/ethmac/rtl/verilog/eth_shiftreg.v
+../../rtl/verilog/ethmac/rtl/verilog/eth_clockgen.v
+../../rtl/verilog/ethmac/rtl/verilog/eth_crc.v
+../../rtl/verilog/ethmac/rtl/verilog/eth_rxcounters.v
+../../rtl/verilog/ethmac/rtl/verilog/eth_macstatus.v
+../../rtl/verilog/ethmac/rtl/verilog/eth_random.v
+../../rtl/verilog/ethmac/rtl/verilog/eth_register.v
+../../rtl/verilog/ethmac/rtl/verilog/eth_fifo.v
+../../rtl/verilog/ethmac/rtl/verilog/eth_receivecontrol.v
+../../rtl/verilog/ethmac/rtl/verilog/eth_transmitcontrol.v
+../../rtl/verilog/ethmac/rtl/verilog/eth_txcounters.v
sim/bin/minsoc_memory.txt
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property