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/bench/verilog/minsoc_bench_defines.v

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/rtl/verilog/minsoc_defines.v File deleted

rtl/verilog/minsoc_defines.v Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: backend/ml509.ucf =================================================================== --- backend/ml509.ucf (revision 63) +++ backend/ml509.ucf (nonexistent) @@ -1,45 +0,0 @@ -NET clk LOC="AH15" | PERIOD=10ns | IOSTANDARD=LVCMOS33; # Bank 4, Vcco=3.3V, No DCI -NET reset LOC="E9" | PULLUP | IOSTANDARD=LVDCI_33; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -NET uart_srx LOC="AG15" | IOSTANDARD=LVCMOS33; # Bank 4, Vcco=3.3V, No DCI -NET uart_stx LOC="AG20" | IOSTANDARD=LVCMOS33; # Bank 4, Vcco=3.3V, No DCI - -## #------------------------------------------------------------------------------ -## # IO Pad Location Constraints / Properties for Ethernet -## #------------------------------------------------------------------------------ - -#NET eth_col LOC = B32 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE; -#NET eth_crs LOC = E34 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE; -#NET eth_rx_dv LOC = E32 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE; -#NET eth_rx_clk LOC = H17 | IOSTANDARD = LVCMOS25; -#NET eth_rxd<3> LOC = C32 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE; -#NET eth_rxd<2> LOC = C33 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE; -#NET eth_rxd<1> LOC = B33 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE; -#NET eth_rxd<0> LOC = A33 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE; - -#NET eth_rx_er LOC = E33 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE; -#NET eth_tx_clk LOC = K17 | IOSTANDARD = LVCMOS25; -#NET eth_trste LOC = J14 | IOSTANDARD = LVCMOS25 | PULLUP | TIG; # PHY_RESET pin on phy -#NET eth_txd<3> LOC = AH10 | IOSTANDARD = LVDCI_33; -#NET eth_txd<2> LOC = AH9 | IOSTANDARD = LVDCI_33; -#NET eth_txd<1> LOC = AE11 | IOSTANDARD = LVDCI_33; -#NET eth_txd<0> LOC = AF11 | IOSTANDARD = LVDCI_33; -#NET eth_tx_en LOC = AJ10 | IOSTANDARD = LVDCI_33; -#NET eth_tx_er LOC = AJ9 | IOSTANDARD = LVDCI_33; - -## PHY Serial Management Interface pins -#NET eth_mdc LOC = H19 | IOSTANDARD = LVCMOS25; -#NET eth_mdio LOC = H13 | IOSTANDARD = LVCMOS25; - -## # Timing Constraints (these are recommended in documentation and -## # are unaltered except for the TIG) -#NET "eth_rx_clk_BUFGP" TNM_NET = "RXCLK_GRP"; -#NET "eth_tx_clk_BUFGP" TNM_NET = "TXCLK_GRP"; -#TIMESPEC "TSTXOUT" = FROM "TXCLK_GRP" TO "PADS" 10 ns; -#TIMESPEC "TSRXIN" = FROM "PADS" TO "RXCLK_GRP" 6 ns; - -## # Timing ignores (to specify unconstrained paths) -#FIXME? NET "*clkgen0/wb_clk_o" TNM_NET = "sys_clk"; # Wishbone clock -#TIMESPEC "TS_PHYTX_OPB" = FROM "TXCLK_GRP" TO "sys_clk" TIG; -#TIMESPEC "TS_OPB_PHYTX" = FROM "sys_clk" TO "TXCLK_GRP" TIG; -#TIMESPEC "TS_PHYRX_OPB" = FROM "RXCLK_GRP" TO "sys_clk" TIG; -#TIMESPEC "TS_OPB_PHYRX" = FROM "sys_clk" TO "RXCLK_GRP" TIG; Index: backend/spartan3e_starter_kit.ucf =================================================================== --- backend/spartan3e_starter_kit.ucf (revision 63) +++ backend/spartan3e_starter_kit.ucf (nonexistent) @@ -1,64 +0,0 @@ -# -# Soldered 50MHz clock. -# -NET "clk" LOC = "C9"; - -# -# Use button "south" as reset. -# -NET "reset" LOC = "K17" | PULLDOWN ; - -# -# UART serial port (RS232 DCE) - connector DB9 female. -# -NET "uart_srx" LOC = "R7"; -NET "uart_stx" LOC = "M14" | DRIVE = 8 | SLEW = SLOW ; - -########################### -## -## ETH -## -#NET "eth_txd(3)" LOC = "t5"; -#NET "eth_txd(2)" LOC = "r5"; -#NET "eth_txd(1)" LOC = "t15"; -#NET "eth_txd(0)" LOC = "r11"; -# -#NET "eth_tx_en" LOC = "p15"; -#NET "eth_tx_clk" LOC = "t7" | CLOCK_DEDICATED_ROUTE = FALSE; -#NET "eth_tx_er" LOC = "r6"; -# -#NET "eth_rxd(3)" LOC = "v14"; -#NET "eth_rxd(2)" LOC = "u11"; -#NET "eth_rxd(1)" LOC = "t11"; -#NET "eth_rxd(0)" LOC = "v8"; -# -#NET "eth_rx_er" LOC = "u14"; -#NET "eth_rx_dv" LOC = "v2"; -# -#NET "eth_rx_clk" LOC = "v3" | CLOCK_DEDICATED_ROUTE = FALSE; -# -#NET "eth_mdio" LOC = "u5" | PULLUP; -#NET "eth_crs" LOC = "u13"; -#NET "eth_col" LOC = "u6"; -#NET "eth_mdc" LOC = "p9"; -# -#NET "eth_trste" LOC = "p13"; #put it to a non connected FPGA pin (starter kit schematic BANK3) -# -#NET "eth_fds_mdint" LOC = "r13" | PULLUP; #put it to a non connected FPGA pin (starter kit schematic BANK3)(pullup not to generate interrupts) -########################### - -# -# JTAG signals - on J4 6-pin accessory header. -# - -#NET "jtag_tms" LOC = "D7" | PULLDOWN ; -#NET "jtag_tdi" LOC = "C7" | PULLDOWN ; -#NET "jtag_tdo" LOC = "F8" | SLEW = FAST | DRIVE = 8 ; -#NET "jtag_tck" LOC = "E8" | PULLDOWN ; - -#net "jtag_gnd" loc = "k2"; #put it to a non connected FPGA pin (starter kit schematic BANK3) -#net "jtag_vref" loc = "k7"; #put it to a non connected FPGA pin (starter kit schematic BANK3) - -# -# End of file. -#

backend/spartan3e_starter_kit.ucf Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: backend/spartan3a_dsp_kit.ucf =================================================================== --- backend/spartan3a_dsp_kit.ucf (revision 63) +++ backend/spartan3a_dsp_kit.ucf (nonexistent) @@ -1,72 +0,0 @@ -########################### -## -## Global signals -## -net "clk" loc = "f13"; #125MHz clock -net "reset" loc = "j17"; #SW5 -########################### - -########################### -## -## JTAG -## -#net "jtag_tms" loc = "aa23"; #SAM D0 -#net "jtag_tdi" loc = "u20"; #SAM D2 -#net "jtag_tdo" loc = "aa25"; #SAM D4 -#net "jtag_tck" loc = "u18" | CLOCK_DEDICATED_ROUTE = FALSE; #SAM D6 -#net "jtag_gnd" loc = "y23"; #SAM D8 -#net "jtag_vref" loc = "t20"; #SAM D10 -########################### - -############################# -## -## SPI Flash External Memory -## -#NET "spi_flash_mosi" LOC = "ab15"; -#NET "spi_flash_miso" LOC = "af24"; -#NET "spi_flash_sclk" LOC = "ae24"; -#NET "spi_flash_ss(1)" LOC = "ac25"; -#NET "spi_flash_ss(0)" LOC = "aa7"; -########################### - -########################### -## -## UART -## -net "uart_stx" loc = "p22"; -net "uart_srx" loc = "n21"; -########################### - -########################### -## -## ETH -## -#NET "eth_txd(3)" LOC = "b1"; -#NET "eth_txd(2)" LOC = "b2"; -#NET "eth_txd(1)" LOC = "j9"; -#NET "eth_txd(0)" LOC = "j8"; -# -#NET "eth_tx_en" LOC = "d3"; -#NET "eth_tx_clk" LOC = "p2"; -#NET "eth_tx_er" LOC = "e4"; -# -#NET "eth_rxd(3)" LOC = "d2"; -#NET "eth_rxd(2)" LOC = "g5"; -#NET "eth_rxd(1)" LOC = "g2"; -#NET "eth_rxd(0)" LOC = "c2"; -# -#NET "eth_rx_er" LOC = "j3"; -#NET "eth_rx_dv" LOC = "d1"; -# -#NET "eth_rx_clk" LOC = "p1"; -# -#NET "eth_mdio" LOC = "f5" | PULLUP; -#NET "eth_crs" LOC = "g1"; -#NET "eth_col" LOC = "y3"; -#NET "eth_mdc" LOC = "f4"; -# -#NET "eth_trste" LOC = "g4"; -# -#NET "eth_fds_mdint" LOC = "j1"; -########################### -

backend/spartan3a_dsp_kit.ucf Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: backend/ml509/ml509.ucf =================================================================== --- backend/ml509/ml509.ucf (nonexistent) +++ backend/ml509/ml509.ucf (revision 64) @@ -0,0 +1,45 @@ +NET clk LOC="AH15" | PERIOD=10ns | IOSTANDARD=LVCMOS33; # Bank 4, Vcco=3.3V, No DCI +NET reset LOC="E9" | PULLUP | IOSTANDARD=LVDCI_33; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors +NET uart_srx LOC="AG15" | IOSTANDARD=LVCMOS33; # Bank 4, Vcco=3.3V, No DCI +NET uart_stx LOC="AG20" | IOSTANDARD=LVCMOS33; # Bank 4, Vcco=3.3V, No DCI + +## #------------------------------------------------------------------------------ +## # IO Pad Location Constraints / Properties for Ethernet +## #------------------------------------------------------------------------------ + +#NET eth_col LOC = B32 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE; +#NET eth_crs LOC = E34 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE; +#NET eth_rx_dv LOC = E32 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE; +#NET eth_rx_clk LOC = H17 | IOSTANDARD = LVCMOS25; +#NET eth_rxd<3> LOC = C32 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE; +#NET eth_rxd<2> LOC = C33 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE; +#NET eth_rxd<1> LOC = B33 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE; +#NET eth_rxd<0> LOC = A33 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE; + +#NET eth_rx_er LOC = E33 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE; +#NET eth_tx_clk LOC = K17 | IOSTANDARD = LVCMOS25; +#NET eth_trste LOC = J14 | IOSTANDARD = LVCMOS25 | PULLUP | TIG; # PHY_RESET pin on phy +#NET eth_txd<3> LOC = AH10 | IOSTANDARD = LVDCI_33; +#NET eth_txd<2> LOC = AH9 | IOSTANDARD = LVDCI_33; +#NET eth_txd<1> LOC = AE11 | IOSTANDARD = LVDCI_33; +#NET eth_txd<0> LOC = AF11 | IOSTANDARD = LVDCI_33; +#NET eth_tx_en LOC = AJ10 | IOSTANDARD = LVDCI_33; +#NET eth_tx_er LOC = AJ9 | IOSTANDARD = LVDCI_33; + +## PHY Serial Management Interface pins +#NET eth_mdc LOC = H19 | IOSTANDARD = LVCMOS25; +#NET eth_mdio LOC = H13 | IOSTANDARD = LVCMOS25; + +## # Timing Constraints (these are recommended in documentation and +## # are unaltered except for the TIG) +#NET "eth_rx_clk_BUFGP" TNM_NET = "RXCLK_GRP"; +#NET "eth_tx_clk_BUFGP" TNM_NET = "TXCLK_GRP"; +#TIMESPEC "TSTXOUT" = FROM "TXCLK_GRP" TO "PADS" 10 ns; +#TIMESPEC "TSRXIN" = FROM "PADS" TO "RXCLK_GRP" 6 ns; + +## # Timing ignores (to specify unconstrained paths) +#FIXME? NET "*clkgen0/wb_clk_o" TNM_NET = "sys_clk"; # Wishbone clock +#TIMESPEC "TS_PHYTX_OPB" = FROM "TXCLK_GRP" TO "sys_clk" TIG; +#TIMESPEC "TS_OPB_PHYTX" = FROM "sys_clk" TO "TXCLK_GRP" TIG; +#TIMESPEC "TS_PHYRX_OPB" = FROM "RXCLK_GRP" TO "sys_clk" TIG; +#TIMESPEC "TS_OPB_PHYRX" = FROM "sys_clk" TO "RXCLK_GRP" TIG; Index: backend/spartan3a_dsp_kit/configure =================================================================== --- backend/spartan3a_dsp_kit/configure (nonexistent) +++ backend/spartan3a_dsp_kit/configure (revision 64) @@ -0,0 +1,81 @@ +#!/bin/bash + +#new boards have to udpate this +BOARD=spartan3a_dsp_kit #this has to have the name of the directory this file is in +DEVICE_PART='xc3sd1800a-4-fg676' +CONSTRAINT_FILE='spartan3a_dsp_kit.ucf' +#~new boards update + +#system workings +MINSOC_DIR=`pwd`/../.. +BACKEND_DIR=$MINSOC_DIR/backend +SYN_DIR=$MINSOC_DIR/syn +SYNSRC_DIR=$SYN_DIR/src +SYNSUPPORT_DIR=$SYN_DIR/buildSupport + +SYN_FILES=(eth_top.xst uart_top.xst adbg_top.xst or1200_top.xst minsoc_top.xst Makefile) + +FIND_PART='DEVICE_PART' +FIND_CONSTRAINT='CONSTRAINT_FILE' + +BOARD_DIR=$BACKEND_DIR/$BOARD +BOARD_FILES=(board.h orp.ld minsoc_defines.v $CONSTRAINT_FILE) + +in_minsoc=`pwd | grep minsoc/backend/${BOARD}$` +if [ -z $in_minsoc ] +then + echo "" + echo " !!!WARNING!!!" + echo "This script cannot be run out of a board directory inside minsoc/backend," + echo "because it relies on the directory structure of the minsoc system." + echo "" + exit 1 +fi + +echo "" +echo "Configuring SoC board's specific files for firmware compilation, " +echo "testbench generation and synthesis." +echo "Firmware and testbench looks for board specific files under minsoc/backend." +echo "Synthesis work under minsoc/syn." +echo "" +echo "" + +if [ $CONSTRAINT_FILE == 'NONE' ] +then + echo "Skipping synthesis preparation. Standard implementation can only be simulated." +else + echo "Device part for files under minsoc/syn/src will be patched and stored " + echo "temporarily." + echo "Afterwards, they are copied to minsoc/syn/buildSupport." + echo "__________________________________________________________________________" + echo "" + for file in "${SYN_FILES[@]}" + do + echo "Updating synthesis file, $file..." + echo "Copying $file to synthesis directory..." + echo "" + sed "s/$FIND_PART/$DEVICE_PART/g" $SYNSRC_DIR/$file > TMPFILE + sed "s/$FIND_CONSTRAINT/$CONSTRAINT_FILE/g" TMPFILE > TMPFILE2 && mv TMPFILE2 $SYNSUPPORT_DIR/$file + rm TMPFILE + done + + echo "Moving Makefile back from minsoc/syn/buildSupport to minsoc/syn..." + mv $SYNSUPPORT_DIR/Makefile $SYN_DIR +fi +echo "" +echo "" + + +echo "Copying board specific SoC files to backend directory." +echo "__________________________________________________________________________" +echo "" +for file in "${BOARD_FILES[@]}" +do + if [ $file != NONE ] + then + echo "Copying $file, to backend directory..." + cp $BOARD_DIR/$file $BACKEND_DIR + fi +done +echo "" +echo ""

backend/spartan3a_dsp_kit/configure Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: backend/spartan3a_dsp_kit/spartan3a_dsp_kit.ucf =================================================================== --- backend/spartan3a_dsp_kit/spartan3a_dsp_kit.ucf (nonexistent) +++ backend/spartan3a_dsp_kit/spartan3a_dsp_kit.ucf (revision 64) @@ -0,0 +1,72 @@ +########################### +## +## Global signals +## +net "clk" loc = "f13"; #125MHz clock +net "reset" loc = "j17"; #SW5 +########################### + +########################### +## +## JTAG +## +#net "jtag_tms" loc = "aa23"; #SAM D0 +#net "jtag_tdi" loc = "u20"; #SAM D2 +#net "jtag_tdo" loc = "aa25"; #SAM D4 +#net "jtag_tck" loc = "u18" | CLOCK_DEDICATED_ROUTE = FALSE; #SAM D6 +#net "jtag_gnd" loc = "y23"; #SAM D8 +#net "jtag_vref" loc = "t20"; #SAM D10 +########################### + +############################# +## +## SPI Flash External Memory +## +NET "spi_flash_mosi" LOC = "ab15"; +NET "spi_flash_miso" LOC = "af24"; +NET "spi_flash_sclk" LOC = "ae24"; +NET "spi_flash_ss(1)" LOC = "ac25"; +NET "spi_flash_ss(0)" LOC = "aa7"; +########################### + +########################### +## +## UART +## +net "uart_stx" loc = "p22"; +net "uart_srx" loc = "n21"; +########################### + +########################### +## +## ETH +## +NET "eth_txd(3)" LOC = "b1"; +NET "eth_txd(2)" LOC = "b2"; +NET "eth_txd(1)" LOC = "j9"; +NET "eth_txd(0)" LOC = "j8"; + +NET "eth_tx_en" LOC = "d3"; +NET "eth_tx_clk" LOC = "p2"; +NET "eth_tx_er" LOC = "e4"; + +NET "eth_rxd(3)" LOC = "d2"; +NET "eth_rxd(2)" LOC = "g5"; +NET "eth_rxd(1)" LOC = "g2"; +NET "eth_rxd(0)" LOC = "c2"; + +NET "eth_rx_er" LOC = "j3"; +NET "eth_rx_dv" LOC = "d1"; + +NET "eth_rx_clk" LOC = "p1"; + +NET "eth_mdio" LOC = "f5" | PULLUP; +NET "eth_crs" LOC = "g1"; +NET "eth_col" LOC = "y3"; +NET "eth_mdc" LOC = "f4"; + +NET "eth_trste" LOC = "g4"; + +NET "eth_fds_mdint" LOC = "j1"; +########################### +

backend/spartan3a_dsp_kit/spartan3a_dsp_kit.ucf Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: backend/spartan3a_dsp_kit/minsoc_defines.v =================================================================== --- backend/spartan3a_dsp_kit/minsoc_defines.v (nonexistent) +++ backend/spartan3a_dsp_kit/minsoc_defines.v (revision 64) @@ -0,0 +1,148 @@ +// +// Define FPGA manufacturer +// +//`define GENERIC_FPGA +//`define ALTERA_FPGA +`define XILINX_FPGA + +// +// Define Xilinx FPGA family +// +`ifdef XILINX_FPGA +//`define SPARTAN2 +//`define SPARTAN3 +//`define SPARTAN3E +`define SPARTAN3A +//`define VIRTEX +//`define VIRTEX2 +//`define VIRTEX4 +//`define VIRTEX5 + +// +// Define Altera FPGA family +// +`elsif ALTERA_FPGA +//`define ARRIA_GX +//`define ARRIA_II_GX +//`define CYCLONE_I +//`define CYCLONE_II +`define CYCLONE_III +//`define CYCLONE_III_LS +//`define CYCLONE_IV_E +//`define CYCLONE_IV_GS +//`define MAX_II +//`define MAX_V +//`define MAX3000A +//`define MAX7000AE +//`define MAX7000B +//`define MAX7000S +//`define STRATIX +//`define STRATIX_II +//`define STRATIX_II_GX +//`define STRATIX_III +`endif + +// +// Memory +// +`define MEMORY_ADR_WIDTH 13 //MEMORY_ADR_WIDTH IS NOT ALLOWED TO BE LESS THAN 12, + //memory is composed by blocks of address width 11 + //Address width of memory -> select memory depth, + //2 powers MEMORY_ADR_WIDTH defines the memory depth + //the memory data width is 32 bit, + //memory amount in Bytes = 4*memory depth + +// +// Memory type (uncomment something if ASIC or generic memory) +// +//`define GENERIC_MEMORY +//`define AVANT_ATP +//`define VIRAGE_SSP +//`define VIRTUALSILICON_SSP + + +// +// TAP selection +// +//`define GENERIC_TAP +`define FPGA_TAP + +// +// Clock Division selection +// +//`define NO_CLOCK_DIVISION +//`define GENERIC_CLOCK_DIVISION +`define FPGA_CLOCK_DIVISION // For Altera ALTPLL, only CYCLONE_III family has been tested. + +// +// Define division +// +`define CLOCK_DIVISOR 5 //in case of GENERIC_CLOCK_DIVISION the real value will be rounded + //down to an even value in FPGA case, check minsoc_clock_manager + //for allowed divisors. + //DO NOT USE CLOCK_DIVISOR = 1 COMMENT THE CLOCK DIVISION SELECTION + //INSTEAD. + +// +// Reset polarity +// +//`define NEGATIVE_RESET //rstn +`define POSITIVE_RESET //rst + +// +// Start-up circuit (only necessary later to load firmware automatically from SPI memory) +// +//`define START_UP + +// +// Connected modules +// +`define UART +`define ETHERNET + +// +// Ethernet reset +// +//`define ETH_RESET 1'b0 +`define ETH_RESET 1'b1 + +// +// Interrupts +// +`define APP_INT_RES1 1:0 +`define APP_INT_UART 2 +`define APP_INT_RES2 3 +`define APP_INT_ETH 4 +`define APP_INT_PS2 5 +`define APP_INT_RES3 19:6 + +// +// Address map +// +`define APP_ADDR_DEC_W 8 +`define APP_ADDR_SRAM `APP_ADDR_DEC_W'h00 +`define APP_ADDR_FLASH `APP_ADDR_DEC_W'h04 +`define APP_ADDR_DECP_W 4 +`define APP_ADDR_PERIP `APP_ADDR_DECP_W'h9 +`define APP_ADDR_SPI `APP_ADDR_DEC_W'h97 +`define APP_ADDR_ETH `APP_ADDR_DEC_W'h92 +`define APP_ADDR_AUDIO `APP_ADDR_DEC_W'h9d +`define APP_ADDR_UART `APP_ADDR_DEC_W'h90 +`define APP_ADDR_PS2 `APP_ADDR_DEC_W'h94 +`define APP_ADDR_RES1 `APP_ADDR_DEC_W'h9e +`define APP_ADDR_RES2 `APP_ADDR_DEC_W'h9f + +// +// Set-up GENERIC_TAP, GENERIC_MEMORY if GENERIC_FPGA was chosen +// and GENERIC_CLOCK_DIVISION if NO_CLOCK_DIVISION was not set +// +`ifdef GENERIC_FPGA + `undef FPGA_TAP + `undef FPGA_CLOCK_DIVISION + + `define GENERIC_TAP + `define GENERIC_MEMORY + `ifndef NO_CLOCK_DIVISION + `define GENERIC_CLOCK_DIVISION + `endif +`endif Index: backend/spartan3a_dsp_kit/board.h =================================================================== --- backend/spartan3a_dsp_kit/board.h (nonexistent) +++ backend/spartan3a_dsp_kit/board.h (revision 64) @@ -0,0 +1,40 @@ +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#define MC_ENABLED 0 + +#define IC_ENABLE 0 +#define IC_SIZE 8192 +#define DC_ENABLE 0 +#define DC_SIZE 8192 + + +#define IN_CLK 25000000 + + +#define STACK_SIZE 0x01000 + +#define UART_BAUD_RATE 115200 + +#define UART_BASE 0x90000000 +#define UART_IRQ 2 +#define ETH_BASE 0x92000000 +#define ETH_IRQ 4 +#define I2C_BASE 0x9D000000 +#define I2C_IRQ 3 +#define CAN_BASE 0x94000000 +#define CAN_IRQ 5 + +#define MC_BASE_ADDR 0x60000000 +#define SPI_BASE 0xa0000000 + +#define ETH_DATA_BASE 0xa8000000 /* Address for ETH_DATA */ + +#define ETH_MACADDR0 0x00 +#define ETH_MACADDR1 0x12 +#define ETH_MACADDR2 0x34 +#define ETH_MACADDR3 0x56 +#define ETH_MACADDR4 0x78 +#define ETH_MACADDR5 0x9a + +#endif

backend/spartan3a_dsp_kit/board.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: backend/spartan3a_dsp_kit/orp.ld =================================================================== --- backend/spartan3a_dsp_kit/orp.ld (nonexistent) +++ backend/spartan3a_dsp_kit/orp.ld (revision 64) @@ -0,0 +1,60 @@ +MEMORY + { + reset : ORIGIN = 0x00000000, LENGTH = 0x00000200 + vectors : ORIGIN = 0x00000200, LENGTH = 0x00001000 + ram : ORIGIN = 0x00001200, LENGTH = 0x0001EE00 /*0x20000 total*/ + } + +SECTIONS +{ + .reset : + { + *(.reset) + } > reset + + + + .vectors : + { + _vec_start = .; + *(.vectors) + _vec_end = .; + } > vectors + + .text : + { + *(.text) + } > ram + + .rodata : + { + *(.rodata) + *(.rodata.*) + } > ram + + .icm : + { + _icm_start = .; + *(.icm) + _icm_end = .; + } > ram + + .data : + { + _dst_beg = .; + *(.data) + _dst_end = .; + } > ram + + .bss : + { + *(.bss) + } > ram + + .stack (NOLOAD) : + { + *(.stack) + _src_addr = .; + } > ram + +}

backend/spartan3a_dsp_kit/orp.ld Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: backend/std/minsoc_defines.v =================================================================== --- backend/std/minsoc_defines.v (nonexistent) +++ backend/std/minsoc_defines.v (revision 64) @@ -0,0 +1,148 @@ +// +// Define FPGA manufacturer +// +`define GENERIC_FPGA +//`define ALTERA_FPGA +//`define XILINX_FPGA + +// +// Define Xilinx FPGA family +// +`ifdef XILINX_FPGA +//`define SPARTAN2 +//`define SPARTAN3 +//`define SPARTAN3E +`define SPARTAN3A +//`define VIRTEX +//`define VIRTEX2 +//`define VIRTEX4 +//`define VIRTEX5 + +// +// Define Altera FPGA family +// +`elsif ALTERA_FPGA +//`define ARRIA_GX +//`define ARRIA_II_GX +//`define CYCLONE_I +//`define CYCLONE_II +`define CYCLONE_III +//`define CYCLONE_III_LS +//`define CYCLONE_IV_E +//`define CYCLONE_IV_GS +//`define MAX_II +//`define MAX_V +//`define MAX3000A +//`define MAX7000AE +//`define MAX7000B +//`define MAX7000S +//`define STRATIX +//`define STRATIX_II +//`define STRATIX_II_GX +//`define STRATIX_III +`endif + +// +// Memory +// +`define MEMORY_ADR_WIDTH 13 //MEMORY_ADR_WIDTH IS NOT ALLOWED TO BE LESS THAN 12, + //memory is composed by blocks of address width 11 + //Address width of memory -> select memory depth, + //2 powers MEMORY_ADR_WIDTH defines the memory depth + //the memory data width is 32 bit, + //memory amount in Bytes = 4*memory depth + +// +// Memory type (uncomment something if ASIC or generic memory) +// +//`define GENERIC_MEMORY +//`define AVANT_ATP +//`define VIRAGE_SSP +//`define VIRTUALSILICON_SSP + + +// +// TAP selection +// +//`define GENERIC_TAP +`define FPGA_TAP + +// +// Clock Division selection +// +//`define NO_CLOCK_DIVISION +//`define GENERIC_CLOCK_DIVISION +`define FPGA_CLOCK_DIVISION // For Altera ALTPLL, only CYCLONE_III family has been tested. + +// +// Define division +// +`define CLOCK_DIVISOR 5 //in case of GENERIC_CLOCK_DIVISION the real value will be rounded + //down to an even value in FPGA case, check minsoc_clock_manager + //for allowed divisors. + //DO NOT USE CLOCK_DIVISOR = 1 COMMENT THE CLOCK DIVISION SELECTION + //INSTEAD. + +// +// Reset polarity +// +`define NEGATIVE_RESET //rstn +//`define POSITIVE_RESET //rst + +// +// Start-up circuit (only necessary later to load firmware automatically from SPI memory) +// +//`define START_UP + +// +// Connected modules +// +`define UART +`define ETHERNET + +// +// Ethernet reset +// +`define ETH_RESET 1'b0 +//`define ETH_RESET 1'b1 + +// +// Interrupts +// +`define APP_INT_RES1 1:0 +`define APP_INT_UART 2 +`define APP_INT_RES2 3 +`define APP_INT_ETH 4 +`define APP_INT_PS2 5 +`define APP_INT_RES3 19:6 + +// +// Address map +// +`define APP_ADDR_DEC_W 8 +`define APP_ADDR_SRAM `APP_ADDR_DEC_W'h00 +`define APP_ADDR_FLASH `APP_ADDR_DEC_W'h04 +`define APP_ADDR_DECP_W 4 +`define APP_ADDR_PERIP `APP_ADDR_DECP_W'h9 +`define APP_ADDR_SPI `APP_ADDR_DEC_W'h97 +`define APP_ADDR_ETH `APP_ADDR_DEC_W'h92 +`define APP_ADDR_AUDIO `APP_ADDR_DEC_W'h9d +`define APP_ADDR_UART `APP_ADDR_DEC_W'h90 +`define APP_ADDR_PS2 `APP_ADDR_DEC_W'h94 +`define APP_ADDR_RES1 `APP_ADDR_DEC_W'h9e +`define APP_ADDR_RES2 `APP_ADDR_DEC_W'h9f + +// +// Set-up GENERIC_TAP, GENERIC_MEMORY if GENERIC_FPGA was chosen +// and GENERIC_CLOCK_DIVISION if NO_CLOCK_DIVISION was not set +// +`ifdef GENERIC_FPGA + `undef FPGA_TAP + `undef FPGA_CLOCK_DIVISION + + `define GENERIC_TAP + `define GENERIC_MEMORY + `ifndef NO_CLOCK_DIVISION + `define GENERIC_CLOCK_DIVISION + `endif +`endif

backend/std/minsoc_defines.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: backend/std/board.h =================================================================== --- backend/std/board.h (nonexistent) +++ backend/std/board.h (revision 64) @@ -0,0 +1,40 @@ +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#define MC_ENABLED 0 + +#define IC_ENABLE 0 +#define IC_SIZE 8192 +#define DC_ENABLE 0 +#define DC_SIZE 8192 + + +#define IN_CLK 25000000 + + +#define STACK_SIZE 0x01000 + +#define UART_BAUD_RATE 115200 + +#define UART_BASE 0x90000000 +#define UART_IRQ 2 +#define ETH_BASE 0x92000000 +#define ETH_IRQ 4 +#define I2C_BASE 0x9D000000 +#define I2C_IRQ 3 +#define CAN_BASE 0x94000000 +#define CAN_IRQ 5 + +#define MC_BASE_ADDR 0x60000000 +#define SPI_BASE 0xa0000000 + +#define ETH_DATA_BASE 0xa8000000 /* Address for ETH_DATA */ + +#define ETH_MACADDR0 0x00 +#define ETH_MACADDR1 0x12 +#define ETH_MACADDR2 0x34 +#define ETH_MACADDR3 0x56 +#define ETH_MACADDR4 0x78 +#define ETH_MACADDR5 0x9a + +#endif

backend/std/board.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: backend/std/orp.ld =================================================================== --- backend/std/orp.ld (nonexistent) +++ backend/std/orp.ld (revision 64) @@ -0,0 +1,60 @@ +MEMORY + { + reset : ORIGIN = 0x00000000, LENGTH = 0x00000200 + vectors : ORIGIN = 0x00000200, LENGTH = 0x00001000 + ram : ORIGIN = 0x00001200, LENGTH = 0x00006E00 /*0x8000 total*/ + } + +SECTIONS +{ + .reset : + { + *(.reset) + } > reset + + + + .vectors : + { + _vec_start = .; + *(.vectors) + _vec_end = .; + } > vectors + + .text : + { + *(.text) + } > ram + + .rodata : + { + *(.rodata) + *(.rodata.*) + } > ram + + .icm : + { + _icm_start = .; + *(.icm) + _icm_end = .; + } > ram + + .data : + { + _dst_beg = .; + *(.data) + _dst_end = .; + } > ram + + .bss : + { + *(.bss) + } > ram + + .stack (NOLOAD) : + { + *(.stack) + _src_addr = .; + } > ram + +}

backend/std/orp.ld Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: backend/spartan3e_starter_kit/configure =================================================================== --- backend/spartan3e_starter_kit/configure (nonexistent) +++ backend/spartan3e_starter_kit/configure (revision 64) @@ -0,0 +1,81 @@ +#!/bin/bash + +#new boards have to udpate this +BOARD=spartan3e_starter_kit #this has to have the name of the directory this file is in +DEVICE_PART='xc3s500e-4-fg320' +CONSTRAINT_FILE='spartan3e_starter_kit.ucf' +#~new boards update + +#system workings +MINSOC_DIR=`pwd`/../.. +BACKEND_DIR=$MINSOC_DIR/backend +SYN_DIR=$MINSOC_DIR/syn +SYNSRC_DIR=$SYN_DIR/src +SYNSUPPORT_DIR=$SYN_DIR/buildSupport + +SYN_FILES=(eth_top.xst uart_top.xst adbg_top.xst or1200_top.xst minsoc_top.xst Makefile) + +FIND_PART='DEVICE_PART' +FIND_CONSTRAINT='CONSTRAINT_FILE' + +BOARD_DIR=$BACKEND_DIR/$BOARD +BOARD_FILES=(board.h orp.ld minsoc_defines.v $CONSTRAINT_FILE) + +in_minsoc=`pwd | grep minsoc/backend/${BOARD}$` +if [ -z $in_minsoc ] +then + echo "" + echo " !!!WARNING!!!" + echo "This script cannot be run out of a board directory inside minsoc/backend," + echo "because it relies on the directory structure of the minsoc system." + echo "" + exit 1 +fi + +echo "" +echo "Configuring SoC board's specific files for firmware compilation, " +echo "testbench generation and synthesis." +echo "Firmware and testbench looks for board specific files under minsoc/backend." +echo "Synthesis work under minsoc/syn." +echo "" +echo "" + +if [ $CONSTRAINT_FILE == 'NONE' ] +then + echo "Skipping synthesis preparation. Standard implementation can only be simulated." +else + echo "Device part for files under minsoc/syn/src will be patched and stored " + echo "temporarily." + echo "Afterwards, they are copied to minsoc/syn/buildSupport." + echo "__________________________________________________________________________" + echo "" + for file in "${SYN_FILES[@]}" + do + echo "Updating synthesis file, $file..." + echo "Copying $file to synthesis directory..." + echo "" + sed "s/$FIND_PART/$DEVICE_PART/g" $SYNSRC_DIR/$file > TMPFILE + sed "s/$FIND_CONSTRAINT/$CONSTRAINT_FILE/g" TMPFILE > TMPFILE2 && mv TMPFILE2 $SYNSUPPORT_DIR/$file + rm TMPFILE + done + + echo "Moving Makefile back from minsoc/syn/buildSupport to minsoc/syn..." + mv $SYNSUPPORT_DIR/Makefile $SYN_DIR +fi +echo "" +echo "" + + +echo "Copying board specific SoC files to backend directory." +echo "__________________________________________________________________________" +echo "" +for file in "${BOARD_FILES[@]}" +do + if [ $file != NONE ] + then + echo "Copying $file, to backend directory..." + cp $BOARD_DIR/$file $BACKEND_DIR + fi +done +echo "" +echo ""

backend/spartan3e_starter_kit/configure Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: backend/spartan3e_starter_kit/spartan3e_starter_kit.ucf =================================================================== --- backend/spartan3e_starter_kit/spartan3e_starter_kit.ucf (nonexistent) +++ backend/spartan3e_starter_kit/spartan3e_starter_kit.ucf (revision 64) @@ -0,0 +1,64 @@ +# +# Soldered 50MHz clock. +# +NET "clk" LOC = "C9"; + +# +# Use button "south" as reset. +# +NET "reset" LOC = "K17" | PULLDOWN ; + +# +# UART serial port (RS232 DCE) - connector DB9 female. +# +NET "uart_srx" LOC = "R7"; +NET "uart_stx" LOC = "M14" | DRIVE = 8 | SLEW = SLOW ; + +########################### +## +## ETH +## +#NET "eth_txd(3)" LOC = "t5"; +#NET "eth_txd(2)" LOC = "r5"; +#NET "eth_txd(1)" LOC = "t15"; +#NET "eth_txd(0)" LOC = "r11"; +# +#NET "eth_tx_en" LOC = "p15"; +#NET "eth_tx_clk" LOC = "t7" | CLOCK_DEDICATED_ROUTE = FALSE; +#NET "eth_tx_er" LOC = "r6"; +# +#NET "eth_rxd(3)" LOC = "v14"; +#NET "eth_rxd(2)" LOC = "u11"; +#NET "eth_rxd(1)" LOC = "t11"; +#NET "eth_rxd(0)" LOC = "v8"; +# +#NET "eth_rx_er" LOC = "u14"; +#NET "eth_rx_dv" LOC = "v2"; +# +#NET "eth_rx_clk" LOC = "v3" | CLOCK_DEDICATED_ROUTE = FALSE; +# +#NET "eth_mdio" LOC = "u5" | PULLUP; +#NET "eth_crs" LOC = "u13"; +#NET "eth_col" LOC = "u6"; +#NET "eth_mdc" LOC = "p9"; +# +#NET "eth_trste" LOC = "p13"; #put it to a non connected FPGA pin (starter kit schematic BANK3) +# +#NET "eth_fds_mdint" LOC = "r13" | PULLUP; #put it to a non connected FPGA pin (starter kit schematic BANK3)(pullup not to generate interrupts) +########################### + +# +# JTAG signals - on J4 6-pin accessory header. +# + +#NET "jtag_tms" LOC = "D7" | PULLDOWN ; +#NET "jtag_tdi" LOC = "C7" | PULLDOWN ; +#NET "jtag_tdo" LOC = "F8" | SLEW = FAST | DRIVE = 8 ; +#NET "jtag_tck" LOC = "E8" | PULLDOWN ; + +#net "jtag_gnd" loc = "k2"; #put it to a non connected FPGA pin (starter kit schematic BANK3) +#net "jtag_vref" loc = "k7"; #put it to a non connected FPGA pin (starter kit schematic BANK3) + +# +# End of file. +#

backend/spartan3e_starter_kit/spartan3e_starter_kit.ucf Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: backend/spartan3e_starter_kit/minsoc_defines.v =================================================================== --- backend/spartan3e_starter_kit/minsoc_defines.v (nonexistent) +++ backend/spartan3e_starter_kit/minsoc_defines.v (revision 64) @@ -0,0 +1,148 @@ +// +// Define FPGA manufacturer +// +//`define GENERIC_FPGA +//`define ALTERA_FPGA +`define XILINX_FPGA + +// +// Define Xilinx FPGA family +// +`ifdef XILINX_FPGA +//`define SPARTAN2 +//`define SPARTAN3 +`define SPARTAN3E +//`define SPARTAN3A +//`define VIRTEX +//`define VIRTEX2 +//`define VIRTEX4 +//`define VIRTEX5 + +// +// Define Altera FPGA family +// +`elsif ALTERA_FPGA +//`define ARRIA_GX +//`define ARRIA_II_GX +//`define CYCLONE_I +//`define CYCLONE_II +`define CYCLONE_III +//`define CYCLONE_III_LS +//`define CYCLONE_IV_E +//`define CYCLONE_IV_GS +//`define MAX_II +//`define MAX_V +//`define MAX3000A +//`define MAX7000AE +//`define MAX7000B +//`define MAX7000S +//`define STRATIX +//`define STRATIX_II +//`define STRATIX_II_GX +//`define STRATIX_III +`endif + +// +// Memory +// +`define MEMORY_ADR_WIDTH 13 //MEMORY_ADR_WIDTH IS NOT ALLOWED TO BE LESS THAN 12, + //memory is composed by blocks of address width 11 + //Address width of memory -> select memory depth, + //2 powers MEMORY_ADR_WIDTH defines the memory depth + //the memory data width is 32 bit, + //memory amount in Bytes = 4*memory depth + +// +// Memory type (uncomment something if ASIC or generic memory) +// +//`define GENERIC_MEMORY +//`define AVANT_ATP +//`define VIRAGE_SSP +//`define VIRTUALSILICON_SSP + + +// +// TAP selection +// +//`define GENERIC_TAP +`define FPGA_TAP + +// +// Clock Division selection +// +//`define NO_CLOCK_DIVISION +//`define GENERIC_CLOCK_DIVISION +`define FPGA_CLOCK_DIVISION // For Altera ALTPLL, only CYCLONE_III family has been tested. + +// +// Define division +// +`define CLOCK_DIVISOR 2 //in case of GENERIC_CLOCK_DIVISION the real value will be rounded + //down to an even value in FPGA case, check minsoc_clock_manager + //for allowed divisors. + //DO NOT USE CLOCK_DIVISOR = 1 COMMENT THE CLOCK DIVISION SELECTION + //INSTEAD. + +// +// Reset polarity +// +//`define NEGATIVE_RESET //rstn +`define POSITIVE_RESET //rst + +// +// Start-up circuit (only necessary later to load firmware automatically from SPI memory) +// +//`define START_UP + +// +// Connected modules +// +`define UART +//`define ETHERNET + +// +// Ethernet reset +// +`define ETH_RESET 1'b0 +//`define ETH_RESET 1'b1 + +// +// Interrupts +// +`define APP_INT_RES1 1:0 +`define APP_INT_UART 2 +`define APP_INT_RES2 3 +`define APP_INT_ETH 4 +`define APP_INT_PS2 5 +`define APP_INT_RES3 19:6 + +// +// Address map +// +`define APP_ADDR_DEC_W 8 +`define APP_ADDR_SRAM `APP_ADDR_DEC_W'h00 +`define APP_ADDR_FLASH `APP_ADDR_DEC_W'h04 +`define APP_ADDR_DECP_W 4 +`define APP_ADDR_PERIP `APP_ADDR_DECP_W'h9 +`define APP_ADDR_SPI `APP_ADDR_DEC_W'h97 +`define APP_ADDR_ETH `APP_ADDR_DEC_W'h92 +`define APP_ADDR_AUDIO `APP_ADDR_DEC_W'h9d +`define APP_ADDR_UART `APP_ADDR_DEC_W'h90 +`define APP_ADDR_PS2 `APP_ADDR_DEC_W'h94 +`define APP_ADDR_RES1 `APP_ADDR_DEC_W'h9e +`define APP_ADDR_RES2 `APP_ADDR_DEC_W'h9f + +// +// Set-up GENERIC_TAP, GENERIC_MEMORY if GENERIC_FPGA was chosen +// and GENERIC_CLOCK_DIVISION if NO_CLOCK_DIVISION was not set +// +`ifdef GENERIC_FPGA + `undef FPGA_TAP + `undef FPGA_CLOCK_DIVISION + + `define GENERIC_TAP + `define GENERIC_MEMORY + `ifndef NO_CLOCK_DIVISION + `define GENERIC_CLOCK_DIVISION + `endif +`endif

backend/spartan3e_starter_kit/minsoc_defines.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: backend/spartan3e_starter_kit/board.h =================================================================== --- backend/spartan3e_starter_kit/board.h (nonexistent) +++ backend/spartan3e_starter_kit/board.h (revision 64) @@ -0,0 +1,40 @@ +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#define MC_ENABLED 0 + +#define IC_ENABLE 0 +#define IC_SIZE 8192 +#define DC_ENABLE 0 +#define DC_SIZE 8192 + + +#define IN_CLK 25000000 + + +#define STACK_SIZE 0x01000 + +#define UART_BAUD_RATE 115200 + +#define UART_BASE 0x90000000 +#define UART_IRQ 2 +#define ETH_BASE 0x92000000 +#define ETH_IRQ 4 +#define I2C_BASE 0x9D000000 +#define I2C_IRQ 3 +#define CAN_BASE 0x94000000 +#define CAN_IRQ 5 + +#define MC_BASE_ADDR 0x60000000 +#define SPI_BASE 0xa0000000 + +#define ETH_DATA_BASE 0xa8000000 /* Address for ETH_DATA */ + +#define ETH_MACADDR0 0x00 +#define ETH_MACADDR1 0x12 +#define ETH_MACADDR2 0x34 +#define ETH_MACADDR3 0x56 +#define ETH_MACADDR4 0x78 +#define ETH_MACADDR5 0x9a + +#endif

backend/spartan3e_starter_kit/board.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: backend/spartan3e_starter_kit/orp.ld =================================================================== --- backend/spartan3e_starter_kit/orp.ld (nonexistent) +++ backend/spartan3e_starter_kit/orp.ld (revision 64) @@ -0,0 +1,60 @@ +MEMORY + { + reset : ORIGIN = 0x00000000, LENGTH = 0x00000200 + vectors : ORIGIN = 0x00000200, LENGTH = 0x00001000 + ram : ORIGIN = 0x00001200, LENGTH = 0x00006E00 /*0x8000 total*/ + } + +SECTIONS +{ + .reset : + { + *(.reset) + } > reset + + + + .vectors : + { + _vec_start = .; + *(.vectors) + _vec_end = .; + } > vectors + + .text : + { + *(.text) + } > ram + + .rodata : + { + *(.rodata) + *(.rodata.*) + } > ram + + .icm : + { + _icm_start = .; + *(.icm) + _icm_end = .; + } > ram + + .data : + { + _dst_beg = .; + *(.data) + _dst_end = .; + } > ram + + .bss : + { + *(.bss) + } > ram + + .stack (NOLOAD) : + { + *(.stack) + _src_addr = .; + } > ram + +}

backend/spartan3e_starter_kit/orp.ld Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: sim/bin/minsoc_verilog_files.txt =================================================================== --- sim/bin/minsoc_verilog_files.txt (revision 63) +++ sim/bin/minsoc_verilog_files.txt (revision 64) @@ -1,3 +1,4 @@ ++incdir+../../backend +incdir+../../bench/verilog +incdir+../../bench/verilog/vpi +incdir+../../bench/verilog/sim_lib @@ -9,6 +10,7 @@ +incdir+../../rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_rtl +incdir+../../rtl/verilog/uart16550/rtl/verilog +incdir+../../rtl/verilog/ethmac/rtl/verilog +../../backend/minsoc_defines.v ../../bench/verilog/minsoc_bench_defines.v ../../bench/verilog/minsoc_bench.v ../../bench/verilog/minsoc_memory_model.v @@ -24,7 +26,6 @@ ../../rtl/verilog/minsoc_onchip_ram.v ../../rtl/verilog/minsoc_clock_manager.v ../../rtl/verilog/minsoc_onchip_ram_top.v -../../rtl/verilog/minsoc_defines.v ../../rtl/verilog/or1200/rtl/verilog/or1200_spram_512x20.v ../../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x24.v ../../rtl/verilog/or1200/rtl/verilog/or1200_du.v Index: sw/eth/Makefile =================================================================== --- sw/eth/Makefile (revision 63) +++ sw/eth/Makefile (nonexistent) @@ -1,24 +0,0 @@ -cases = eth-nocache eth-icdc -common = ../support/except.o ../support/libsupport.a -drivers = ../drivers/libdrivers.a - -all: $(cases) - -eth-nocache: eth.o ../support/reset-nocache.o $(common) $(drivers) - $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $(GCC_LIB_OPTS) -T ../support/orp.ld $? -o $@.or32 - $(OR32_TOOL_PREFIX)-objcopy -O binary $@.or32 $@.bin - ../utils/bin2hex $@.bin 1 -size_word > $@$(FLASH_MEM_HEX_FILE_SUFFIX).hex - ../utils/bin2vmem $@.bin > $@.vmem - - -eth-icdc: eth.o ../support/reset-icdc.o $(common) $(drivers) - $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $(GCC_LIB_OPTS) -T ../support/orp.ld $? -o $@.or32 - $(OR32_TOOL_PREFIX)-objcopy -O binary $@.or32 $@.bin - ../utils/bin2hex $@.bin 1 -size_word > $@$(FLASH_MEM_HEX_FILE_SUFFIX).hex - ../utils/bin2vmem $@.bin > $@.vmem - - -eth.o: eth.c - $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $? -c -o $@ - -include ../support/Makefile.inc

sw/eth/Makefile Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: sw/eth/eth.c =================================================================== --- sw/eth/eth.c (revision 63) +++ sw/eth/eth.c (revision 64) @@ -1,5 +1,5 @@ +#include "../../backend/board.h" #include "../support/support.h" -#include "../support/board.h" #include "../support/or1200.h"

/sw/eth/common.mk

sw/eth/common.mk Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: sw/uart/Makefile =================================================================== --- sw/uart/Makefile (revision 63) +++ sw/uart/Makefile (nonexistent) @@ -1,24 +0,0 @@ -cases = uart-nocache uart-icdc -common = ../support/except.o ../support/libsupport.a -drivers = ../drivers/libdrivers.a - -all: $(cases) - -uart-nocache: uart.o ../support/reset-nocache.o $(common) $(drivers) - $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $(GCC_LIB_OPTS) -T ../support/orp.ld $? -o $@.or32 - $(OR32_TOOL_PREFIX)-objcopy -O binary $@.or32 $@.bin - ../utils/bin2hex $@.bin 1 -size_word > $@$(FLASH_MEM_HEX_FILE_SUFFIX).hex - ../utils/bin2vmem $@.bin > $@.vmem - - -uart-icdc: uart.o ../support/reset-icdc.o $(common) $(drivers) - $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $(GCC_LIB_OPTS) -T ../support/orp.ld $? -o $@.or32 - $(OR32_TOOL_PREFIX)-objcopy -O binary $@.or32 $@.bin - ../utils/bin2hex $@.bin 1 -size_word > $@$(FLASH_MEM_HEX_FILE_SUFFIX).hex - ../utils/bin2vmem $@.bin > $@.vmem - - -uart.o: uart.c - $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $? -c -o $@ - -include ../support/Makefile.inc

sw/uart/Makefile Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: sw/uart/uart.c =================================================================== --- sw/uart/uart.c (revision 63) +++ sw/uart/uart.c (revision 64) @@ -1,5 +1,5 @@ +#include "../../backend/board.h" #include "../support/support.h" -#include "../support/board.h" #include "../support/or1200.h" #include "../drivers/uart.h"

/sw/uart/common.mk

sw/uart/common.mk Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: sw/support/orp.ld =================================================================== --- sw/support/orp.ld (revision 63) +++ sw/support/orp.ld (nonexistent) @@ -1,69 +0,0 @@ -/* -MEMORY - { - vectors : ORIGIN = 0x00000000, LENGTH = 0x00002000 - flash : ORIGIN = 0x04000000, LENGTH = 0x00200000 - ram : ORIGIN = 0x00002000, LENGTH = 0x001fe000 - icm : ORIGIN = 0x00800000, LENGTH = 0x00004000 - } - */ -MEMORY - { - reset : ORIGIN = 0x00000000, LENGTH = 0x00000200 - vectors : ORIGIN = 0x00000200, LENGTH = 0x00001000 - ram : ORIGIN = 0x00001200, LENGTH = 0x00006E00 /*0x8000 total*/ - } - -SECTIONS -{ - .reset : - { - *(.reset) - } > reset - - - - .vectors : - { - _vec_start = .; - *(.vectors) - _vec_end = .; - } > vectors - - .text : - { - *(.text) - } > ram - - .rodata : - { - *(.rodata) - *(.rodata.*) - } > ram - - .icm : - { - _icm_start = .; - *(.icm) - _icm_end = .; - } > ram - - .data : - { - _dst_beg = .; - *(.data) - _dst_end = .; - } > ram - - .bss : - { - *(.bss) - } > ram - - .stack (NOLOAD) : - { - *(.stack) - _src_addr = .; - } > ram - -}

sw/support/orp.ld Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: sw/support/board.h =================================================================== --- sw/support/board.h (revision 63) +++ sw/support/board.h (nonexistent) @@ -1,40 +0,0 @@ -#ifndef _BOARD_H_ -#define _BOARD_H_ - -#define MC_ENABLED 0 - -#define IC_ENABLE 0 -#define IC_SIZE 8192 -#define DC_ENABLE 0 -#define DC_SIZE 8192 - - -#define IN_CLK 25000000 - - -#define STACK_SIZE 0x01000 - -#define UART_BAUD_RATE 115200 - -#define UART_BASE 0x90000000 -#define UART_IRQ 2 -#define ETH_BASE 0x92000000 -#define ETH_IRQ 4 -#define I2C_BASE 0x9D000000 -#define I2C_IRQ 3 -#define CAN_BASE 0x94000000 -#define CAN_IRQ 5 - -#define MC_BASE_ADDR 0x60000000 -#define SPI_BASE 0xa0000000 - -#define ETH_DATA_BASE 0xa8000000 /* Address for ETH_DATA */ - -#define ETH_MACADDR0 0x00 -#define ETH_MACADDR1 0x12 -#define ETH_MACADDR2 0x34 -#define ETH_MACADDR3 0x56 -#define ETH_MACADDR4 0x78 -#define ETH_MACADDR5 0x9a - -#endif

sw/support/board.h Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: sw/support/reset.S =================================================================== --- sw/support/reset.S (revision 63) +++ sw/support/reset.S (revision 64) @@ -1,6 +1,6 @@ /* Support file for c based tests */ #include "or1200.h" -#include "board.h" +#include "../../backend/board.h" .section .stack .space STACK_SIZE

/sw/support/Makefile.inc

/sw/support/tick.c

/sw/support/Makefile

sw/support/Makefile Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: sw/support/common.mk =================================================================== --- sw/support/common.mk (nonexistent) +++ sw/support/common.mk (revision 64) @@ -0,0 +1,21 @@ +$(LIB_SUPPORT): $(SUPPORT_DIR)/support.o $(SUPPORT_DIR)/tick.o $(SUPPORT_DIR)/int.o + $(OR32_TOOL_PREFIX)-ar cru $(SUPPORT_DIR)/libsupport.a $(SUPPORT_DIR)/support.o $(SUPPORT_DIR)/tick.o $(SUPPORT_DIR)/int.o + $(OR32_TOOL_PREFIX)-ranlib $(SUPPORT_DIR)/libsupport.a + +$(SUPPORT_DIR)/support.o: $(SUPPORT_DIR)/support.c $(OR1200_HDR) $(SUPPORT_HDR) $(SUPPORT_DIR)/int.h $(UART_HDR) + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) -c -o $@ $< + +$(SUPPORT_DIR)/tick.o: $(SUPPORT_DIR)/tick.c $(OR1200_HDR) $(SUPPORT_HDR) $(SUPPORT_DIR)/tick.h + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) -c -o $@ $< + +$(SUPPORT_DIR)/int.o: $(SUPPORT_DIR)/int.c $(SUPPORT_HDR) $(OR1200_HDR) $(SUPPORT_DIR)/int.h + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) -c -o $@ $< + +$(EXCPT_HNDLR): $(SUPPORT_DIR)/except.S $(OR1200_HDR) + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) -c -o $@ $< + +$(RESET_NOCACHE): $(SUPPORT_DIR)/reset.S $(BOARD_HDR) + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) -c -DIC=0 -DDC=0 -o $@ $< + +$(RESET_ICDC): $(SUPPORT_DIR)/reset.S $(BOARD_HDR) + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) -c -DIC=1 -DDC=1 -o $@ $<

sw/support/common.mk Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: sw/drivers/Makefile =================================================================== --- sw/drivers/Makefile (revision 63) +++ sw/drivers/Makefile (nonexistent) @@ -1,22 +0,0 @@ -all: libdrivers.a - -libdrivers.a: eth.o uart.o interrupts.o can.o i2c.o - $(OR32_TOOL_PREFIX)-ar cru libdrivers.a eth.o uart.o interrupts.o can.o i2c.o - $(OR32_TOOL_PREFIX)-ranlib libdrivers.a - -eth.o: eth.c - $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $? -c -o $@ - -uart.o: uart.c - $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $? -c -o $@ - -interrupts.o: interrupts.c - $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $? -c -o $@ - -can.o: can.c - $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $? -c -o $@ - -i2c.o: i2c.c - $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $? -c -o $@ - -include ../support/Makefile.inc Index: sw/drivers/eth.c =================================================================== --- sw/drivers/eth.c (revision 63) +++ sw/drivers/eth.c (revision 64) @@ -1,4 +1,4 @@ -#include "../support/board.h" +#include "../../backend/board.h" #include "../support/support.h" #include "eth.h"

/sw/drivers/can.c

/sw/drivers/uart.c

/sw/drivers/i2c.c

/sw/drivers/common.mk

/syn/Makefile File deleted

/syn/src/eth_top.xst

/syn/src/or1200_top.xst

/syn/src/minsoc_top.xst

/syn/src/uart_top.xst

/syn/src/adbg_top.xst

/syn/src/Makefile

/syn/buildSupport/minsoc_startup_top.xst File deleted \ No newline at end of file

/syn/buildSupport/or1200_top.xst File deleted \ No newline at end of file

/syn/buildSupport/eth_top.xst File deleted \ No newline at end of file

/syn/buildSupport/minsoc_startup_top.prj File deleted \ No newline at end of file

/syn/buildSupport/uart_top.xst File deleted \ No newline at end of file

/syn/buildSupport/adbg_top.xst File deleted \ No newline at end of file

/syn/buildSupport/minsoc_top.xst File deleted \ No newline at end of file

/syn/buildSupport/minsoc_top.prj

/syn/blackboxes/OR1K_startup_generic.v File deleted

syn/blackboxes/OR1K_startup_generic.v Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property