URL
https://opencores.org/ocsvn/minsoc/minsoc/trunk
Subversion Repositories minsoc
Compare Revisions
- This comparison shows the changes necessary to convert path
/minsoc
- from Rev 146 to Rev 147
- ↔ Reverse comparison
Rev 146 → Rev 147
/branches/rc-1.0/bench/verilog/minsoc_bench.v
60,6 → 60,7
reg [12*8-1:0] hello; |
reg new_line; |
reg new_char; |
reg flush_line; |
`endif |
`ifdef ETHERNET |
reg [7:0] eth_rx_data [0:1535]; //receive buffer ETH (max packet 1536) |
310,7 → 311,7
if ( line[7:0] == "B" ) |
$display("UART interrupt working."); |
else |
$display("UART interrupt failed."); |
$display("UART interrupt failed. B was expected, %c was received.", line[7:0]); |
uart_echo = 1'b1; |
|
if ( hello == "Hello World." ) |
347,9 → 348,9
#((`CLK_PERIOD)/2) clock <= ~clock; |
end |
|
`ifdef VCD_OUTPUT |
`ifdef WAVEFORM_OUTPUT |
initial begin |
$dumpfile("../results/minsoc_wave.vcd"); |
$dumpfile("../results/minsoc_wave.lxt"); |
$dumpvars(); |
end |
`endif |
400,6 → 401,7
begin |
new_line = 1'b0; |
new_char = 1'b0; |
flush_line = 1'b0; |
end |
|
always @ (posedge clock) |
411,6 → 413,7
reg [7:0] tx_byte; |
begin |
new_char = 1'b0; |
new_line = 1'b0; |
// Wait for start bit |
while (uart_stx == 1'b1) |
@(uart_stx); |
431,16 → 434,19
//$display("* USER UART returned to idle at time %d",$time); |
end |
// display the char |
new_char = 1'b1; |
if ( uart_echo ) |
$write("%c", tx_byte); |
if ( new_line ) |
if ( flush_line ) begin |
line = ""; |
if ( tx_byte == "\n" ) |
flush_line = 1'b0; |
end |
if ( tx_byte == "\n" ) begin |
new_line = 1'b1; |
flush_line = 1'b1; |
end |
else begin |
line = { line[39*8-1:0], tx_byte}; |
new_line = 1'b0; |
new_char = 1'b1; |
end |
end |
endtask |
/branches/rc-1.0/utils/setup/minsoc-install.sh
64,6 → 64,7
testtool libncurses |
testtool flex |
testtool bison |
testtool libz |
if [ "$ENV" == "Cygwin" ] |
then |
testtool ioperm |
/branches/rc-1.0/backend/spartan3a_dsp_kit/minsoc_bench_defines.v
16,7 → 16,7
|
`define VPI_DEBUG |
|
//`define VCD_OUTPUT |
//`define WAVEFORM_OUTPUT |
|
//`define START_UP //pass firmware over spi to or1k_startup |
|
/branches/rc-1.0/backend/ug257/minsoc_bench_defines.v
6,17 → 6,17
|
`define FREQ_NUM_FOR_NS 100000000 |
|
`define FREQ 25000000 |
`define FREQ 10000000 |
`define CLK_PERIOD (`FREQ_NUM_FOR_NS/`FREQ) |
|
`define ETH_PHY_FREQ 25000000 |
`define ETH_PHY_PERIOD (`FREQ_NUM_FOR_NS/`ETH_PHY_FREQ) //40ns |
|
`define UART_BAUDRATE 115200 |
`define UART_BAUDRATE 9600 |
|
`define VPI_DEBUG |
|
//`define VCD_OUTPUT |
//`define WAVEFORM_OUTPUT |
|
//`define START_UP //pass firmware over spi to or1k_startup |
|
/branches/rc-1.0/backend/std/minsoc_bench_defines.v
16,7 → 16,7
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`define VPI_DEBUG |
|
//`define VCD_OUTPUT |
//`define WAVEFORM_OUTPUT |
|
//`define START_UP //pass firmware over spi to or1k_startup |
|
/branches/rc-1.0/backend/altera_3c25_board/minsoc_bench_defines.v
16,7 → 16,7
|
`define VPI_DEBUG |
|
//`define VCD_OUTPUT |
//`define WAVEFORM_OUTPUT |
|
//`define START_UP //pass firmware over spi to or1k_startup |
|
/branches/rc-1.0/backend/spartan3e_starter_kit/minsoc_bench_defines.v
16,7 → 16,7
|
`define VPI_DEBUG |
|
//`define VCD_OUTPUT |
//`define WAVEFORM_OUTPUT |
|
//`define START_UP //pass firmware over spi to or1k_startup |
|
/branches/rc-1.0/sim/run/run_bench
10,4 → 10,4
# regardless of the number of hex bytes per line. |
FIRMWARE_SIZE_IN_BYTES="$(wc -w <"$1")" |
|
vvp -M ../../bench/verilog/vpi/ -mjp-io-vpi minsoc_bench +file_name="$1" +firmware_size="$FIRMWARE_SIZE_IN_BYTES" |
vvp -M ../../bench/verilog/vpi/ -mjp-io-vpi minsoc_bench +file_name="$1" +firmware_size="$FIRMWARE_SIZE_IN_BYTES" -lxt2 |
/branches/rc-1.0/sw/eth/eth.c
38,7 → 38,7
|
/* We can't use printf because in this simple example |
we don't link C library. */ |
uart_print_str("Hello World.\n\r"); |
uart_print_str("Hello World.\n"); |
|
eth_tx_data[0] = 0xFF; |
eth_tx_data[1] = 0x2B; |
/branches/rc-1.0/sw/uart/uart.c
14,7 → 14,7
|
/* We can't use printf because in this simple example |
we don't link C library. */ |
uart_print_str("Hello World.\n\r"); |
uart_print_str("Hello World.\n"); |
|
report(0xdeaddead); |
or32_exit(0); |
/branches/rc-1.0/sw/drivers/uart.c
57,10 → 57,6
|
WAIT_FOR_THRE; |
REG8(UART_BASE + UART_TX) = c; |
if(c == '\n') { |
WAIT_FOR_THRE; |
REG8(UART_BASE + UART_TX) = '\r'; |
} |
WAIT_FOR_XMITR; |
} |
|