URL
https://opencores.org/ocsvn/minsoc/minsoc/trunk
Subversion Repositories minsoc
Compare Revisions
- This comparison shows the changes necessary to convert path
/minsoc
- from Rev 95 to Rev 96
- ↔ Reverse comparison
Rev 95 → Rev 96
/trunk/backend/altera_3c25_board/configure
17,7 → 17,7
SYNSUPPORT_DIR=$SYN_DIR/buildSupport |
MAKEFILE_DIR=$SYN_DIR/altera |
|
SYN_FILES=(adbg_top.prj jtag_top.prj or1200_top.prj uart_top.prj minsoc_top.prj) |
SYN_FILES=(adbg_top.prj jtag_top.prj or1200_top.prj uart_top.prj minsoc_top.prj altera_virtual_jtag.prj) |
MAKEFILE=Makefile |
|
FIND_PART='DEVICE_PART' |
/trunk/prj/scripts/altprj.sh
0,0 → 1,54
#!/bin/bash |
|
#system workings |
MINSOC_DIR=`pwd`/.. |
|
PROJECT=$1 |
OUTPUT=$2 |
|
if [ ! -f $PROJECT ] |
then |
echo "Unexistent project file." |
exit 1 |
fi |
|
if [ -z "$OUTPUT" ] |
then |
echo "Second argument should be the destintion file for the file and directory inclusions." |
exit 1 |
fi |
echo -n "" > $OUTPUT |
|
source $PROJECT |
|
for dir in "${PROJECT_DIR[@]}" |
do |
echo "set_global_assignment -name SEARCH_PATH $MINSOC_DIR/$dir" >> $OUTPUT |
done |
|
for file in "${PROJECT_SRC[@]}" |
do |
FOUND=0 |
|
for dir in "${PROJECT_DIR[@]}" |
do |
if [ -f $MINSOC_DIR/$dir/$file ] |
then |
is_vhdl=`ls $MINSOC_DIR/$dir/$file | grep vhd` |
if [ -z $is_vhdl ] |
then |
echo "set_global_assignment -name VERILOG_FILE $MINSOC_DIR/$dir/$file" >> $OUTPUT |
else |
echo "set_global_assignment -name VHDL_FILE $MINSOC_DIR/$dir/$file" >> $OUTPUT |
fi |
FOUND=1 |
break |
fi |
done |
|
if [ $FOUND != 1 ] |
then |
echo "FILE NOT FOUND" |
exit 1 |
fi |
done |
trunk/prj/scripts/altprj.sh
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/prj/src/altera_virtual_jtag.prj
===================================================================
--- trunk/prj/src/altera_virtual_jtag.prj (nonexistent)
+++ trunk/prj/src/altera_virtual_jtag.prj (revision 96)
@@ -0,0 +1,2 @@
+PROJECT_DIR=rtl/verilog/adv_debug_sys/Hardware/altera_virtual_jtag/rtl/vhdl/
+PROJECT_SRC=altera_virtual_jtag.vhd
Index: trunk/prj/altera/altera_virtual_jtag.prj
===================================================================
--- trunk/prj/altera/altera_virtual_jtag.prj (nonexistent)
+++ trunk/prj/altera/altera_virtual_jtag.prj (revision 96)
@@ -0,0 +1,2 @@
+set_global_assignment -name SEARCH_PATH ../../rtl/verilog/adv_debug_sys/Hardware/altera_virtual_jtag/rtl/vhdl/
+set_global_assignment -name VHDL_FILE ../../rtl/verilog/adv_debug_sys/Hardware/altera_virtual_jtag/rtl/vhdl/altera_virtual_jtag.vhd
Index: trunk/prj/Makefile
===================================================================
--- trunk/prj/Makefile (revision 95)
+++ trunk/prj/Makefile (revision 96)
@@ -1,4 +1,4 @@
-PROJECTS = minsoc_bench.prj minsoc_top.prj or1200_top.prj adbg_top.prj jtag_top.prj uart_top.prj ethmac.prj
+PROJECTS = minsoc_bench.prj minsoc_top.prj or1200_top.prj adbg_top.prj jtag_top.prj uart_top.prj ethmac.prj altera_virtual_jtag.prj
SRC_DIR = src
SCRIPTS_DIR = scripts