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URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

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Rev 18 → Rev 19

/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
340,7 → 340,47
);
end component last_stage;
--------------------------------------------------------------------
-- counter_sync
--------------------------------------------------------------------
-- counter with synchronous count enable. It generates an
-- overflow when max_value is reached
--
component counter_sync is
generic(
max_value : integer := 1024 -- maximum value (constraints the nr bits for counter)
);
port(
reset_value : in integer; -- value the counter counts to
core_clk : in std_logic; -- clock input
ce : in std_logic; -- count enable
reset : in std_logic; -- reset input
overflow : out std_logic -- gets high when counter reaches reset_value
);
end component counter_sync;
--------------------------------------------------------------------
-- stepping_logic
--------------------------------------------------------------------
-- stepping logic for the pipeline, generates the start pulses for the
-- first stage and keeps track of when the last stages are done
--
component stepping_logic is
generic(
n : integer := 1536; -- max nr of steps required to complete a multiplication
t : integer := 192 -- total nr of steps in the pipeline
);
port(
core_clk : in std_logic; -- clock input
start : in std_logic; -- start signal for pipeline (one multiplication)
reset : in std_logic; -- reset signal
t_sel : in integer range 0 to t; -- nr of stages in the pipeline piece
n_sel : in integer range 0 to n; -- nr of steps(bits in operands) required for a complete multiplication
start_first_stage : out std_logic; -- start pulse output for first stage
stepping_done : out std_logic -- done signal
);
end component stepping_logic;
 
component autorun_cntrl is
port (
clk : in std_logic;
356,19 → 396,6
);
end component autorun_cntrl;
component counter_sync is
generic(
max_value : integer := 1024
);
port(
reset_value : in integer;
core_clk : in std_logic;
ce : in std_logic;
reset : in std_logic;
overflow : out std_logic
);
end component counter_sync;
component fifo_primitive is
port (
clk : in std_logic;
540,22 → 567,6
);
end component operands_sp;
component stepping_logic is
generic(
n : integer := 1536; -- max nr of steps required to complete a multiplication
t : integer := 192 -- total nr of steps in the pipeline
);
port(
core_clk : in std_logic;
start : in std_logic;
reset : in std_logic;
t_sel : in integer range 0 to t; -- nr of stages in the pipeline piece
n_sel : in integer range 0 to n; -- nr of steps required for a complete multiplication
start_first_stage : out std_logic;
stepping_done : out std_logic
);
end component stepping_logic;
component systolic_pipeline is
generic(
n : integer := 1536; -- width of the operands (# bits)
/mod_sim_exp/trunk/rtl/vhdl/core/stepping_logic.vhd
6,7 → 6,8
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- stepping logic for the pipelined montgomery multiplier ----
---- stepping logic to control the pipeline for one ----
---- montgommery multiplication ----
---- ----
---- Dependencies: ----
---- - d_flip_flop ----
52,70 → 53,77
use mod_sim_exp.mod_sim_exp_pkg.all;
 
 
-- stepping logic for the pipeline, generates the start pulses for the
-- first stage and keeps track of when the last stages are done
entity stepping_logic is
generic(
n : integer := 1536; -- max nr of steps required to complete a multiplication
t : integer := 192 -- total nr of steps in the pipeline
n : integer := 1536; -- max nr of steps required to complete a multiplication
t : integer := 192 -- total nr of steps in the pipeline
);
port(
core_clk : in std_logic;
start : in std_logic;
reset : in std_logic;
core_clk : in std_logic; -- clock input
start : in std_logic; -- start signal for pipeline (one multiplication)
reset : in std_logic; -- reset signal
t_sel : in integer range 0 to t; -- nr of stages in the pipeline piece
n_sel : in integer range 0 to n; -- nr of steps required for a complete multiplication
start_first_stage : out std_logic;
stepping_done : out std_logic
n_sel : in integer range 0 to n; -- nr of steps(bits in operands) required for a complete multiplication
start_first_stage : out std_logic; -- start pulse output for first stage
stepping_done : out std_logic -- done signal
);
end stepping_logic;
 
 
architecture Behavioral of stepping_logic is
signal laststeps_in_i : std_logic := '0';
signal laststeps_out_i : std_logic := '0';
signal start_stop_in_i : std_logic := '0';
signal start_stop_out_i : std_logic := '0';
signal steps_in_i : std_logic := '0';
signal steps_out_i : std_logic := '0';
signal substeps_in_i : std_logic := '0';
signal substeps_out_i : std_logic := '0';
signal done_reg_in_i : std_logic := '0';
signal done_reg_out_i : std_logic := '0';
signal start_first_stage_i : std_logic := '0';
signal start_i : std_logic := '0';
 
-- signals for the first stage control, pulses and counters
signal first_stage_done : std_logic; -- indicates the first stage is done running for this multiplication
signal first_stage_active : std_logic; -- indicates the first stage is active
signal first_stage_active_d : std_logic; -- delayed version of first_stage_active
signal start_first_stage_i : std_logic; -- internal version of start_first_stage output
 
-- signals for the last stages control and counter
signal last_stages_done : std_logic; -- indicates the last stages are done running for this multiplication
signal last_stages_active : std_logic; -- indicates the last stages are active
signal last_stages_active_d : std_logic; -- delayed version of last_stages_active
 
begin
start_i <= start;
 
-- map outputs
start_first_stage <= start_first_stage_i;
stepping_done <= laststeps_out_i;
stepping_done <= last_stages_done;
-- internal signals
start_stop_in_i <= start_i or (start_stop_out_i and not steps_out_i);
substeps_in_i <= start_stop_in_i;
steps_in_i <= substeps_out_i;
done_reg_in_i <= steps_out_i or (done_reg_out_i and not laststeps_out_i);
laststeps_in_i <= done_reg_in_i;
start_first_stage_i <= start_i or steps_in_i;
--start_first_stage_i <= steps_in_i;
--------------------
-- first_stage_active signal gets active from a start pulse
-- inactive from first_stage_done pulse
first_stage_active <= start or (first_stage_active_d and not first_stage_done);
done_reg : d_flip_flop
-- done signal gets active from a first_stage_done pulse
-- inactive from last_stages_done pulse
last_stages_active <= first_stage_done or (last_stages_active_d and not last_stages_done);
-- map start_first_stage_i to output, but also use the initial start pulse
start_first_stage <= start or start_first_stage_i;
last_stages_active_delay : d_flip_flop
port map(
core_clk => core_clk,
reset => reset,
din => done_reg_in_i,
dout => done_reg_out_i
din => last_stages_active,
dout => last_stages_active_d
);
 
start_stop_reg : d_flip_flop
first_stage_active_delay : d_flip_flop
port map(
core_clk => core_clk,
reset => reset,
din => start_stop_in_i,
dout => start_stop_out_i
din => first_stage_active,
dout => first_stage_active_d
);
 
-- for counting the last steps
-- the counters
----------------
-- for counting the last steps (waiting for the other stages to stop)
-- counter for keeping track of how many stages are done
laststeps_counter : counter_sync
generic map(
max_value => t
123,12 → 131,13
port map(
reset_value => t_sel,
core_clk => core_clk,
ce => laststeps_in_i,
ce => last_stages_active,
reset => reset,
overflow => laststeps_out_i
overflow => last_stages_done
);
 
-- counter for keeping track of the steps
-- counter for keeping track of how many times the first stage is started
-- counts bits in operand x till operand width then generates pulse on first_stage_done
steps_counter : counter_sync
generic map(
max_value => n
136,12 → 145,12
port map(
reset_value => (n_sel),
core_clk => core_clk,
ce => steps_in_i,
ce => start_first_stage_i,
reset => reset,
overflow => steps_out_i
overflow => first_stage_done
);
 
-- makes sure we don't start too early with a new step
-- the output (overflow) of this counter starts the first stage every 2 clock cycles
substeps_counter : counter_sync
generic map(
max_value => 2
149,9 → 158,9
port map(
reset_value => 2,
core_clk => core_clk,
ce => substeps_in_i,
ce => first_stage_active,
reset => reset,
overflow => substeps_out_i
overflow => start_first_stage_i
);
 
end Behavioral;
/mod_sim_exp/trunk/rtl/vhdl/core/counter_sync.vhd
47,48 → 47,48
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
 
-- counter with synchronous count enable. It generates an
-- overflow when max_value is reached
entity counter_sync is
generic(
max_value : integer := 1024
max_value : integer := 1024 -- maximum value (constraints the nr bits for counter)
);
port(
reset_value : in integer;
core_clk : in std_logic;
ce : in std_logic;
reset : in std_logic;
overflow : out std_logic
reset_value : in integer; -- value the counter counts to
core_clk : in std_logic; -- clock input
ce : in std_logic; -- count enable
reset : in std_logic; -- reset input
overflow : out std_logic -- gets high when counter reaches reset_value
);
end counter_sync;
 
 
architecture Behavioral of counter_sync is
signal overflow_i : std_logic := '0';
begin
overflow <= overflow_i;
COUNT_PROC: process(core_clk, ce, reset)
variable steps_counter : integer range 0 to max_value-1 := 0;
-- counter process with asynchronous active high reset
count_proc: process(core_clk, ce, reset)
variable steps_counter : integer range 0 to max_value-1;
begin
if reset = '1' then -- reset counter
steps_counter := 0;
overflow_i <= '0';
overflow <= '0';
elsif rising_edge(core_clk) then
if ce = '1' then -- count
-- counter is enabled, count till reset_value
if ce = '1' then
if steps_counter = (reset_value-1) then -- generate overflow and reset counter
steps_counter := 0;
overflow_i <= '1';
overflow <= '1';
else -- just count
steps_counter := steps_counter + 1;
overflow_i <= '0';
overflow <= '0';
end if;
else
overflow_i <= '0';
--counter disabled, halt counter
overflow <= '0';
steps_counter := steps_counter;
end if;
end if;
end process;
end Behavioral;
end Behavioral;

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