URL
https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk
Subversion Repositories mod_sim_exp
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 34 to Rev 33
- ↔ Reverse comparison
Rev 34 → Rev 33
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
133,10 → 133,7
); |
|
-- Block ram memory for storing the operands and the modulus |
the_memory : operand_mem |
generic map( |
n => n |
) |
the_memory : operand_mem |
port map( |
data_in => data_in, |
data_out => data_out, |
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
611,9 → 611,9
|
-- operand interface (multiplier side) |
op_sel : in std_logic_vector(1 downto 0); |
xy_out : out std_logic_vector((n-1) downto 0); |
m : out std_logic_vector((n-1) downto 0); |
result_in : in std_logic_vector((n-1) downto 0); |
xy_out : out std_logic_vector(1535 downto 0); |
m : out std_logic_vector(1535 downto 0); |
result_in : in std_logic_vector(1535 downto 0); |
-- control signals |
load_op : in std_logic; |
load_m : in std_logic; |
/mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd
70,9 → 70,9
|
-- operand interface (multiplier side) |
op_sel : in std_logic_vector(1 downto 0); |
xy_out : out std_logic_vector((n-1) downto 0); |
m : out std_logic_vector((n-1) downto 0); |
result_in : in std_logic_vector((n-1) downto 0); |
xy_out : out std_logic_vector(1535 downto 0); |
m : out std_logic_vector(1535 downto 0); |
result_in : in std_logic_vector(1535 downto 0); |
-- control signals |
load_op : in std_logic; |
load_m : in std_logic; |
91,9 → 91,7
signal operand_in_sel_i : std_logic_vector(1 downto 0); |
signal collision_i : std_logic; |
|
signal xy_out_i : std_logic_vector(1535 downto 0); |
signal m_i : std_logic_vector(1535 downto 0); |
signal result_in_i : std_logic_vector(1535 downto 0); |
signal xy_op_i : std_logic_vector(1535 downto 0); |
|
signal m_addr_i : std_logic_vector(5 downto 0); |
signal write_m_i : std_logic; |
102,9 → 100,7
begin |
|
-- map outputs |
xy_out <= xy_out_i((n-1) downto 0); |
m <= m_i((n-1) downto 0); |
result_in_i((n-1) downto 0) <= result_in; |
xy_out <= xy_op_i; |
collision <= collision_i; |
|
-- map inputs |
125,11 → 121,11
operand_in_sel => operand_in_sel_i, |
result_out => data_out, |
write_operand => load_op, |
operand_out => xy_out_i, |
operand_out => xy_op_i, |
operand_out_sel => op_sel, |
result_dest_op => result_dest_op, |
write_result => load_result, |
result_in => result_in_i |
result_in => result_in |
); |
|
-- modulus storage |
139,7 → 135,7
modulus_addr => m_addr_i, |
write_modulus => write_m_i, |
modulus_in => m_data_i, |
modulus_out => m_i |
modulus_out => m |
); |
|
end Behavioral; |