URL
https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk
Subversion Repositories mod_sim_exp
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- This comparison shows the changes necessary to convert path
/
- from Rev 57 to Rev 56
- ↔ Reverse comparison
Rev 57 → Rev 56
/mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/std_functions.vhd
File deleted
\ No newline at end of file
/mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/mod_sim_exp_pkg.vhd
353,30 → 353,6
); |
end component fifo_primitive; |
|
-------------------------------------------------------------------- |
-- fifo_generic |
-------------------------------------------------------------------- |
-- a behavorial implementation of a fifo |
-- |
component fifo_generic is |
generic ( |
depth : integer := 32 |
); |
port ( |
clk : in std_logic; -- clock input |
din : in std_logic_vector (31 downto 0); -- 32 bit input data for push |
dout : out std_logic_vector (31 downto 0); -- 32 bit output data for pop |
empty : out std_logic; -- empty flag, 1 when FIFO is empty |
full : out std_logic; -- full flag, 1 when FIFO is full |
push : in std_logic; |
pop : in std_logic; |
reset : in std_logic; |
nopop : out std_logic; |
nopush : out std_logic |
); |
end component fifo_generic; |
|
|
component modulus_ram is |
port( |
clk : in std_logic; |
/mod_sim_exp/branches/newRAMstyle/rtl/vhdl/core/mod_sim_exp_core.vhd
156,10 → 156,7
result_dest_op <= dest_op_single when exp_m = '0' else "11"; -- in autorun mode we always store the result in operand3 |
|
-- A fifo for auto-run operand selection |
the_exponent_fifo : fifo_generic |
generic map( |
depth => 8 -- depth needs to be at least C_NR_EXP_BITS_MAX/16 |
) |
the_exponent_fifo : fifo_primitive |
port map( |
clk => clk, |
din => fifo_din, |