URL
https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk
Subversion Repositories mod_sim_exp
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- This comparison shows the changes necessary to convert path
/mod_sim_exp/branches
- from Rev 58 to Rev 68
- ↔ Reverse comparison
Rev 58 → Rev 68
/newRAMstyle/bench/vhdl/multiplier_tb.vhd
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/newRAMstyle/bench/vhdl/mod_sim_exp_core_tb.vhd
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/newRAMstyle/rtl/vhdl/core/fifo_primitive.vhd
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/newRAMstyle/rtl/vhdl/core/mod_sim_exp_core.vhd
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/newRAMstyle/rtl/vhdl/core/counter_sync.vhd
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/newRAMstyle/rtl/vhdl/core/operand_dp.vhd
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/newRAMstyle/rtl/vhdl/core/operands_sp.vhd
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/newRAMstyle/rtl/vhdl/core/d_flip_flop.vhd
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/newRAMstyle/rtl/vhdl/core/sys_last_cell_logic.vhd
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/newRAMstyle/rtl/vhdl/core/fifo_generic.vhd
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/newRAMstyle/rtl/vhdl/core/std_functions.vhd
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/newRAMstyle/rtl/vhdl/core/mont_multiplier.vhd
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/newRAMstyle/rtl/vhdl/core/operand_mem.vhd
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/newRAMstyle/rtl/vhdl/core/modulus_ram.vhd
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/newRAMstyle/rtl/vhdl/core/operand_ram.vhd
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/newRAMstyle/rtl/vhdl/core/adder_block.vhd
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/newRAMstyle/rtl/vhdl/core/cell_1b_mux.vhd
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/newRAMstyle/rtl/vhdl/core/autorun_cntrl.vhd
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/newRAMstyle/rtl/vhdl/core/cell_1b_adder.vhd
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/newRAMstyle/rtl/vhdl/core/sys_stage.vhd
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/newRAMstyle/rtl/vhdl/core/sys_first_cell_logic.vhd
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/newRAMstyle/rtl/vhdl/core/register_n.vhd
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/newRAMstyle/rtl/vhdl/core/cell_1b.vhd
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/newRAMstyle/rtl/vhdl/core/mont_ctrl.vhd
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/newRAMstyle/rtl/vhdl/core/x_shift_reg.vhd
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/newRAMstyle/rtl/vhdl/core/sys_pipeline.vhd
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/newRAMstyle/rtl/vhdl/core/mod_sim_exp_pkg.vhd
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/newRAMstyle/rtl/vhdl/core/stepping_logic.vhd
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/newRAMstyle/rtl/vhdl/core/register_1b.vhd
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/newRAMstyle/rtl/vhdl/core/standard_cell_block.vhd
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/newRAMstyle/rtl/vhdl/interface/plb/user_logic.vhd
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/newRAMstyle/doc/src/plb_interface.tex
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/newRAMstyle/doc/src/Speedtest.xlsx
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newRAMstyle/doc/src/Speedtest.xlsx
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Index: newRAMstyle/doc/src/acknowl.tex
===================================================================
--- newRAMstyle/doc/src/acknowl.tex (revision 58)
+++ newRAMstyle/doc/src/acknowl.tex (nonexistent)
@@ -1,30 +0,0 @@
-\chapter*{Acknowledgments}
-\addcontentsline{toc}{chapter}{Acknowledgments}
-This project is maintained by the DraMCo research group\footnote{\url{http://www.dramco.be/}} of KAHO Sint-Lieven\footnote{\url{http://www.kahosl.be/}}, part of the KU Leuven association\footnote{\url{http://associatie.kuleuven.be/}}.
-The base design for this IP core is written by Geoffrey Ottoy, member of the DraMCo research group. Further adjustments have been made by Jonas De Craene
-
-%\addtocontents{toc}{Document Revision History}
-
-\chapter*{Document Revision History}
-\addcontentsline{toc}{chapter}{Document Revision History}
-
-\section*{History}
-\begin{tabular}{|l|c|l|p{10cm}|}
- \hline
- \rowcolor{Gray}
- \textbf{Revision} & \textbf{Date} & \textbf{By} & \textbf{Description} \\
- \hline
- 0 & November 2012 & JDC & First draft of this specification\\
- \hline
- 1.0 & November 2012 & JDC & Added sections ``Acknowledgement'' and ``Performance and resource usage'' as well as different fonts for \textit{variables} and \verb|signal_names|\\
- \hline
- 1.1 & November 2012 & GO & Added this ``Document Revision History''. Made several small changes in layout and formulation.\\
- \hline
-\end{tabular}%
-
-\section*{Author info}
-
-\begin{itemize}
-\item[GO:] Geoffrey Ottoy\\DraMCo research group\\\url{geoffrey.ottoy@kahosl.be}
-\item[JDC:] Jonas De Craene\\KAHO Sint-Lieven\\\url{JonasDC@opencores.org}
-\end{itemize}
\ No newline at end of file
Index: newRAMstyle/doc/src/pictures/pipeline_operation.pdf
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