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/Release_1.0/bench/vhdl/mod_sim_exp_core_tb.vhd
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----------------------------------------------------------------------
---- mod_sim_exp_core_tb ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- testbench for the modular simultaneous exponentiation ----
---- core. Performs some exponentiations to verify the design ----
---- Takes input parameters from sim_input.txt en writes ----
---- result and output to sim_output.txt ----
---- ----
---- Dependencies: ----
---- - multiplier_core ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
 
library std;
use std.textio.all;
 
library ieee;
use ieee.std_logic_textio.all;
 
library mod_sim_exp;
use mod_sim_exp.mod_sim_exp_pkg.all;
 
entity mod_sim_exp_core_tb is
end mod_sim_exp_core_tb;
 
architecture test of mod_sim_exp_core_tb is
constant nr_stages : integer := 96;
constant clk_period : time := 10 ns;
signal clk : std_logic := '0';
signal reset : std_logic := '1';
file input : text open read_mode is "src/sim_input.txt";
file output : text open write_mode is "out/sim_output.txt";
------------------------------------------------------------------
-- Signals for multiplier core memory space
------------------------------------------------------------------
signal core_rw_address : std_logic_vector (8 downto 0);
signal core_data_in : std_logic_vector(31 downto 0);
signal core_fifo_din : std_logic_vector(31 downto 0);
signal core_data_out : std_logic_vector(31 downto 0);
signal core_write_enable : std_logic;
signal core_fifo_push : std_logic;
------------------------------------------------------------------
-- Signals for multiplier core control
------------------------------------------------------------------
signal core_start : std_logic;
signal core_run_auto : std_logic;
signal core_p_sel : std_logic_vector(1 downto 0);
signal core_dest_op_single : std_logic_vector(1 downto 0);
signal core_x_sel_single : std_logic_vector(1 downto 0);
signal core_y_sel_single : std_logic_vector(1 downto 0);
signal calc_time : std_logic;
------------------------------------------------------------------
-- Signals for multiplier core interrupt
------------------------------------------------------------------
signal core_fifo_full : std_logic;
signal core_fifo_nopush : std_logic;
signal core_ready : std_logic;
signal core_mem_collision : std_logic;
 
begin
 
------------------------------------------
-- Generate clk
------------------------------------------
clk_process : process
begin
while (true) loop
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end loop;
end process;
 
------------------------------------------
-- Stimulus Process
------------------------------------------
stim_proc : process
procedure waitclk(n : natural := 1) is
begin
for i in 1 to n loop
wait until rising_edge(clk);
end loop;
end waitclk;
procedure loadOp(constant op_sel : std_logic_vector(2 downto 0);
variable op_data : std_logic_vector(2047 downto 0)) is
begin
wait until rising_edge(clk);
core_rw_address <= op_sel & "000000";
wait until rising_edge(clk);
core_write_enable <= '1';
for i in 0 to (1536/32)-1 loop
assert (core_mem_collision='0')
report "collision detected while writing operand!!" severity failure;
case (core_p_sel) is
when "11" =>
core_data_in <= op_data(((i+1)*32)-1 downto (i*32));
when "01" =>
if (i < 16) then core_data_in <= op_data(((i+1)*32)-1 downto (i*32));
else core_data_in <= x"00000000"; end if;
when "10" =>
if (i >= 16) then core_data_in <= op_data(((i-15)*32)-1 downto ((i-16)*32));
else core_data_in <= x"00000000"; end if;
when others =>
core_data_in <= x"00000000";
end case;
wait until rising_edge(clk);
core_rw_address <= core_rw_address+"000000001";
end loop;
core_write_enable <= '0';
wait until rising_edge(clk);
end loadOp;
procedure readOp(constant op_sel : std_logic_vector(2 downto 0);
variable op_data : out std_logic_vector(2047 downto 0);
variable op_width : integer) is
begin
wait until rising_edge(clk);
core_dest_op_single <= op_sel(1 downto 0);
if (core_p_sel = "10") then
core_rw_address <= op_sel & "010000";
else
core_rw_address <= op_sel & "000000";
end if;
waitclk(2);
for i in 0 to (op_width/32)-2 loop
op_data(((i+1)*32)-1 downto (i*32)) := core_data_out;
core_rw_address <= core_rw_address+"000000001";
waitclk(2);
end loop;
op_data(op_width-1 downto op_width-32) := core_data_out;
wait until rising_edge(clk);
end readOp;
 
function ToString(constant Timeval : time) return string is
variable StrPtr : line;
begin
write(StrPtr,Timeval);
return StrPtr.all;
end ToString;
 
-- variables to read file
variable L : line;
variable Lw : line;
variable base_width : integer;
variable exponent_width : integer;
variable g0 : std_logic_vector(2047 downto 0) := (others=>'0');
variable g1 : std_logic_vector(2047 downto 0) := (others=>'0');
variable e0 : std_logic_vector(2047 downto 0) := (others=>'0');
variable e1 : std_logic_vector(2047 downto 0) := (others=>'0');
variable m : std_logic_vector(2047 downto 0) := (others=>'0');
variable R2 : std_logic_vector(2047 downto 0) := (others=>'0');
variable R : std_logic_vector(2047 downto 0) := (others=>'0');
variable gt0 : std_logic_vector(2047 downto 0) := (others=>'0');
variable gt1 : std_logic_vector(2047 downto 0) := (others=>'0');
variable gt01 : std_logic_vector(2047 downto 0) := (others=>'0');
variable one : std_logic_vector(2047 downto 0) := std_logic_vector(conv_unsigned(1, 2048));
variable result : std_logic_vector(2047 downto 0) := (others=>'0');
variable data_read : std_logic_vector(2047 downto 0) := (others=>'0');
variable good_value : boolean;
variable param_count : integer := 0;
-- constants for operand selection
constant op_modulus : std_logic_vector(2 downto 0) := "100";
constant op_0 : std_logic_vector(2 downto 0) := "000";
constant op_1 : std_logic_vector(2 downto 0) := "001";
constant op_2 : std_logic_vector(2 downto 0) := "010";
constant op_3 : std_logic_vector(2 downto 0) := "011";
variable timer : time;
begin
-- initialisation
-- memory
core_write_enable <= '0';
core_data_in <= x"00000000";
core_rw_address <= "000000000";
-- fifo
core_fifo_din <= x"00000000";
core_fifo_push <= '0';
-- control
core_start <= '0';
core_run_auto <= '0';
core_x_sel_single <= "00";
core_y_sel_single <= "01";
core_dest_op_single <= "01";
core_p_sel <= "11";
-- Generate active high reset signal
reset <= '1';
waitclk(100);
reset <= '0';
waitclk(100);
while not endfile(input) loop
readline(input, L); -- read next line
next when L(1)='-'; -- skip comment lines
-- read input values
case param_count is
when 0 => -- base width
read(L, base_width, good_value);
assert good_value report "Can not read base width" severity failure;
assert false report "Simulating exponentiation" severity note;
write(Lw, string'("----------------------------------------------"));
writeline(output, Lw);
write(Lw, string'("-- EXPONENTIATION --"));
writeline(output, Lw);
write(Lw, string'("----------------------------------------------"));
writeline(output, Lw);
write(Lw, string'("----- Variables used:"));
writeline(output, Lw);
write(Lw, string'("base width: "));
write(Lw, base_width);
writeline(output, Lw);
case (base_width) is
when 1536 => when 1024 => when 512 =>
when others =>
write(Lw, string'("=> incompatible base width!!!")); writeline(output, Lw);
assert false report "incompatible base width!!!" severity failure;
end case;
when 1 => -- exponent width
read(L, exponent_width, good_value);
assert good_value report "Can not read exponent width" severity failure;
write(Lw, string'("exponent width: "));
write(Lw, exponent_width);
writeline(output, Lw);
when 2 => -- g0
hread(L, g0(base_width-1 downto 0), good_value);
assert good_value report "Can not read g0! (wrong lenght?)" severity failure;
write(Lw, string'("g0: "));
hwrite(Lw, g0(base_width-1 downto 0));
writeline(output, Lw);
when 3 => -- g1
hread(L, g1(base_width-1 downto 0), good_value);
assert good_value report "Can not read g1! (wrong lenght?)" severity failure;
write(Lw, string'("g1: "));
hwrite(Lw, g1(base_width-1 downto 0));
writeline(output, Lw);
when 4 => -- e0
hread(L, e0(exponent_width-1 downto 0), good_value);
assert good_value report "Can not read e0! (wrong lenght?)" severity failure;
write(Lw, string'("e0: "));
hwrite(Lw, e0(exponent_width-1 downto 0));
writeline(output, Lw);
when 5 => -- e1
hread(L, e1(exponent_width-1 downto 0), good_value);
assert good_value report "Can not read e1! (wrong lenght?)" severity failure;
write(Lw, string'("e1: "));
hwrite(Lw, e1(exponent_width-1 downto 0));
writeline(output, Lw);
when 6 => -- m
hread(L, m(base_width-1 downto 0), good_value);
assert good_value report "Can not read m! (wrong lenght?)" severity failure;
write(Lw, string'("m: "));
hwrite(Lw, m(base_width-1 downto 0));
writeline(output, Lw);
when 7 => -- R^2
hread(L, R2(base_width-1 downto 0), good_value);
assert good_value report "Can not read R2! (wrong lenght?)" severity failure;
write(Lw, string'("R2: "));
hwrite(Lw, R2(base_width-1 downto 0));
writeline(output, Lw);
when 8 => -- R
hread(L, R(base_width-1 downto 0), good_value);
assert good_value report "Can not read R! (wrong lenght?)" severity failure;
when 9 => -- gt0
hread(L, gt0(base_width-1 downto 0), good_value);
assert good_value report "Can not read gt0! (wrong lenght?)" severity failure;
when 10 => -- gt1
hread(L, gt1(base_width-1 downto 0), good_value);
assert good_value report "Can not read gt1! (wrong lenght?)" severity failure;
when 11 => -- gt01
hread(L, gt01(base_width-1 downto 0), good_value);
assert good_value report "Can not read gt01! (wrong lenght?)" severity failure;
-- select pipeline for all computations
----------------------------------------
writeline(output, Lw);
write(Lw, string'("----- Selecting pipeline: "));
writeline(output, Lw);
case (base_width) is
when 1536 => core_p_sel <= "11"; write(Lw, string'(" Full pipeline selected"));
when 1024 => core_p_sel <= "10"; write(Lw, string'(" Upper pipeline selected"));
when 512 => core_p_sel <= "01"; write(Lw, string'(" Lower pipeline selected"));
when others =>
write(Lw, string'(" Invallid bitwidth for design"));
assert false report "impossible basewidth!" severity failure;
end case;
writeline(output, Lw);
writeline(output, Lw);
write(Lw, string'("----- Writing operands:"));
writeline(output, Lw);
-- load the modulus
--------------------
loadOp(op_modulus, m); -- visual check needed
write(Lw, string'(" m written"));
writeline(output, Lw);
-- load g0
-----------
loadOp(op_0, g0);
-- verify
readOp(op_0, data_read, base_width);
if (g0(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
write(Lw, string'(" g0 written in operand_0")); writeline(output, Lw);
else
write(Lw, string'(" failed to write g0 to operand_0!")); writeline(output, Lw);
assert false report "Load g0 to op0 data verify failed!!" severity failure;
end if;
-- load g1
-----------
loadOp(op_1, g1);
-- verify
readOp(op_1, data_read, base_width);
if (g1(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
write(Lw, string'(" g1 written in operand_1")); writeline(output, Lw);
else
write(Lw, string'(" failed to write g1 to operand_1!")); writeline(output, Lw);
assert false report "Load g1 to op1 data verify failed!!" severity failure;
end if;
-- load R2
-----------
loadOp(op_2, R2);
-- verify
readOp(op_2, data_read, base_width);
if (R2(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
write(Lw, string'(" R^2 written in operand_2")); writeline(output, Lw);
else
write(Lw, string'(" failed to write R^2 to operand_2!")); writeline(output, Lw);
assert false report "Load R2 to op2 data verify failed!!" severity failure;
end if;
-- load a=1
------------
loadOp(op_3, one);
-- verify
readOp(op_3, data_read, base_width);
if (one(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
write(Lw, string'(" 1 written in operand_3")); writeline(output, Lw);
else
write(Lw, string'(" failed to write 1 to operand_3!")); writeline(output, Lw);
assert false report "Load 1 to op3 data verify failed!!" severity failure;
end if;
writeline(output, Lw);
write(Lw, string'("----- Pre-computations: "));
writeline(output, Lw);
-- compute gt0
---------------
core_x_sel_single <= "00"; -- g0
core_y_sel_single <= "10"; -- R^2
core_dest_op_single <= "00"; -- op_0 = (g0 * R) mod m
wait until rising_edge(clk);
timer := NOW;
core_start <= '1';
wait until rising_edge(clk);
core_start <= '0';
wait until core_ready = '1';
timer := NOW-timer;
waitclk(10);
readOp(op_0, data_read, base_width);
write(Lw, string'(" Computed gt0: "));
hwrite(Lw, data_read(base_width-1 downto 0));
writeline(output, Lw);
write(Lw, string'(" Read gt0: "));
hwrite(Lw, gt0(base_width-1 downto 0));
writeline(output, Lw);
write(Lw, string'(" => calc time is "));
write(Lw, string'(ToString(timer)));
writeline(output, Lw);
write(Lw, string'(" => expected time is "));
write(Lw, (nr_stages+(2*(base_width-1)))*clk_period);
writeline(output, Lw);
if (gt0(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
write(Lw, string'(" => gt0 is correct!")); writeline(output, Lw);
else
write(Lw, string'(" => Error: gt0 is incorrect!!!")); writeline(output, Lw);
assert false report "gt0 is incorrect!!!" severity failure;
end if;
-- compute gt1
---------------
core_x_sel_single <= "01"; -- g1
core_y_sel_single <= "10"; -- R^2
core_dest_op_single <= "01"; -- op_1 = (g1 * R) mod m
wait until rising_edge(clk);
timer := NOW;
core_start <= '1';
wait until rising_edge(clk);
core_start <= '0';
wait until core_ready = '1';
timer := NOW-timer;
waitclk(10);
readOp(op_1, data_read, base_width);
write(Lw, string'(" Computed gt1: "));
hwrite(Lw, data_read(base_width-1 downto 0));
writeline(output, Lw);
write(Lw, string'(" Read gt1: "));
hwrite(Lw, gt1(base_width-1 downto 0));
writeline(output, Lw);
write(Lw, string'(" => calc time is "));
write(Lw, string'(ToString(timer)));
writeline(output, Lw);
write(Lw, string'(" => expected time is "));
write(Lw, (nr_stages+(2*(base_width-1)))*clk_period);
writeline(output, Lw);
if (gt1(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
write(Lw, string'(" => gt1 is correct!")); writeline(output, Lw);
else
write(Lw, string'(" => Error: gt1 is incorrect!!!")); writeline(output, Lw);
assert false report "gt1 is incorrect!!!" severity failure;
end if;
-- compute a
-------------
core_x_sel_single <= "10"; -- R^2
core_y_sel_single <= "11"; -- 1
core_dest_op_single <= "11"; -- op_3 = (R) mod m
wait until rising_edge(clk);
core_start <= '1';
timer := NOW;
wait until rising_edge(clk);
core_start <= '0';
wait until core_ready = '1';
timer := NOW-timer;
waitclk(10);
readOp(op_3, data_read, base_width);
write(Lw, string'(" Computed a=(R)mod m: "));
hwrite(Lw, data_read(base_width-1 downto 0));
writeline(output, Lw);
write(Lw, string'(" Read (R)mod m: "));
hwrite(Lw, R(base_width-1 downto 0));
writeline(output, Lw);
write(Lw, string'(" => calc time is "));
write(Lw, string'(ToString(timer)));
writeline(output, Lw);
write(Lw, string'(" => expected time is "));
write(Lw, (nr_stages+(2*(base_width-1)))*clk_period);
writeline(output, Lw);
if (R(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
write(Lw, string'(" => (R)mod m is correct!")); writeline(output, Lw);
else
write(Lw, string'(" => Error: (R)mod m is incorrect!!!")); writeline(output, Lw);
assert false report "(R)mod m is incorrect!!!" severity failure;
end if;
-- compute gt01
---------------
core_x_sel_single <= "00"; -- gt0
core_y_sel_single <= "01"; -- gt1
core_dest_op_single <= "10"; -- op_2 = (gt0 * gt1) mod m
wait until rising_edge(clk);
core_start <= '1';
timer := NOW;
wait until rising_edge(clk);
core_start <= '0';
wait until core_ready = '1';
timer := NOW-timer;
waitclk(10);
readOp(op_2, data_read, base_width);
write(Lw, string'(" Computed gt01: "));
hwrite(Lw, data_read(base_width-1 downto 0));
writeline(output, Lw);
write(Lw, string'(" Read gt01: "));
hwrite(Lw, gt01(base_width-1 downto 0));
writeline(output, Lw);
write(Lw, string'(" => calc time is "));
write(Lw, string'(ToString(timer)));
writeline(output, Lw);
write(Lw, string'(" => expected time is "));
write(Lw, (nr_stages+(2*(base_width-1)))*clk_period);
writeline(output, Lw);
if (gt01(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
write(Lw, string'(" => gt01 is correct!")); writeline(output, Lw);
else
write(Lw, string'(" => Error: gt01 is incorrect!!!")); writeline(output, Lw);
assert false report "gt01 is incorrect!!!" severity failure;
end if;
-- load exponent fifo
----------------------
writeline(output, Lw);
write(Lw, string'("----- Loading exponent fifo: "));
writeline(output, Lw);
for i in (exponent_width/16)-1 downto 0 loop
core_fifo_din <= e1((i*16)+15 downto (i*16)) & e0((i*16)+15 downto (i*16));
wait until rising_edge(clk);
core_fifo_push <= '1';
wait until rising_edge(clk);
assert (core_fifo_full='0' and core_fifo_nopush='0')
report "Fifo error, full or nopush" severity failure;
core_fifo_push <= '0';
wait until rising_edge(clk);
end loop;
waitclk(10);
write(Lw, string'(" => Done"));
writeline(output, Lw);
-- start exponentiation
------------------------
writeline(output, Lw);
write(Lw, string'("----- Starting exponentiation: "));
writeline(output, Lw);
core_run_auto <= '1';
wait until rising_edge(clk);
timer := NOW;
core_start <= '1';
wait until rising_edge(clk);
core_start <= '0';
wait until core_ready='1';
timer := NOW-timer;
waitclk(10);
write(Lw, string'(" => calc time is "));
write(Lw, string'(ToString(timer)));
writeline(output, Lw);
write(Lw, string'(" => expected time is "));
write(Lw, ((nr_stages+(2*(base_width-1)))*clk_period*7*exponent_width)/4);
writeline(output, Lw);
write(Lw, string'(" => Done"));
core_run_auto <= '0';
writeline(output, Lw);
-- post-computations
---------------------
writeline(output, Lw);
write(Lw, string'("----- Post-computations: "));
writeline(output, Lw);
-- load in 1 to operand 2
loadOp(op_2, one);
-- verify
readOp(op_2, data_read, base_width);
if (one(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
write(Lw, string'(" 1 written in operand_2")); writeline(output, Lw);
else
write(Lw, string'(" failed to write 1 to operand_2!")); writeline(output, Lw);
assert false report "Load 1 to op2 data verify failed!!" severity failure;
end if;
-- compute result
core_x_sel_single <= "11"; -- a
core_y_sel_single <= "10"; -- 1
core_dest_op_single <= "11"; -- op_3 = (a) mod m
wait until rising_edge(clk);
timer := NOW;
core_start <= '1';
wait until rising_edge(clk);
core_start <= '0';
wait until core_ready = '1';
timer := NOW-timer;
waitclk(10);
readOp(op_3, data_read, base_width);
write(Lw, string'(" Computed result: "));
hwrite(Lw, data_read(base_width-1 downto 0));
writeline(output, Lw);
write(Lw, string'(" => calc time is "));
write(Lw, string'(ToString(timer)));
writeline(output, Lw);
write(Lw, string'(" => expected time is "));
write(Lw, (nr_stages+(2*(base_width-1)))*clk_period);
writeline(output, Lw);
when 12 => -- check with result
hread(L, result(base_width-1 downto 0), good_value);
assert good_value report "Can not read result! (wrong lenght?)" severity failure;
writeline(output, Lw);
write(Lw, string'("----- verifying result: "));
writeline(output, Lw);
write(Lw, string'(" Read result: "));
hwrite(Lw, result(base_width-1 downto 0));
writeline(output, Lw);
write(Lw, string'(" Computed result: "));
hwrite(Lw, data_read(base_width-1 downto 0));
writeline(output, Lw);
if (result(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
write(Lw, string'(" => Result is correct!")); writeline(output, Lw);
else
write(Lw, string'(" Error: result is incorrect!!!")); writeline(output, Lw);
assert false report "result is incorrect!!!" severity failure;
end if;
writeline(output, Lw);
 
when others =>
assert false report "undefined state!" severity failure;
end case;
if (param_count = 12) then
param_count := 0;
else
param_count := param_count+1;
end if;
end loop;
wait for 1 us;
assert false report "End of simulation" severity failure;
 
end process;
 
------------------------------------------
-- Multiplier core instance
------------------------------------------
the_multiplier : mod_sim_exp.mod_sim_exp_pkg.mod_sim_exp_core
port map(
clk => clk,
reset => reset,
-- operand memory interface (plb shared memory)
write_enable => core_write_enable,
data_in => core_data_in,
rw_address => core_rw_address,
data_out => core_data_out,
collision => core_mem_collision,
-- op_sel fifo interface
fifo_din => core_fifo_din,
fifo_push => core_fifo_push,
fifo_full => core_fifo_full,
fifo_nopush => core_fifo_nopush,
-- ctrl signals
start => core_start,
run_auto => core_run_auto,
ready => core_ready,
x_sel_single => core_x_sel_single,
y_sel_single => core_y_sel_single,
dest_op_single => core_dest_op_single,
p_sel => core_p_sel,
calc_time => calc_time
);
 
end test;
/Release_1.0/rtl/vhdl/core/mont_ctrl.vhd
0,0 → 1,202
----------------------------------------------------------------------
---- mont_ctrl ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- control unit for a pipelined montgomery multiplier, with ----
---- split pipeline operation and "auto-run" support ----
---- ----
---- Dependencies: ----
---- - autorun_cntrl ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
library mod_sim_exp;
use mod_sim_exp.mod_sim_exp_pkg.all;
 
 
-- This module controls the montgommery mutliplier and controls traffic between
-- RAM and multiplier. Also contains the autorun logic for exponentiations.
entity mont_ctrl is
port (
clk : in std_logic;
reset : in std_logic;
-- bus side
start : in std_logic;
x_sel_single : in std_logic_vector(1 downto 0);
y_sel_single : in std_logic_vector(1 downto 0);
run_auto : in std_logic;
op_buffer_empty : in std_logic;
op_sel_buffer : in std_logic_vector(31 downto 0);
read_buffer : out std_logic;
buffer_noread : in std_logic;
done : out std_logic;
calc_time : out std_logic;
-- multiplier side
op_sel : out std_logic_vector(1 downto 0);
load_x : out std_logic;
load_result : out std_logic;
start_multiplier : out std_logic;
multiplier_ready : in std_logic
);
end mont_ctrl;
 
 
architecture Behavioral of mont_ctrl is
signal start_d : std_logic; -- delayed version of start input
signal start_pulse : std_logic;
signal auto_start_pulse : std_logic;
signal start_multiplier_i : std_logic;
signal start_up_counter : std_logic_vector(2 downto 0) := "100"; -- used in op_sel at multiplier start
 
signal calc_time_i : std_logic; -- high ('1') during multiplication
 
signal x_sel : std_logic_vector(1 downto 0); -- the operand used as x input
signal y_sel : std_logic_vector(1 downto 0); -- the operand used as y input
signal x_sel_buffer : std_logic_vector(1 downto 0); -- x operand as specified by fifo buffer (autorun)
 
signal auto_done : std_logic;
signal start_auto : std_logic;
signal auto_multiplier_done_i : std_logic;
begin
 
-----------------------------------------------------------------------------------
-- Processes related to starting and stopping the multiplier
-----------------------------------------------------------------------------------
-- generate a start pulse (duration 1 clock cycle) based on ext. start sig
START_PULSE_PROC: process(clk)
begin
if rising_edge(clk) then
start_d <= start;
end if;
end process START_PULSE_PROC;
start_pulse <= start and (not start_d);
start_auto <= start_pulse and run_auto;
 
-- to start the multiplier we first need to select the x_operand and
-- clock it in the x shift register
-- the we select the y_operand and start the multiplier
-- start_up_counter
-- default state : "100"
-- at start pulse counter resets to 0 and counts up to "100"
START_MULT_PROC: process(clk, reset)
begin
if reset = '1' then
start_up_counter <= "100";
elsif rising_edge(clk) then
if start_pulse = '1' or auto_start_pulse = '1' then
start_up_counter <= "000";
elsif start_up_counter(2) /= '1' then
start_up_counter <= start_up_counter + '1';
else
start_up_counter <= "100";
end if;
else
start_up_counter <= start_up_counter;
end if;
end process;
-- select operands (autorun/single run)
x_sel <= x_sel_buffer when (run_auto = '1') else x_sel_single;
y_sel <= "11" when (run_auto = '1') else y_sel_single; -- y is operand3 in auto mode
-- clock operands to operand_mem output (first x, then y)
with start_up_counter(2 downto 1) select
op_sel <= x_sel when "00", -- start_up_counter="00x" (first 2 cycles)
y_sel when others; --
load_x <= start_up_counter(0) and (not start_up_counter(1)); -- latch x operand if start_up_counter="x01"
-- start multiplier when start_up_counter="x11"
start_multiplier_i <= start_up_counter(1) and start_up_counter(0);
start_multiplier <= start_multiplier_i;
 
-- signal calc time is high during multiplication
CALC_TIME_PROC: process(clk, reset)
begin
if reset = '1' then
calc_time_i <= '0';
elsif rising_edge(clk) then
if start_multiplier_i = '1' then
calc_time_i <= '1';
elsif multiplier_ready = '1' then
calc_time_i <= '0';
else
calc_time_i <= calc_time_i;
end if;
else
calc_time_i <= calc_time_i;
end if;
end process CALC_TIME_PROC;
calc_time <= calc_time_i;
-- what happens when a multiplication has finished
load_result <= multiplier_ready;
-- ignore multiplier_ready when in automode, the logic will assert auto_done when finished
done <= ((not run_auto) and multiplier_ready) or auto_done;
-----------------------------------------------------------------------------------
-- Processes related to op_buffer cntrl and auto_run mode
-- start_auto -> start autorun mode operation
-- auto_start_pulse <- autorun logic starts the multiplier
-- auto_done <- autorun logic signals when autorun operation has finished
-- x_sel_buffer <- autorun logic determines which operand is used as x
-- check buffer empty signal
-----------------------------------------------------------------------------------
 
-- multiplier_ready is only passed to autorun control when in autorun mode
auto_multiplier_done_i <= (multiplier_ready and run_auto);
autorun_control_logic : autorun_cntrl port map(
clk => clk,
reset => reset,
start => start_auto,
done => auto_done,
op_sel => x_sel_buffer,
start_multiplier => auto_start_pulse,
multiplier_done => auto_multiplier_done_i,
read_buffer => read_buffer,
buffer_din => op_sel_buffer,
buffer_empty => op_buffer_empty
);
 
end Behavioral;
/Release_1.0/rtl/vhdl/core/mod_sim_exp_pkg.vhd
0,0 → 1,658
----------------------------------------------------------------------
---- mod_sim_exp_pkg ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- Package for the Modular Simultaneous Exponentiation Core ----
---- Project. Contains the component declarations and used ----
---- constants. ----
---- ----
---- Dependencies: none ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
 
package mod_sim_exp_pkg is
--------------------------------------------------------------------
-- d_flip_flop
--------------------------------------------------------------------
-- 1-bit D flip-flop with asynchronous active high reset
--
component d_flip_flop is
port(
core_clk : in std_logic; -- clock signal
reset : in std_logic; -- active high reset
din : in std_logic; -- data in
dout : out std_logic -- data out
);
end component d_flip_flop;
--------------------------------------------------------------------
-- register_1b
--------------------------------------------------------------------
-- 1-bit register with asynchronous reset and clock enable
--
component register_1b is
port(
core_clk : in std_logic; -- clock input
ce : in std_logic; -- clock enable (active high)
reset : in std_logic; -- reset (active high)
din : in std_logic; -- data in
dout : out std_logic -- data out
);
end component register_1b;
--------------------------------------------------------------------
-- register_n
--------------------------------------------------------------------
-- n-bit register with asynchronous reset and clock enable
--
component register_n is
generic(
width : integer := 4
);
port(
core_clk : in std_logic; -- clock input
ce : in std_logic; -- clock enable (active high)
reset : in std_logic; -- reset (active high)
din : in std_logic_vector((width-1) downto 0); -- data in (width)-bit
dout : out std_logic_vector((width-1) downto 0) -- data out (width)-bit
);
end component register_n;
--------------------------------------------------------------------
-- cell_1b_adder
--------------------------------------------------------------------
-- 1-bit full adder cell using combinatorial logic
--
component cell_1b_adder is
port (
-- input operands a, b
a : in std_logic;
b : in std_logic;
-- carry in, out
cin : in std_logic;
cout : out std_logic;
-- result out
r : out std_logic
);
end component cell_1b_adder;
--------------------------------------------------------------------
-- cell_1b_mux
--------------------------------------------------------------------
-- 1-bit mux for a standard cell in the montgommery multiplier
-- systolic array
--
component cell_1b_mux is
port (
-- input bits
my : in std_logic;
y : in std_logic;
m : in std_logic;
-- selection bits
x : in std_logic;
q : in std_logic;
-- mux out
result : out std_logic
);
end component cell_1b_mux;
--------------------------------------------------------------------
-- cell_1b
--------------------------------------------------------------------
-- 1-bit cell for the systolic array
--
component cell_1b is
port (
-- operand input bits (m+y, y and m)
my : in std_logic;
y : in std_logic;
m : in std_logic;
-- operand x input bit and q
x : in std_logic;
q : in std_logic;
-- previous result input bit
a : in std_logic;
-- carry's
cin : in std_logic;
cout : out std_logic;
-- cell result out
r : out std_logic
);
end component cell_1b;
--------------------------------------------------------------------
-- adder_block
--------------------------------------------------------------------
-- (width)-bit full adder block using cell_1b_adders with buffered
-- carry out
--
component adder_block is
generic (
width : integer := 32 --adder operand widths
);
port (
-- clock input
core_clk : in std_logic;
-- adder input operands a, b (width)-bit
a : in std_logic_vector((width-1) downto 0);
b : in std_logic_vector((width-1) downto 0);
-- carry in, out
cin : in std_logic;
cout : out std_logic;
-- adder result out (width)-bit
r : out std_logic_vector((width-1) downto 0)
);
end component adder_block;
--------------------------------------------------------------------
-- adder_n
--------------------------------------------------------------------
-- n-bit adder using adder blocks. works in stages, to prevent
-- large carry propagation.
-- Result avaiable after (width/block_width) clock cycles
--
component adder_n is
generic (
width : integer := 1536; -- adder operands width
block_width : integer := 8 -- adder blocks size
);
port (
-- clock input
core_clk : in std_logic;
-- adder input operands (width)-bit
a : in std_logic_vector((width-1) downto 0);
b : in std_logic_vector((width-1) downto 0);
-- carry in, out
cin : in std_logic;
cout : out std_logic;
-- adder output result (width)-bit
r : out std_logic_vector((width-1) downto 0)
);
end component adder_n;
--------------------------------------------------------------------
-- standard_cell_block
--------------------------------------------------------------------
-- a standard cell block of (width)-bit for the montgommery multiplier
-- systolic array
--
component standard_cell_block is
generic (
width : integer := 16
);
port (
-- modulus and y operand input (width)-bit
my : in std_logic_vector((width-1) downto 0);
y : in std_logic_vector((width-1) downto 0);
m : in std_logic_vector((width-1) downto 0);
-- q and x operand input (serial input)
x : in std_logic;
q : in std_logic;
-- previous result in (width)-bit
a : in std_logic_vector((width-1) downto 0);
-- carry in and out
cin : in std_logic;
cout : out std_logic;
-- result out (width)-bit
r : out std_logic_vector((width-1) downto 0)
);
end component standard_cell_block;
--------------------------------------------------------------------
-- standard_stage
--------------------------------------------------------------------
-- standard stage for use in the montgommery multiplier pipeline
-- the result is available after 1 clock cycle
--
component standard_stage is
generic(
width : integer := 32
);
port(
-- clock input
core_clk : in std_logic;
-- modulus and y operand input (width)-bit
my : in std_logic_vector((width-1) downto 0);
y : in std_logic_vector((width-1) downto 0);
m : in std_logic_vector((width-1) downto 0);
-- q and x operand input (serial input)
xin : in std_logic;
qin : in std_logic;
-- q and x operand output (serial output)
xout : out std_logic;
qout : out std_logic;
-- msb input (lsb from next stage, for shift right operation)
a_msb : in std_logic;
-- carry out(clocked) and in
cin : in std_logic;
cout : out std_logic;
-- control singals
start : in std_logic;
reset : in std_logic;
done : out std_logic;
-- result out
r : out std_logic_vector((width-1) downto 0)
);
end component standard_stage;
--------------------------------------------------------------------
-- first_stage
--------------------------------------------------------------------
-- first stage for use in the montgommery multiplier pipeline
-- generates the q signal for all following stages
-- the result is available after 1 clock cycle
--
component first_stage is
generic(
width : integer := 16 -- must be the same as width of the standard stage
);
port(
-- clock input
core_clk : in std_logic;
-- modulus and y operand input (width+1)-bit
my : in std_logic_vector((width) downto 0);
y : in std_logic_vector((width) downto 0);
m : in std_logic_vector((width) downto 0);
-- x operand input (serial input)
xin : in std_logic;
-- q and x operand output (serial output)
xout : out std_logic;
qout : out std_logic;
-- msb input (lsb from next stage, for shift right operation)
a_msb : in std_logic;
-- carry out
cout : out std_logic;
-- control signals
start : in std_logic;
reset : in std_logic;
done : out std_logic;
-- result out
r : out std_logic_vector((width-1) downto 0)
);
end component first_stage;
--------------------------------------------------------------------
-- last_stage
--------------------------------------------------------------------
-- last stage for use in the montgommery multiplier pipeline
-- the result is available after 1 clock cycle
--
component last_stage is
generic(
width : integer := 16 -- must be the same as width of the standard stage
);
port(
-- clock input
core_clk : in std_logic;
-- modulus and y operand input (width(-1))-bit
my : in std_logic_vector((width-1) downto 0);
y : in std_logic_vector((width-2) downto 0);
m : in std_logic_vector((width-2) downto 0);
-- q and x operand input (serial input)
xin : in std_logic;
qin : in std_logic;
-- carry in
cin : in std_logic;
-- control signals
start : in std_logic;
reset : in std_logic;
-- result out
r : out std_logic_vector((width+1) downto 0)
);
end component last_stage;
--------------------------------------------------------------------
-- counter_sync
--------------------------------------------------------------------
-- counter with synchronous count enable. It generates an
-- overflow when max_value is reached
--
component counter_sync is
generic(
max_value : integer := 1024 -- maximum value (constraints the nr bits for counter)
);
port(
reset_value : in integer; -- value the counter counts to
core_clk : in std_logic; -- clock input
ce : in std_logic; -- count enable
reset : in std_logic; -- reset input
overflow : out std_logic -- gets high when counter reaches reset_value
);
end component counter_sync;
--------------------------------------------------------------------
-- stepping_logic
--------------------------------------------------------------------
-- stepping logic for the pipeline, generates the start pulses for the
-- first stage and keeps track of when the last stages are done
--
component stepping_logic is
generic(
n : integer := 1536; -- max nr of steps required to complete a multiplication
t : integer := 192 -- total nr of steps in the pipeline
);
port(
core_clk : in std_logic; -- clock input
start : in std_logic; -- start signal for pipeline (one multiplication)
reset : in std_logic; -- reset signal
t_sel : in integer range 0 to t; -- nr of stages in the pipeline piece
n_sel : in integer range 0 to n; -- nr of steps(bits in operands) required for a complete multiplication
start_first_stage : out std_logic; -- start pulse output for first stage
stepping_done : out std_logic -- done signal
);
end component stepping_logic;
 
--------------------------------------------------------------------
-- x_shift_reg
--------------------------------------------------------------------
-- shift register for the x operand of the multiplier
-- outputs the lsb of the register or bit at offset according to the
-- selected pipeline part
--
component x_shift_reg is
generic(
n : integer := 1536; -- width of the operands (# bits)
t : integer := 48; -- total number of stages
tl : integer := 16 -- lower number of stages
);
port(
-- clock input
clk : in std_logic;
-- x operand in (n-bit)
x_in : in std_logic_vector((n-1) downto 0);
-- control signals
reset : in std_logic; -- reset, clears register
load_x : in std_logic; -- load operand into shift register
next_x : in std_logic; -- next bit of x
p_sel : in std_logic_vector(1 downto 0); -- pipeline selection
-- x operand bit out (serial)
xi : out std_logic
);
end component x_shift_reg;
--------------------------------------------------------------------
-- systolic_pipeline
--------------------------------------------------------------------
-- systolic pipeline implementation of the montgommery multiplier
-- devides the pipeline into 2 parts, so 3 operand widths are supported
--
-- p_sel:
-- 01 = lower part
-- 10 = upper part
-- 11 = full range
component systolic_pipeline is
generic(
n : integer := 1536; -- width of the operands (# bits)
t : integer := 192; -- total number of stages (divider of n) >= 2
tl : integer := 64 -- lower number of stages (best take t = sqrt(n))
);
port(
-- clock input
core_clk : in std_logic;
-- modulus and y opperand input (n)-bit
my : in std_logic_vector((n) downto 0); -- m+y
y : in std_logic_vector((n-1) downto 0);
m : in std_logic_vector((n-1) downto 0);
-- x operand input (serial)
xi : in std_logic;
-- control signals
start : in std_logic; -- start multiplier
reset : in std_logic;
p_sel : in std_logic_vector(1 downto 0); -- select which piece of the multiplier will be used
ready : out std_logic; -- multiplication ready
next_x : out std_logic; -- next x operand bit
-- result out
r : out std_logic_vector((n+1) downto 0)
);
end component systolic_pipeline;
--------------------------------------------------------------------
-- mont_mult_sys_pipeline
--------------------------------------------------------------------
-- Structural description of the montgommery multiply pipeline
-- contains the x operand shift register, my adder, the pipeline and
-- reduction adder. To do a multiplication, the following actions must take place:
--
-- * load in the x operand in the shift register using the xy bus and load_x
-- * place the y operand on the xy bus for the rest of the operation
-- * generate a start pulse of 1 clk cycle long on start
-- * wait for ready signal
-- * result is avaiable on the r bus
--
component mont_mult_sys_pipeline is
generic (
n : integer := 1536; -- width of the operands
nr_stages : integer := 96; -- total number of stages
stages_low : integer := 32 -- lower number of stages
);
port (
-- clock input
core_clk : in std_logic;
-- operand inputs
xy : in std_logic_vector((n-1) downto 0); -- bus for x or y operand
m : in std_logic_vector((n-1) downto 0); -- modulus
-- result output
r : out std_logic_vector((n-1) downto 0); -- result
-- control signals
start : in std_logic;
reset : in std_logic;
p_sel : in std_logic_vector(1 downto 0);
load_x : in std_logic;
ready : out std_logic
);
end component mont_mult_sys_pipeline;
 
--------------------------------------------------------------------
-- mod_sim_exp_core
--------------------------------------------------------------------
-- toplevel of the modular simultaneous exponentiation core
-- contains an operand and modulus ram, multiplier, an exponent fifo
-- and control logic
--
component mod_sim_exp_core is
port(
clk : in std_logic;
reset : in std_logic;
-- operand memory interface (plb shared memory)
write_enable : in std_logic; -- write data to operand ram
data_in : in std_logic_vector (31 downto 0); -- operand ram data in
rw_address : in std_logic_vector (8 downto 0); -- operand ram address bus
data_out : out std_logic_vector (31 downto 0); -- operand ram data out
collision : out std_logic; -- write collision
-- op_sel fifo interface
fifo_din : in std_logic_vector (31 downto 0); -- exponent fifo data in
fifo_push : in std_logic; -- push data in exponent fifo
fifo_full : out std_logic; -- high if fifo is full
fifo_nopush : out std_logic; -- high if error during push
-- control signals
start : in std_logic; -- start multiplication/exponentiation
run_auto : in std_logic; -- single multiplication if low, exponentiation if high
ready : out std_logic; -- calculations done
x_sel_single : in std_logic_vector (1 downto 0); -- single multiplication x operand selection
y_sel_single : in std_logic_vector (1 downto 0); -- single multiplication y operand selection
dest_op_single : in std_logic_vector (1 downto 0); -- result destination operand selection
p_sel : in std_logic_vector (1 downto 0); -- pipeline part selection
calc_time : out std_logic
);
end component mod_sim_exp_core;
 
component autorun_cntrl is
port (
clk : in std_logic;
reset : in std_logic;
start : in std_logic;
done : out std_logic;
op_sel : out std_logic_vector (1 downto 0);
start_multiplier : out std_logic;
multiplier_done : in std_logic;
read_buffer : out std_logic;
buffer_din : in std_logic_vector (31 downto 0);
buffer_empty : in std_logic
);
end component autorun_cntrl;
component fifo_primitive is
port (
clk : in std_logic;
din : in std_logic_vector (31 downto 0);
dout : out std_logic_vector (31 downto 0);
empty : out std_logic;
full : out std_logic;
push : in std_logic;
pop : in std_logic;
reset : in std_logic;
nopop : out std_logic;
nopush : out std_logic
);
end component fifo_primitive;
component modulus_ram is
port(
clk : in std_logic;
modulus_addr : in std_logic_vector(5 downto 0);
write_modulus : in std_logic;
modulus_in : in std_logic_vector(31 downto 0);
modulus_out : out std_logic_vector(1535 downto 0)
);
end component modulus_ram;
component mont_ctrl is
port (
clk : in std_logic;
reset : in std_logic;
-- bus side
start : in std_logic;
x_sel_single : in std_logic_vector(1 downto 0);
y_sel_single : in std_logic_vector(1 downto 0);
run_auto : in std_logic;
op_buffer_empty : in std_logic;
op_sel_buffer : in std_logic_vector(31 downto 0);
read_buffer : out std_logic;
buffer_noread : in std_logic;
done : out std_logic;
calc_time : out std_logic;
-- multiplier side
op_sel : out std_logic_vector(1 downto 0);
load_x : out std_logic;
load_result : out std_logic;
start_multiplier : out std_logic;
multiplier_ready : in std_logic
);
end component mont_ctrl;
component operand_dp is
port (
clka : in std_logic;
wea : in std_logic_vector(0 downto 0);
addra : in std_logic_vector(5 downto 0);
dina : in std_logic_vector(31 downto 0);
douta : out std_logic_vector(511 downto 0);
clkb : in std_logic;
web : in std_logic_vector(0 downto 0);
addrb : in std_logic_vector(5 downto 0);
dinb : in std_logic_vector(511 downto 0);
doutb : out std_logic_vector(31 downto 0)
);
end component operand_dp;
component operand_mem is
generic(n : integer := 1536
);
port(
-- data interface (plb side)
data_in : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(31 downto 0);
rw_address : in std_logic_vector(8 downto 0);
-- address structure:
-- bit: 8 -> '1': modulus
-- '0': operands
-- bits: 7-6 -> operand_in_sel in case of bit 8 = '0'
-- don't care in case of modulus
-- bits: 5-0 -> modulus_addr / operand_addr resp.
-- operand interface (multiplier side)
op_sel : in std_logic_vector(1 downto 0);
xy_out : out std_logic_vector(1535 downto 0);
m : out std_logic_vector(1535 downto 0);
result_in : in std_logic_vector(1535 downto 0);
-- control signals
load_op : in std_logic;
load_m : in std_logic;
load_result : in std_logic;
result_dest_op : in std_logic_vector(1 downto 0);
collision : out std_logic;
-- system clock
clk : in std_logic
);
end component operand_mem;
component operand_ram is
port( -- write_operand_ack voorzien?
-- global ports
clk : in std_logic;
collision : out std_logic;
-- bus side connections (32-bit serial)
operand_addr : in std_logic_vector(5 downto 0);
operand_in : in std_logic_vector(31 downto 0);
operand_in_sel : in std_logic_vector(1 downto 0);
result_out : out std_logic_vector(31 downto 0);
write_operand : in std_logic;
-- multiplier side connections (1536 bit parallel)
result_dest_op : in std_logic_vector(1 downto 0);
operand_out : out std_logic_vector(1535 downto 0);
operand_out_sel : in std_logic_vector(1 downto 0); -- controlled by bus side
write_result : in std_logic;
result_in : in std_logic_vector(1535 downto 0)
);
end component operand_ram;
component operands_sp is
port (
clka : in std_logic;
wea : in std_logic_vector(0 downto 0);
addra : in std_logic_vector(4 downto 0);
dina : in std_logic_vector(31 downto 0);
douta : out std_logic_vector(511 downto 0)
);
end component operands_sp;
end package mod_sim_exp_pkg;
/Release_1.0/rtl/vhdl/core/mod_sim_exp_core.vhd
0,0 → 1,194
----------------------------------------------------------------------
---- mod_sim_exp_core ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- toplevel of a modular simultaneous exponentiation core ----
---- using a pipelined montgommery multiplier with split ----
---- pipeline and auto-run support ----
---- ----
---- Dependencies: ----
---- - mont_mult_sys_pipeline ----
---- - operand_mem ----
---- - fifo_primitive ----
---- - mont_ctrl ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
library mod_sim_exp;
use mod_sim_exp.mod_sim_exp_pkg.all;
 
-- toplevel of the modular simultaneous exponentiation core
-- contains an operand and modulus ram, multiplier, an exponent fifo
-- and control logic
entity mod_sim_exp_core is
port(
clk : in std_logic;
reset : in std_logic;
-- operand memory interface (plb shared memory)
write_enable : in std_logic; -- write data to operand ram
data_in : in std_logic_vector (31 downto 0); -- operand ram data in
rw_address : in std_logic_vector (8 downto 0); -- operand ram address bus
data_out : out std_logic_vector (31 downto 0); -- operand ram data out
collision : out std_logic; -- write collision
-- op_sel fifo interface
fifo_din : in std_logic_vector (31 downto 0); -- exponent fifo data in
fifo_push : in std_logic; -- push data in exponent fifo
fifo_full : out std_logic; -- high if fifo is full
fifo_nopush : out std_logic; -- high if error during push
-- control signals
start : in std_logic; -- start multiplication/exponentiation
run_auto : in std_logic; -- single multiplication if low, exponentiation if high
ready : out std_logic; -- calculations done
x_sel_single : in std_logic_vector (1 downto 0); -- single multiplication x operand selection
y_sel_single : in std_logic_vector (1 downto 0); -- single multiplication y operand selection
dest_op_single : in std_logic_vector (1 downto 0); -- result destination operand selection
p_sel : in std_logic_vector (1 downto 0); -- pipeline part selection
calc_time : out std_logic
);
end mod_sim_exp_core;
 
 
architecture Structural of mod_sim_exp_core is
constant n : integer := 1536;
constant t : integer := 96;
constant tl : integer := 32;
-- data busses
signal xy : std_logic_vector(n-1 downto 0); -- x and y operand data bus RAM -> multiplier
signal m : std_logic_vector(n-1 downto 0); -- modulus data bus RAM -> multiplier
signal r : std_logic_vector(n-1 downto 0); -- result data bus RAM <- multiplier
-- control signals
signal op_sel : std_logic_vector(1 downto 0); -- operand selection
signal result_dest_op : std_logic_vector(1 downto 0); -- result destination operand
signal mult_ready : std_logic;
signal start_mult : std_logic;
signal load_op : std_logic;
signal load_x : std_logic;
signal load_m : std_logic;
signal load_result : std_logic;
-- fifo signals
signal fifo_empty : std_logic;
signal fifo_pop : std_logic;
signal fifo_nopop : std_logic;
signal fifo_dout : std_logic_vector(31 downto 0);
begin
 
-- The actual multiplier
the_multiplier : mont_mult_sys_pipeline
generic map(
n => n,
nr_stages => t, --(divides n, bits_low & (n-bits_low))
stages_low => tl
)
port map(
core_clk => clk,
xy => xy,
m => m,
r => r,
start => start_mult,
reset => reset,
p_sel => p_sel,
load_x => load_x,
ready => mult_ready
);
 
-- Block ram memory for storing the operands and the modulus
the_memory : operand_mem
port map(
data_in => data_in,
data_out => data_out,
rw_address => rw_address,
op_sel => op_sel,
xy_out => xy,
m => m,
result_in => r,
load_op => load_op,
load_m => load_m,
load_result => load_result,
result_dest_op => result_dest_op,
collision => collision,
clk => clk
);
 
load_op <= write_enable when (rw_address(8) = '0') else '0';
load_m <= write_enable when (rw_address(8) = '1') else '0';
result_dest_op <= dest_op_single when run_auto = '0' else "11"; -- in autorun mode we always store the result in operand3
-- A fifo for auto-run operand selection
the_exponent_fifo : fifo_primitive
port map(
clk => clk,
din => fifo_din,
dout => fifo_dout,
empty => fifo_empty,
full => fifo_full,
push => fifo_push,
pop => fifo_pop,
reset => reset,
nopop => fifo_nopop,
nopush => fifo_nopush
);
-- The control logic for the core
the_control_unit : mont_ctrl
port map(
clk => clk,
reset => reset,
start => start,
x_sel_single => x_sel_single,
y_sel_single => y_sel_single,
run_auto => run_auto,
op_buffer_empty => fifo_empty,
op_sel_buffer => fifo_dout,
read_buffer => fifo_pop,
buffer_noread => fifo_nopop,
done => ready,
calc_time => calc_time,
op_sel => op_sel,
load_x => load_x,
load_result => load_result,
start_multiplier => start_mult,
multiplier_ready => mult_ready
);
 
end Structural;
/Release_1.0/rtl/vhdl/core/mont_mult_sys_pipeline.vhd
0,0 → 1,278
----------------------------------------------------------------------
---- mont_mult_sys_pipeline ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- n-bit montgomery multiplier with a pipelined systolic ----
---- array ----
---- ----
---- Dependencies: ----
---- - x_shift_reg ----
---- - adder_n ----
---- - d_flip_flop ----
---- - systolic_pipeline ----
---- - cell_1b_adder ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
library mod_sim_exp;
use mod_sim_exp.mod_sim_exp_pkg.all;
 
 
-- Structural description of the montgommery multiply pipeline
-- contains the x operand shift register, my adder, the pipeline and
-- reduction adder. To do a multiplication, the following actions must take place:
--
-- * load in the x operand in the shift register using the xy bus and load_x
-- * place the y operand on the xy bus for the rest of the operation
-- * generate a start pulse of 1 clk cycle long on start
-- * wait for ready signal
-- * result is avaiable on the r bus
--
entity mont_mult_sys_pipeline is
generic (
n : integer := 1536; -- width of the operands
nr_stages : integer := 96; -- total number of stages
stages_low : integer := 32 -- lower number of stages
);
port (
-- clock input
core_clk : in std_logic;
-- operand inputs
xy : in std_logic_vector((n-1) downto 0); -- bus for x or y operand
m : in std_logic_vector((n-1) downto 0); -- modulus
-- result output
r : out std_logic_vector((n-1) downto 0); -- result
-- control signals
start : in std_logic;
reset : in std_logic;
p_sel : in std_logic_vector(1 downto 0);
load_x : in std_logic;
ready : out std_logic
);
end mont_mult_sys_pipeline;
 
architecture Structural of mont_mult_sys_pipeline is
constant stage_width : integer := n/nr_stages;
constant bits_l : integer := stage_width * stages_low;
constant bits_h : integer := n - bits_l;
 
signal my : std_logic_vector(n downto 0);
signal my_h_cin : std_logic;
signal my_l_cout : std_logic;
signal r_pipeline : std_logic_vector(n+1 downto 0);
signal r_red : std_logic_vector(n-1 downto 0);
signal r_i : std_logic_vector(n-1 downto 0);
signal c_red_l : std_logic_vector(2 downto 0);
signal c_red_h : std_logic_vector(2 downto 0);
signal cin_red_h : std_logic;
signal r_sel : std_logic;
signal reset_multiplier : std_logic;
signal start_multiplier : std_logic;
signal m_inv : std_logic_vector(n-1 downto 0);
 
signal next_xi : std_logic;
signal xi : std_logic;
begin
 
-- register to store the x value in
-- outputs the operand in serial using a shift register
x_selection : x_shift_reg
generic map(
n => n,
t => nr_stages,
tl => stages_low
)
port map(
clk => core_clk,
reset => reset,
x_in => xy,
load_x => load_x,
next_x => next_xi,
p_sel => p_sel,
xi => xi
);
 
-- precomputation of my (m+y)
-- lower part of pipeline
my_adder_l : adder_n
generic map(
width => bits_l,
block_width => stage_width
)
port map(
core_clk => core_clk,
a => m((bits_l-1) downto 0),
b => xy((bits_l-1) downto 0),
cin => '0',
cout => my_l_cout,
r => my((bits_l-1) downto 0)
);
--higher part of pipeline
my_adder_h : adder_n
generic map(
width => bits_h,
block_width => stage_width
)
port map(
core_clk => core_clk,
a => m((n-1) downto bits_l),
b => xy((n-1) downto bits_l),
cin => my_h_cin,
cout => my(n),
r => my((n-1) downto bits_l)
);
-- if higher pipeline selected, do not give through carry, but 0
my_h_cin <= '0' when (p_sel(1) and (not p_sel(0)))='1' else my_l_cout;
-- multiplication
-- multiplier is reset every calculation or reset
reset_multiplier <= reset or start;
 
-- start is delayed 1 cycle
delay_1_cycle : d_flip_flop
port map(
core_clk => core_clk,
reset => reset,
din => start,
dout => start_multiplier
);
 
the_multiplier : systolic_pipeline
generic map(
n => n, -- width of the operands (# bits)
t => nr_stages, -- number of stages (divider of n) >= 2
tl => stages_low
)
port map(
core_clk => core_clk,
my => my,
y => xy,
m => m,
xi => xi,
start => start_multiplier,
reset => reset_multiplier,
p_sel => p_sel,
ready => ready,
next_x => next_xi,
r => r_pipeline
);
-- post-computation (reduction)
-- if the result is greater than the modulus, a final reduction with m is needed
-- this is done by using an adder and the 2s complement of m
m_inv <= not(m);
-- calculate r_l - m_l
reduction_adder_l : adder_n
generic map(
width => bits_l,
block_width => stage_width
)
port map(
core_clk => core_clk,
a => m_inv((bits_l-1) downto 0),
b => r_pipeline((bits_l-1) downto 0),
cin => '1', -- +1 for 2s complement
cout => c_red_l(0),
r => r_red((bits_l-1) downto 0)
);
-- pipeline result may be greater, check following bits
reduction_adder_l_a : cell_1b_adder
port map(
a => '1', -- for 2s complement of m
b => r_pipeline(bits_l),
cin => c_red_l(0),
cout => c_red_l(1)
--r =>
);
 
reduction_adder_l_b : cell_1b_adder
port map(
a => '1', -- for 2s complement of m
b => r_pipeline(bits_l+1),
cin => c_red_l(1),
cout => c_red_l(2)
-- r =>
);
 
-- pass cout from lower stages if full pipeline selected, else '1' (+1 for 2s complement)
cin_red_h <= c_red_l(0) when p_sel(0) = '1' else '1';
reduction_adder_h : adder_n
generic map(
width => bits_h,
block_width => stage_width
)
port map(
core_clk => core_clk,
a => m_inv((n-1) downto bits_l),
b => r_pipeline((n-1) downto bits_l),
cin => cin_red_h,
cout => c_red_h(0),
r => r_red((n-1) downto bits_l)
);
-- pipeline result may be greater, check following bits
reduction_adder_h_a : cell_1b_adder
port map(
a => '1', -- for 2s complement of m
b => r_pipeline(n),
cin => c_red_h(0),
cout => c_red_h(1)
);
 
reduction_adder_h_b : cell_1b_adder
port map(
a => '1', -- for 2s complement of m
b => r_pipeline(n+1),
cin => c_red_h(1),
cout => c_red_h(2)
);
-- select the correct result
r_sel <= (c_red_h(2) and p_sel(1)) or (c_red_l(2) and (p_sel(0) and (not p_sel(1))));
r_i <= r_red when r_sel = '1' else r_pipeline((n-1) downto 0);
-- output
r <= r_i;
end Structural;
/Release_1.0/rtl/vhdl/core/systolic_pipeline.vhd
0,0 → 1,367
----------------------------------------------------------------------
---- systolic_pipeline ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- structural description of a pipelined systolic array ----
---- implementation of a montgomery multiplier. ----
---- ----
---- Dependencies: ----
---- - stepping_logic ----
---- - first_stage ----
---- - standard_stage ----
---- - last_stage ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
library mod_sim_exp;
use mod_sim_exp.mod_sim_exp_pkg.all;
 
-- systolic pipeline implementation of the montgommery multiplier
-- devides the pipeline into 2 parts, so 3 operand widths are supported
--
-- p_sel:
-- 01 = lower part
-- 10 = upper part
-- 11 = full range
entity systolic_pipeline is
generic(
n : integer := 1536; -- width of the operands (# bits)
t : integer := 192; -- total number of stages (divider of n) >= 2
tl : integer := 64 -- lower number of stages (best take t = sqrt(n))
);
port(
-- clock input
core_clk : in std_logic;
-- modulus and y opperand input (n)-bit
my : in std_logic_vector((n) downto 0); -- m+y
y : in std_logic_vector((n-1) downto 0);
m : in std_logic_vector((n-1) downto 0);
-- x operand input (serial)
xi : in std_logic;
-- control signals
start : in std_logic; -- start multiplier
reset : in std_logic;
p_sel : in std_logic_vector(1 downto 0); -- select which piece of the multiplier will be used
ready : out std_logic; -- multiplication ready
next_x : out std_logic; -- next x operand bit
-- result out
r : out std_logic_vector((n+1) downto 0)
);
end systolic_pipeline;
 
 
architecture Structural of systolic_pipeline is
constant s : integer := n/t; -- stage width (# bits)
constant nl : integer := s*tl; -- lower pipeline width (# bits)
constant nh : integer := n - nl; -- higher pipeline width (# bits)
 
-- pipeline selection flags
signal p_full_selected : std_logic; -- full
signal p_low_full_selected : std_logic; -- low or full
signal p_high_selected : std_logic; -- high
signal t_sel : integer range 0 to t; -- width in stages of selected pipeline part
signal n_sel : integer range 0 to n; -- width in bits of selected pipeline part
-- general stage interconnect signals
signal start_stage : std_logic_vector((t-1) downto 0); -- vector for the start bits for the stages
signal done_stage : std_logic_vector((t-2) downto 0); -- vector for the done bits of the stages
signal xin_stage : std_logic_vector((t-1) downto 0); -- vector for the xin bits of the stages
signal qout_stage : std_logic_vector((t-2) downto 0); -- vector for the qout bits of the stages
signal cout_stage : std_logic_vector((t-2) downto 0); -- vector for the cout bits of the stages
-- stage result signals
signal r_tot : std_logic_vector((n+1) downto 0); -- result of the total multiplier
signal r_stage_midstart : std_logic_vector(s-1 downto 0); -- result of the mid-start stage of the multiplier
signal r_stage_midend : std_logic_vector((s+1) downto 0); -- result of the mid-end stage of the multiplier
-- mapped result registers
signal r_i : std_logic_vector((n+1) downto 0);
signal r_i_stage_midstart : std_logic_vector((s*2)-1 downto 0);
signal r_i_stage_midend : std_logic_vector((s*2)-1 downto 0);
 
-- pipeline start signals
signal start_first_stage : std_logic; -- start for full and low pipeline
signal start_higher : std_logic; -- start for higher pipeline
-- midstart stage signals
signal done_stage_midstart : std_logic;
signal xout_stage_midstart : std_logic;
signal qout_stage_midstart : std_logic;
signal cout_stage_midstart : std_logic;
-- tl+1 stage signals
signal xin_stage_tl_1 : std_logic;
signal qin_stage_tl_1 : std_logic;
signal cin_stage_tl_1 : std_logic;
begin
 
-- output mapping
r <= r_i;
 
-- result feedback
r_i((n+1) downto ((tl+1)*s)) <= r_tot((n+1) downto ((tl+1)*s));
r_i(((tl-1)*s-1) downto 0) <= r_tot(((tl-1)*s-1) downto 0);
r_i_stage_midend((s*2)-1 downto s+2) <= (others=>'0');
r_i_stage_midend((s+1) downto 0) <= r_stage_midend;
r_i_stage_midstart((s*2)-1 downto s) <= r_stage_midstart;
r_i_stage_midstart((s-1) downto 0) <= (others=>'0');
with p_sel select
r_i(((tl+1)*s-1) downto ((tl-1)*s)) <= r_i_stage_midend when "01",
r_i_stage_midstart when "10",
r_tot(((tl+1)*s-1) downto ((tl-1)*s)) when others;
 
-- signals from x_selection
next_x <= start_stage(1) or (start_stage(tl+1) and p_high_selected);
xin_stage(0) <= xi;
-- this module controls the pipeline operation
-- width in stages for selected pipeline
with p_sel select
t_sel <= tl when "01", -- lower pipeline part
t-tl when "10", -- higher pipeline part
t when others; -- full pipeline
 
-- width in bits for selected pipeline
with p_sel select
n_sel <= nl-1 when "01", -- lower pipeline part
nh-1 when "10", -- higher pipeline part
n-1 when others; -- full pipeline
with p_sel select
p_low_full_selected <= '0' when "10", -- higher pipeline part
'1' when others; -- full or lower pipeline
with p_sel select
p_high_selected <= '1' when "10", -- higher pipeline part
'0' when others; -- full or lower pipeline
p_full_selected <= p_sel(0) and p_sel(1);
-- stepping control logic to keep track off the multiplication and when it is done
stepping_control : stepping_logic
generic map(
n => n, -- max nr of steps required to complete a multiplication
t => t -- total nr of steps in the pipeline
)
port map(
core_clk => core_clk,
start => start,
reset => reset,
t_sel => t_sel,
n_sel => n_sel,
start_first_stage => start_first_stage,
stepping_done => ready
);
-- start signals for first stage of lower and higher part
start_stage(0) <= start_first_stage and p_low_full_selected;
start_higher <= start_first_stage and p_high_selected;
-- start signals for stage tl and tl+1 (full pipeline operation)
start_stage(tl) <= done_stage(tl-1) and p_full_selected; -- only pass the start signal if full pipeline
start_stage(tl+1) <= done_stage(tl) or done_stage_midstart;
-- nothing special here, previous stages starts the next
start_signals_l: for i in 1 to tl-1 generate
start_stage(i) <= done_stage(i-1);
end generate;
start_signals_h: for i in tl+2 to t-1 generate
start_stage(i) <= done_stage(i-1);
end generate;
-- first stage
-- bits (s downto 0)
stage_0 : first_stage
generic map(
width => s
)
port map(
core_clk => core_clk,
my => my(s downto 0),
y => y(s downto 0),
m => m(s downto 0),
xin => xin_stage(0),
xout => xin_stage(1),
qout => qout_stage(0),
a_msb => r_i(s),
cout => cout_stage(0),
start => start_stage(0),
reset => reset,
done => done_stage(0),
r => r_tot((s-1) downto 0)
);
-- lower pipeline standard stages: stages tl downto 1
-- bits ((tl+1)*s downto s+1)
-- (nl downto s+1)
stages_l : for i in 1 to (tl) generate
standard_stages : standard_stage
generic map(
width => s
)
port map(
core_clk => core_clk,
my => my(((i+1)*s) downto ((s*i)+1)),
y => y(((i+1)*s) downto ((s*i)+1)),
m => m(((i+1)*s) downto ((s*i)+1)),
xin => xin_stage(i),
qin => qout_stage(i-1),
xout => xin_stage(i+1),
qout => qout_stage(i),
a_msb => r_i((i+1)*s),
cin => cout_stage(i-1),
cout => cout_stage(i),
start => start_stage(i),
reset => reset,
done => done_stage(i),
r => r_tot((((i+1)*s)-1) downto (s*i))
);
end generate;
cin_stage_tl_1 <= cout_stage_midstart or cout_stage(tl);
qin_stage_tl_1 <= qout_stage_midstart or qout_stage(tl);
xin_stage_tl_1 <= xout_stage_midstart or xin_stage(tl+1);
stage_tl_1 : standard_stage
generic map(
width => s
)
port map(
core_clk => core_clk,
my => my(((tl+2)*s) downto ((s*(tl+1))+1)),
y => y(((tl+2)*s) downto ((s*(tl+1))+1)),
m => m(((tl+2)*s) downto ((s*(tl+1))+1)),
xin => xin_stage_tl_1,
qin => qin_stage_tl_1,
xout => xin_stage(tl+2),
qout => qout_stage(tl+1),
a_msb => r_i((tl+2)*s),
cin => cin_stage_tl_1,
cout => cout_stage(tl+1),
start => start_stage(tl+1),
reset => reset,
done => done_stage(tl+1),
r => r_tot((((tl+2)*s)-1) downto (s*(tl+1)))
);
 
stages_h : for i in (tl+2) to (t-2) generate
standard_stages : standard_stage
generic map(
width => s
)
port map(
core_clk => core_clk,
my => my(((i+1)*s) downto ((s*i)+1)),
y => y(((i+1)*s) downto ((s*i)+1)),
m => m(((i+1)*s) downto ((s*i)+1)),
xin => xin_stage(i),
qin => qout_stage(i-1),
xout => xin_stage(i+1),
qout => qout_stage(i),
a_msb => r_i((i+1)*s),
cin => cout_stage(i-1),
cout => cout_stage(i),
start => start_stage(i),
reset => reset,
done => done_stage(i),
r => r_tot((((i+1)*s)-1) downto (s*i))
);
end generate;
 
stage_t : last_stage
generic map(
width => s -- must be the same as width of the standard stage
)
port map(
core_clk => core_clk,
my => my(n downto ((n-s)+1)), --width-1
y => y((n-1) downto ((n-s)+1)), --width-2
m => m((n-1) downto ((n-s)+1)), --width-2
xin => xin_stage(t-1),
qin => qout_stage(t-2),
cin => cout_stage(t-2),
start => start_stage(t-1),
reset => reset,
r => r_tot((n+1) downto (n-s)) --width+1
);
 
mid_start : first_stage
generic map(
width => s
)
port map(
core_clk => core_clk,
my => my((tl*s+s) downto tl*s),
y => y((tl*s+s) downto tl*s),
m => m((tl*s+s) downto tl*s),
xin => xin_stage(0),
xout => xout_stage_midstart,
qout => qout_stage_midstart,
a_msb => r_i((tl+1)*s),
cout => cout_stage_midstart,
start => start_higher,
reset => reset,
done => done_stage_midstart,
r => r_stage_midstart
);
 
mid_end : last_stage
generic map(
width => s -- must be the same as width of the standard stage
)
port map(
core_clk => core_clk,
my => my((tl*s) downto ((tl-1)*s)+1), --width-1
y => y(((tl*s)-1) downto ((tl-1)*s)+1), --width-2
m => m(((tl*s)-1) downto ((tl-1)*s)+1), --width-2
xin => xin_stage(tl-1),
qin => qout_stage(tl-2),
cin => cout_stage(tl-2),
start => start_stage(tl-1),
reset => reset,
r => r_stage_midend --width+1
);
 
end Structural;
/Release_1.0/rtl/vhdl/core/x_shift_reg.vhd
0,0 → 1,100
----------------------------------------------------------------------
---- x_shift_reg ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- n bit shift register for the x operand of the multiplier ----
---- with bit output ----
---- ----
---- Dependencies: none ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
-- shift register for the x operand of the multiplier
-- outputs the lsb of the register or bit at offset according to the
-- selected pipeline part
entity x_shift_reg is
generic(
n : integer := 1536; -- width of the operands (# bits)
t : integer := 48; -- total number of stages
tl : integer := 16 -- lower number of stages
);
port(
-- clock input
clk : in std_logic;
-- x operand in (n-bit)
x_in : in std_logic_vector((n-1) downto 0);
-- control signals
reset : in std_logic; -- reset, clears register
load_x : in std_logic; -- load operand into shift register
next_x : in std_logic; -- next bit of x
p_sel : in std_logic_vector(1 downto 0); -- pipeline selection
-- x operand bit out (serial)
xi : out std_logic
);
end x_shift_reg;
 
 
architecture Behavioral of x_shift_reg is
signal x_reg : std_logic_vector((n-1) downto 0); -- register
constant s : integer := n/t; -- stage width
constant offset : integer := s*tl; -- calculate startbit pos of higher part of pipeline
begin
 
REG_PROC: process(reset, clk)
begin
if reset = '1' then -- Reset, clear the register
x_reg <= (others => '0');
elsif rising_edge(clk) then
if load_x = '1' then -- Load_x, load the register with x_in
x_reg <= x_in;
elsif next_x = '1' then -- next_x, shift to right. LSbit gets lost and zero's are shifted in
x_reg((n-2) downto 0) <= x_reg((n-1) downto 1);
else -- else remember state
x_reg <= x_reg;
end if;
end if;
end process;
 
with p_sel select -- pipeline select
xi <= x_reg(offset) when "10", -- use bit at offset for high part of pipeline
x_reg(0) when others; -- use LS bit for lower part of pipeline
 
end Behavioral;
/Release_1.0/rtl/vhdl/core/stepping_logic.vhd
0,0 → 1,166
----------------------------------------------------------------------
---- stepping_logic ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- stepping logic to control the pipeline for one ----
---- montgommery multiplication ----
---- ----
---- Dependencies: ----
---- - d_flip_flop ----
---- - counter_sync ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
library mod_sim_exp;
use mod_sim_exp.mod_sim_exp_pkg.all;
 
 
-- stepping logic for the pipeline, generates the start pulses for the
-- first stage and keeps track of when the last stages are done
entity stepping_logic is
generic(
n : integer := 1536; -- max nr of steps required to complete a multiplication
t : integer := 192 -- total nr of steps in the pipeline
);
port(
core_clk : in std_logic; -- clock input
start : in std_logic; -- start signal for pipeline (one multiplication)
reset : in std_logic; -- reset signal
t_sel : in integer range 0 to t; -- nr of stages in the pipeline piece
n_sel : in integer range 0 to n; -- nr of steps(bits in operands) required for a complete multiplication
start_first_stage : out std_logic; -- start pulse output for first stage
stepping_done : out std_logic -- done signal
);
end stepping_logic;
 
 
architecture Behavioral of stepping_logic is
 
-- signals for the first stage control, pulses and counters
signal first_stage_done : std_logic; -- indicates the first stage is done running for this multiplication
signal first_stage_active : std_logic; -- indicates the first stage is active
signal first_stage_active_d : std_logic; -- delayed version of first_stage_active
signal start_first_stage_i : std_logic; -- internal version of start_first_stage output
 
-- signals for the last stages control and counter
signal last_stages_done : std_logic; -- indicates the last stages are done running for this multiplication
signal last_stages_active : std_logic; -- indicates the last stages are active
signal last_stages_active_d : std_logic; -- delayed version of last_stages_active
 
begin
 
-- map outputs
stepping_done <= last_stages_done;
-- internal signals
--------------------
-- first_stage_active signal gets active from a start pulse
-- inactive from first_stage_done pulse
first_stage_active <= start or (first_stage_active_d and not first_stage_done);
-- done signal gets active from a first_stage_done pulse
-- inactive from last_stages_done pulse
last_stages_active <= first_stage_done or (last_stages_active_d and not last_stages_done);
-- map start_first_stage_i to output, but also use the initial start pulse
start_first_stage <= start or start_first_stage_i;
last_stages_active_delay : d_flip_flop
port map(
core_clk => core_clk,
reset => reset,
din => last_stages_active,
dout => last_stages_active_d
);
 
first_stage_active_delay : d_flip_flop
port map(
core_clk => core_clk,
reset => reset,
din => first_stage_active,
dout => first_stage_active_d
);
-- the counters
----------------
-- for counting the last steps (waiting for the other stages to stop)
-- counter for keeping track of how many stages are done
laststeps_counter : counter_sync
generic map(
max_value => t
)
port map(
reset_value => t_sel,
core_clk => core_clk,
ce => last_stages_active,
reset => reset,
overflow => last_stages_done
);
 
-- counter for keeping track of how many times the first stage is started
-- counts bits in operand x till operand width then generates pulse on first_stage_done
steps_counter : counter_sync
generic map(
max_value => n
)
port map(
reset_value => (n_sel),
core_clk => core_clk,
ce => start_first_stage_i,
reset => reset,
overflow => first_stage_done
);
 
-- the output (overflow) of this counter starts the first stage every 2 clock cycles
substeps_counter : counter_sync
generic map(
max_value => 2
)
port map(
reset_value => 2,
core_clk => core_clk,
ce => first_stage_active,
reset => reset,
overflow => start_first_stage_i
);
 
end Behavioral;
/Release_1.0/rtl/vhdl/core/counter_sync.vhd
0,0 → 1,94
----------------------------------------------------------------------
---- counter_sync ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- counter with synchronous count enable. It generates an ----
---- overflow when max_value is reached ----
---- ----
---- Dependencies: none ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
-- counter with synchronous count enable. It generates an
-- overflow when max_value is reached
entity counter_sync is
generic(
max_value : integer := 1024 -- maximum value (constraints the nr bits for counter)
);
port(
reset_value : in integer; -- value the counter counts to
core_clk : in std_logic; -- clock input
ce : in std_logic; -- count enable
reset : in std_logic; -- reset input
overflow : out std_logic -- gets high when counter reaches reset_value
);
end counter_sync;
 
 
architecture Behavioral of counter_sync is
begin
-- counter process with asynchronous active high reset
count_proc: process(core_clk, ce, reset)
variable steps_counter : integer range 0 to max_value-1;
begin
if reset = '1' then -- reset counter
steps_counter := 0;
overflow <= '0';
elsif rising_edge(core_clk) then
-- counter is enabled, count till reset_value
if ce = '1' then
if steps_counter = (reset_value-1) then -- generate overflow and reset counter
steps_counter := 0;
overflow <= '1';
else -- just count
steps_counter := steps_counter + 1;
overflow <= '0';
end if;
else
--counter disabled, halt counter
overflow <= '0';
steps_counter := steps_counter;
end if;
end if;
end process;
end Behavioral;
/Release_1.0/rtl/vhdl/core/first_stage.vhd
0,0 → 1,198
----------------------------------------------------------------------
---- first_stage ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- first stage for use in the montgommery multiplier ----
---- systolic array pipeline ----
---- ----
---- Dependencies: ----
---- - standard_cell_block ----
---- - d_flip_flop ----
---- - register_n ----
---- - register_1b ----
---- - cell_1b_mux ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
library mod_sim_exp;
use mod_sim_exp.mod_sim_exp_pkg.all;
 
-- first stage for use in the montgommery multiplier pipeline
-- generates the q signal for all following stages
-- the result is available after 1 clock cycle
entity first_stage is
generic(
width : integer := 16 -- must be the same as width of the standard stage
);
port(
-- clock input
core_clk : in std_logic;
-- modulus and y operand input (width+1)-bit
my : in std_logic_vector((width) downto 0);
y : in std_logic_vector((width) downto 0);
m : in std_logic_vector((width) downto 0);
-- x operand input (serial input)
xin : in std_logic;
-- q and x operand output (serial output)
xout : out std_logic;
qout : out std_logic;
-- msb input (lsb from next stage, for shift right operation)
a_msb : in std_logic;
-- carry out
cout : out std_logic;
-- control signals
start : in std_logic;
reset : in std_logic;
done : out std_logic;
-- result out
r : out std_logic_vector((width-1) downto 0)
);
end first_stage;
 
 
architecture Structural of first_stage is
-- output
signal cout_i : std_logic;
signal r_i : std_logic_vector((width-1) downto 0);
signal r_i_reg : std_logic_vector((width-1) downto 0);
signal qout_i : std_logic;
 
-- interconnection
signal first_res : std_logic;
signal c_first_res : std_logic;
signal a : std_logic_vector((width) downto 0);
 
begin
-- map internal signals to outputs
r <= r_i_reg;
-- a is equal to the right shifted version(/2) of r_reg with a_msb as MSB
a <= a_msb & r_i_reg;
 
-- compute first q and carry
qout_i <= a(0) xor (y(0) and xin);
c_first_res <= a(0) and first_res;
first_cell : cell_1b_mux
port map(
my => my(0),
y => y(0),
m => m(0),
x => xin,
q => qout_i,
result => first_res
);
 
-- structure of (width) standard_cell_blocks
cell_block : standard_cell_block
generic map(
width => width
)
port map(
my => my(width downto 1),
y => y(width downto 1),
m => m(width downto 1),
x => xin,
q => qout_i,
a => a(width downto 1),
cin => c_first_res,
cout => cout_i,
r => r_i((width-1) downto 0)
);
 
-- stage done signal
-- 1 cycle after start of stage
done_signal : d_flip_flop
port map(
core_clk => core_clk,
reset => reset,
din => start,
dout => done
);
 
-- output registers
--------------------
-- result register (width)-bit
result_reg : register_n
generic map(
width => width
)
port map(
core_clk => core_clk,
ce => start,
reset => reset,
din => r_i,
dout => r_i_reg
);
 
-- xout register
xout_reg : register_1b
port map(
core_clk => core_clk,
ce => start,
reset => reset,
din => xin,
dout => xout
);
-- qout register
qout_reg : register_1b
port map(
core_clk => core_clk,
ce => start,
reset => reset,
din => qout_i,
dout => qout
);
 
-- carry out register
cout_reg : register_1b
port map(
core_clk => core_clk,
ce => start,
reset => reset,
din => cout_i,
dout => cout
);
 
end Structural;
/Release_1.0/rtl/vhdl/core/standard_stage.vhd
0,0 → 1,181
----------------------------------------------------------------------
---- standard_stage ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- standard stage for use in the montgommery multiplier ----
---- systolic array pipeline ----
---- ----
---- Dependencies: ----
---- - standard_cell_block ----
---- - d_flip_flop ----
---- - register_n ----
---- - register_1b ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
library mod_sim_exp;
use mod_sim_exp.mod_sim_exp_pkg.all;
 
-- standard stage for use in the montgommery multiplier pipeline
-- the result is available after 1 clock cycle
entity standard_stage is
generic(
width : integer := 32
);
port(
-- clock input
core_clk : in std_logic;
-- modulus and y operand input (width)-bit
my : in std_logic_vector((width-1) downto 0);
y : in std_logic_vector((width-1) downto 0);
m : in std_logic_vector((width-1) downto 0);
-- q and x operand input (serial input)
xin : in std_logic;
qin : in std_logic;
-- q and x operand output (serial output)
xout : out std_logic;
qout : out std_logic;
-- msb input (lsb from next stage, for shift right operation)
a_msb : in std_logic;
-- carry out(clocked) and in
cin : in std_logic;
cout : out std_logic;
-- control singals
start : in std_logic;
reset : in std_logic;
done : out std_logic;
-- result out
r : out std_logic_vector((width-1) downto 0)
);
end standard_stage;
 
 
architecture Structural of standard_stage is
-- output
signal cout_i : std_logic;
signal r_i : std_logic_vector((width-1) downto 0);
signal r_i_reg : std_logic_vector((width-1) downto 0);
 
-- interconnect
signal a : std_logic_vector((width-1) downto 0);
 
begin
 
-- map internal signals to outputs
r <= r_i_reg;
-- a is equal to the right shifted version(/2) of r_reg with a_msb as MSB
a <= a_msb & r_i_reg((width-1) downto 1);
-- structure of (width) standard_cell_blocks
cell_block : standard_cell_block
generic map(
width => width
)
port map(
my => my,
y => y,
m => m,
x => xin,
q => qin,
a => a,
cin => cin,
cout => cout_i,
r => r_i
);
-- stage done signal
-- 1 cycle after start of stage
done_signal : d_flip_flop
port map(
core_clk => core_clk,
reset => reset,
din => start,
dout => done
);
 
-- output registers
--------------------
-- result register (width)-bit
result_reg : register_n
generic map(
width => width
)
port map(
core_clk => core_clk,
ce => start,
reset => reset,
din => r_i,
dout => r_i_reg
);
-- xout register
xout_reg : register_1b
port map(
core_clk => core_clk,
ce => start,
reset => reset,
din => xin,
dout => xout
);
-- qout register
qout_reg : register_1b
port map(
core_clk => core_clk,
ce => start,
reset => reset,
din => qin,
dout => qout
);
 
-- carry out register
cout_reg : register_1b
port map(
core_clk => core_clk,
ce => start,
reset => reset,
din => cout_i,
dout => cout
);
end Structural;
/Release_1.0/rtl/vhdl/core/last_stage.vhd
0,0 → 1,153
----------------------------------------------------------------------
---- last_stage ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- last stage for use in the montgommery multiplier ----
---- systolic array pipeline ----
---- ----
---- Dependencies: ----
---- - standard_cell_block ----
---- - register_n ----
---- - cell_1b ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
library mod_sim_exp;
use mod_sim_exp.mod_sim_exp_pkg.all;
 
-- last stage for use in the montgommery multiplier pipeline
-- the result is available after 1 clock cycle
entity last_stage is
generic(
width : integer := 16 -- must be the same as width of the standard stage
);
port(
-- clock input
core_clk : in std_logic;
-- modulus and y operand input (width(-1))-bit
my : in std_logic_vector((width-1) downto 0);
y : in std_logic_vector((width-2) downto 0);
m : in std_logic_vector((width-2) downto 0);
-- q and x operand input (serial input)
xin : in std_logic;
qin : in std_logic;
-- carry in
cin : in std_logic;
-- control signals
start : in std_logic;
reset : in std_logic;
-- result out
r : out std_logic_vector((width+1) downto 0)
);
end last_stage;
 
 
architecture Structural of last_stage is
-- input
signal my_i : std_logic_vector(width downto 0);
signal m_i : std_logic_vector(width downto 0);
signal y_i : std_logic_vector(width downto 0);
-- output
signal r_i : std_logic_vector((width+1) downto 0);
signal r_i_reg : std_logic_vector((width+1) downto 0);
 
-- interconnection
signal carry : std_logic;
signal a : std_logic_vector((width) downto 0);
begin
-- map internal signals to outputs
r <= r_i_reg;
-- map inputs to internal signals
my_i <= '0' & my;
m_i <= "00" & m;
y_i <= "00" & y;
 
-- a is equal to the right shifted version(/2) of r_reg
a <= r_i_reg((width+1) downto 1);
-- structure of (width) standard_cell_blocks
cell_block : standard_cell_block
generic map(
width => width
)
port map(
my => my_i(width-1 downto 0),
y => y_i(width-1 downto 0),
m => m_i(width-1 downto 0),
x => xin,
q => qin,
a => a((width-1) downto 0),
cin => cin,
cout => carry,
r => r_i((width-1) downto 0)
);
 
-- last cell of the pipeline
last_cell : cell_1b
port map(
my => my_i(width),
y => y_i(width),
m => m_i(width),
x => xin,
q => qin,
a => a(width),
cin => carry,
cout => r_i(width+1),
r => r_i(width)
);
 
-- output register (width+2)-bit
result_reg : register_n
generic map(
width => (width+2)
)
port map(
core_clk => core_clk,
ce => start,
reset => reset,
din => r_i,
dout => r_i_reg
);
end Structural;
/Release_1.0/rtl/vhdl/core/standard_cell_block.vhd
0,0 → 1,105
----------------------------------------------------------------------
---- standard_cell_block ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- a block of (width) cell_1b cells for use in the ----
---- montgommery multiplier systolic array ----
---- ----
---- Dependencies: ----
---- - cell_1b ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
library mod_sim_exp;
use mod_sim_exp.mod_sim_exp_pkg.all;
 
-- a standard cell block of (width)-bit for the montgommery multiplier
-- systolic array
entity standard_cell_block is
generic (
width : integer := 16
);
port (
-- modulus and y operand input (width)-bit
my : in std_logic_vector((width-1) downto 0);
y : in std_logic_vector((width-1) downto 0);
m : in std_logic_vector((width-1) downto 0);
-- q and x operand input (serial input)
x : in std_logic;
q : in std_logic;
-- previous result in (width)-bit
a : in std_logic_vector((width-1) downto 0);
-- carry in and out
cin : in std_logic;
cout : out std_logic;
-- result out (width)-bit
r : out std_logic_vector((width-1) downto 0)
);
end standard_cell_block;
 
 
architecture Structural of standard_cell_block is
-- vector for the carry bits
signal carry : std_logic_vector(width downto 0);
begin
-- carry in
carry(0) <= cin;
-- structure of (width) 1-bit cells
cell_block : for i in 0 to (width-1) generate
cells : cell_1b
port map(
my => my(i),
y => y(i),
m => m(i),
x => x,
q => q,
a => a(i),
cin => carry(i),
cout => carry(i+1),
r => r(i)
);
end generate;
-- carry out
cout <= carry(width);
end Structural;
/Release_1.0/rtl/vhdl/core/register_n.vhd
0,0 → 1,81
----------------------------------------------------------------------
---- register_n ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- n bit register with active high asynchronious reset and ce----
---- used in montgommery multiplier systolic array stages ----
---- ----
---- Dependencies: none ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
-- n-bit register with asynchronous reset and clock enable
entity register_n is
generic(
width : integer := 4
);
port(
core_clk : in std_logic; -- clock input
ce : in std_logic; -- clock enable (active high)
reset : in std_logic; -- reset (active high)
din : in std_logic_vector((width-1) downto 0); -- data in (width)-bit
dout : out std_logic_vector((width-1) downto 0) -- data out (width)-bit
);
end register_n;
 
 
architecture Behavorial of register_n is
begin
-- process for (width)-bit register
reg_nb : process (reset, ce, core_clk, din)
begin
if reset='1' then -- asynchronous active high reset
dout <= (others=>'0');
else
if rising_edge(core_clk) then -- clock in data on rising edge
if ce='1' then -- active high clock enable to clock in data
dout <= din;
end if;
end if;
end if;
end process;
 
end Behavorial;
/Release_1.0/rtl/vhdl/core/cell_1b.vhd
0,0 → 1,102
----------------------------------------------------------------------
---- cell_1b ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- 1-bit cell for use in the montgommery multiplier systolic ----
---- array ----
---- ----
---- Dependencies: ----
---- - cell_1bit_adder ----
---- - cell_1bit_mux ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
library mod_sim_exp;
use mod_sim_exp.mod_sim_exp_pkg.all;
 
-- 1-bit cell for the systolic array
entity cell_1b is
port (
-- operand input bits (m+y, y and m)
my : in std_logic;
y : in std_logic;
m : in std_logic;
-- operand x input bit and q
x : in std_logic;
q : in std_logic;
-- previous result input bit
a : in std_logic;
-- carry's
cin : in std_logic;
cout : out std_logic;
-- cell result out
r : out std_logic
);
end cell_1b;
 
 
architecture Structural of cell_1b is
-- mux to adder connection
signal mux2adder : std_logic;
begin
-- mux for my, y and m input bits
cell_mux : cell_1b_mux
port map(
my => my,
y => y,
m => m,
x => x,
q => q,
result => mux2adder
);
-- full adder for a+mux2adder
cell_adder : cell_1b_adder
port map(
a => a,
b => mux2adder,
cin => cin,
cout => cout,
r => r
);
 
end Structural;
/Release_1.0/rtl/vhdl/core/adder_n.vhd
0,0 → 1,110
----------------------------------------------------------------------
---- adder_n ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- This file contains the implementation of a n-bit adder ----
---- using adder_blocks, divides the adder in stages ----
---- used for the montgommery multiplier pre- and post- ----
---- computation adder ----
---- ----
---- Dependencies: ----
---- - adder_block ----
---- ----
---- Author(s): ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
library mod_sim_exp;
use mod_sim_exp.mod_sim_exp_pkg.all;
 
-- n-bit adder using adder blocks. works in stages, to prevent large
-- carry propagation
-- Result avaiable after (width/block_width) clock cycles
entity adder_n is
generic (
width : integer := 1536; -- adder operands width
block_width : integer := 8 -- adder blocks size
);
port (
-- clock input
core_clk : in std_logic;
-- adder input operands (width)-bit
a : in std_logic_vector((width-1) downto 0);
b : in std_logic_vector((width-1) downto 0);
-- carry in, out
cin : in std_logic;
cout : out std_logic;
-- adder output result (width)-bit
r : out std_logic_vector((width-1) downto 0)
);
end adder_n;
 
 
architecture Structural of adder_n is
constant nr_of_blocks : integer := width/block_width; -- number of blocks/stages in the adder
signal carry : std_logic_vector(nr_of_blocks downto 0); -- vector for the carry bits
begin
-- report failure if width is not dividable by block_width
assert (width mod block_width)=0
report "adder_n: width is not divisible by block_width!!" severity failure;
-- carry in
carry(0) <= cin;
 
-- structure of (nr_of_blocks) adder_blocks
adder_block_chain : for i in 0 to (nr_of_blocks-1) generate
adder_blocks : adder_block
generic map(
width => block_width
)
port map(
core_clk => core_clk,
a => a((((i+1)*block_width)-1) downto (i*block_width)),
b => b((((i+1)*block_width)-1) downto (i*block_width)),
cin => carry(i),
cout => carry(i+1),
r => r((((i+1)*block_width)-1) downto (i*block_width))
);
end generate;
 
-- carry out
cout <= carry(nr_of_blocks);
 
end Structural;
/Release_1.0/rtl/vhdl/core/adder_block.vhd
0,0 → 1,106
----------------------------------------------------------------------
---- adder_block ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- Adder block with a flipflop for the carry out so result ----
---- is available after 1 clock cycle ----
---- for use in the montgommery multiplier pre and post ----
---- computation adders ----
---- ----
---- Dependencies: ----
---- - cell_1b_adder ----
---- - d_flip_flop ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
library mod_sim_exp;
use mod_sim_exp.mod_sim_exp_pkg.all;
 
-- (width)-bit full adder block using cell_1b_adders
-- with buffered carry out -> result after 1 clock cycle
entity adder_block is
generic (
width : integer := 32 --adder operand widths
);
port (
-- clock input
core_clk : in std_logic;
-- adder input operands a, b (width)-bit
a : in std_logic_vector((width-1) downto 0);
b : in std_logic_vector((width-1) downto 0);
-- carry in, out
cin : in std_logic;
cout : out std_logic;
-- adder result out (width)-bit
r : out std_logic_vector((width-1) downto 0)
);
end adder_block;
 
 
architecture Structural of adder_block is
-- vector for the carry bits
signal carry : std_logic_vector(width downto 0);
begin
-- carry in
carry(0) <= cin;
 
-- structure of (width) cell_1b_adders
adder_chain : for i in 0 to (width-1) generate
adders : cell_1b_adder
port map(
a => a(i),
b => b(i),
cin => carry(i),
cout => carry(i+1),
r => r(i)
);
end generate;
-- buffer the carry every clock cycle
carry_reg : d_flip_flop
port map(
core_clk => core_clk,
reset => '0',
din => carry(width),
dout => cout
);
 
end Structural;
/Release_1.0/rtl/vhdl/core/cell_1b_adder.vhd
0,0 → 1,74
----------------------------------------------------------------------
---- cell_1b_adder ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- This file contains the implementation of a 1-bit full ----
---- adder cell using combinatorial logic ----
---- used in adder_block ----
---- ----
---- Dependencies: none ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
-- 1-bit full adder cell
entity cell_1b_adder is
port (
-- input operands a, b
a : in std_logic;
b : in std_logic;
-- carry in, out
cin : in std_logic;
cout : out std_logic;
-- result out
r : out std_logic
);
end cell_1b_adder;
 
 
architecture Behavioral of cell_1b_adder is
signal a_xor_b : std_logic;
begin
-- 1-bit full adder with combinatorial logic
-- uses 2 XOR's, 2 AND's and 1 OR port
a_xor_b <= a xor b;
r <= a_xor_b xor cin;
cout <= (a and b) or (cin and a_xor_b);
end Behavioral;
/Release_1.0/rtl/vhdl/core/cell_1b_mux.vhd
0,0 → 1,78
----------------------------------------------------------------------
---- cel_1b_mux ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- 1-bit mux for a standard cell in the montgommery ----
---- multiplier systolic array ----
---- ----
---- Dependencies: none ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
-- 1-bit mux for a standard cell in the montgommery multiplier systolic array
entity cell_1b_mux is
port (
-- input bits
my : in std_logic;
y : in std_logic;
m : in std_logic;
-- selection bits
x : in std_logic;
q : in std_logic;
-- mux out
result : out std_logic
);
end cell_1b_mux;
 
 
architecture Behavioral of cell_1b_mux is
signal sel : std_logic_vector(1 downto 0);
begin
-- selection bits
sel <= x & q;
-- multipexer
with sel select
result <= my when "11",
y when "10",
m when "01",
'0' when others;
 
end Behavioral;
/Release_1.0/rtl/vhdl/core/register_1b.vhd
0,0 → 1,79
----------------------------------------------------------------------
---- register_1b ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- 1 bit register with active high asynchronious reset and ce----
---- used in montgommery multiplier systolic array stages ----
---- ----
---- Dependencies: none ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
-- 1-bit register with asynchronous reset and clock enable
entity register_1b is
port(
core_clk : in std_logic; -- clock input
ce : in std_logic; -- clock enable (active high)
reset : in std_logic; -- reset (active high)
din : in std_logic; -- data in
dout : out std_logic -- data out
);
end register_1b;
 
 
architecture Behavorial of register_1b is
begin
-- process for 1-bit register
reg_1b : process (reset, ce, core_clk, din)
begin
if reset='1' then -- asynchronous active high reset
dout <= '0';
else
if rising_edge(core_clk) then -- clock in data on rising edge
if ce='1' then -- active high clock enable to clock in data
dout <= din;
end if;
end if;
end if;
end process;
end Behavorial;
/Release_1.0/rtl/vhdl/core/d_flip_flop.vhd
0,0 → 1,76
----------------------------------------------------------------------
---- d_flip_flop ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- 1-bit D flip-flop implemented with behavorial (generic) ----
---- description. With asynchronous active high reset. ----
---- ----
---- Dependencies: none ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
-- 1-bit D flip-flop with asynchronous active high reset
entity d_flip_flop is
port(
core_clk : in std_logic; -- clock signal
reset : in std_logic; -- active high reset
din : in std_logic; -- data in
dout : out std_logic -- data out
);
end d_flip_flop;
 
 
architecture Behavorial of d_flip_flop is
begin
-- process for 1-bit D flip-flop
d_FF : process (reset, core_clk, din)
begin
if reset='1' then -- asynchronous active high reset
dout <= '0';
else
if rising_edge(core_clk) then -- clock in data on rising edge
dout <= din;
end if;
end if;
end process;
end Behavorial;
/Release_1.0/rtl/vhdl/core/autorun_cntrl.vhd
0,0 → 1,187
----------------------------------------------------------------------
---- autorun_ctrl ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- autorun control unit for a pipelined montgomery ----
---- multiplier ----
---- ----
---- Dependencies: none ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
 
entity autorun_cntrl is
port (
clk : in std_logic;
reset : in std_logic;
start : in std_logic;
done : out std_logic;
op_sel : out std_logic_vector (1 downto 0);
start_multiplier : out std_logic;
multiplier_done : in std_logic;
read_buffer : out std_logic;
buffer_din : in std_logic_vector (31 downto 0);
buffer_empty : in std_logic
);
end autorun_cntrl;
 
 
architecture Behavioral of autorun_cntrl is
 
signal bit_counter_i : integer range 0 to 15 := 0;
signal bit_counter_0_i : std_logic;
signal bit_counter_15_i : std_logic;
signal next_bit_i : std_logic := '0';
signal next_bit_del_i : std_logic;
signal start_cycle_i : std_logic := '0';
signal start_cycle_del_i : std_logic;
signal done_i : std_logic;
signal start_i : std_logic;
signal running_i : std_logic;
signal start_multiplier_i : std_logic;
signal start_multiplier_del_i : std_logic;
signal mult_done_del_i : std_logic;
signal e0_i : std_logic_vector(15 downto 0);
signal e1_i : std_logic_vector(15 downto 0);
signal e0_bit_i : std_logic;
signal e1_bit_i : std_logic;
signal e_bits_i : std_logic_vector(1 downto 0);
signal e_bits_0_i : std_logic;
signal cycle_counter_i : std_logic;
signal op_sel_sel_i : std_logic;
signal op_sel_i : std_logic_vector(1 downto 0);
begin
 
done <= done_i;
-- the two exponents
e0_i <= buffer_din(15 downto 0);
e1_i <= buffer_din(31 downto 16);
 
-- generate the index to select a single bit from the two exponents
SYNC_BIT_COUNTER: process (clk, reset)
begin
if reset = '1' then
bit_counter_i <= 15;
elsif rising_edge(clk) then
if start = '1' then -- make sure we start @ bit 0
bit_counter_i <= 15;
elsif next_bit_i = '1' then -- count
if bit_counter_i = 0 then
bit_counter_i <= 15;
else
bit_counter_i <= bit_counter_i - 1;
end if;
end if;
end if;
end process SYNC_BIT_COUNTER;
-- signal when bit_counter_i = 0
bit_counter_0_i <= '1' when bit_counter_i=0 else '0';
bit_counter_15_i <= '1' when bit_counter_i=15 else '0';
-- the bits...
e0_bit_i <= e0_i(bit_counter_i);
e1_bit_i <= e1_i(bit_counter_i);
e_bits_i <= e0_bit_i & e1_bit_i;
e_bits_0_i <= '1' when (e_bits_i = "00") else '0';
-- operand pre-select
with e_bits_i select
op_sel_i <= "00" when "10", -- gt0
"01" when "01", -- gt1
"10" when "11", -- gt01
"11" when others;
-- select operands
op_sel_sel_i <= '0' when e_bits_0_i = '1' else (cycle_counter_i);
op_sel <= op_sel_i when op_sel_sel_i = '1' else "11";
-- process that drives running_i signal ('1' when in autorun, '0' when not)
RUNNING_PROC: process(clk, reset)
begin
if reset = '1' then
running_i <= '0';
elsif rising_edge(clk) then
running_i <= start or (running_i and (not done_i));
end if;
end process RUNNING_PROC;
-- ctrl logic
start_multiplier_i <= start_cycle_del_i or (mult_done_del_i and (cycle_counter_i) and (not e_bits_0_i));
read_buffer <= start_cycle_del_i and bit_counter_15_i and running_i; -- pop new word from fifo when bit_counter is back at '15'
start_multiplier <= start_multiplier_del_i and running_i;
-- start/stop logic
start_cycle_i <= (start and (not buffer_empty)) or next_bit_i; -- start pulse (external or internal)
done_i <= (start and buffer_empty) or (next_bit_i and bit_counter_0_i and buffer_empty); -- stop when buffer is empty
next_bit_i <= (mult_done_del_i and e_bits_0_i) or (mult_done_del_i and (not e_bits_0_i) and (not cycle_counter_i));
 
-- process for delaying signals with 1 clock cycle
DEL_PROC: process(clk)
begin
if rising_edge(clk) then
start_multiplier_del_i <= start_multiplier_i;
start_cycle_del_i <= start_cycle_i;
mult_done_del_i <= multiplier_done;
end if;
end process DEL_PROC;
-- process for delaying signals with 1 clock cycle
CYCLE_CNTR_PROC: process(clk, start)
begin
if start = '1' or reset = '1' then
cycle_counter_i <= '0';
elsif rising_edge(clk) then
if (e_bits_0_i = '0') and (multiplier_done = '1') then
cycle_counter_i <= not cycle_counter_i;
elsif (e_bits_0_i = '1') and (multiplier_done = '1') then
cycle_counter_i <= '0';
else
cycle_counter_i <= cycle_counter_i;
end if;
end if;
end process CYCLE_CNTR_PROC;
end Behavioral;
 
/Release_1.0/rtl/vhdl/core/fifo_primitive.vhd
0,0 → 1,143
----------------------------------------------------------------------
---- fifo_primitive ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- 512 x 32 bit fifo ----
---- ----
---- Dependencies: ----
---- - FIFO18E1 (xilinx primitive) ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
-- Xilinx primitives used in this code.
library UNISIM;
use UNISIM.VComponents.all;
 
 
entity fifo_primitive is
port (
clk : in std_logic;
din : in std_logic_vector (31 downto 0);
dout : out std_logic_vector (31 downto 0);
empty : out std_logic;
full : out std_logic;
push : in std_logic;
pop : in std_logic;
reset : in std_logic;
nopop : out std_logic;
nopush : out std_logic
);
end fifo_primitive;
 
 
architecture Behavioral of fifo_primitive is
signal rdcount : std_logic_vector(11 downto 0); -- debugging
signal wrcount : std_logic_vector(11 downto 0); -- debugging
signal reset_i, pop_i, push_i, empty_i, full_i, wrerr_i, rderr_i : std_logic;
begin
empty <= empty_i;
full <= full_i;
-- these logical equations need to be extended where necessary
nopop <= rderr_i or (pop and reset_i);
nopush <= wrerr_i or (push and reset_i);
pop_i <= pop and (not reset_i);
push_i <= push and (not reset_i);
-- makes the reset at least three clk_cycles long
RESET_PROC: process (reset, clk)
variable clk_counter : integer range 0 to 3 := 3;
begin
if reset = '1' then
reset_i <= '1';
clk_counter := 3;
elsif rising_edge(clk) then
if clk_counter = 0 then
clk_counter := 0;
reset_i <= '0';
else
clk_counter := clk_counter - 1;
reset_i <= '1';
end if;
end if;
end process;
 
FIFO18E1_inst : FIFO18E1
generic map (
ALMOST_EMPTY_OFFSET => X"00080", -- Sets the almost empty threshold
ALMOST_FULL_OFFSET => X"00080", -- Sets almost full threshold
DATA_WIDTH => 36, -- Sets data width to 4, 9, 18, or 36
DO_REG => 1, -- Enable output register (0 or 1) Must be 1 if EN_SYN = "FALSE"
EN_SYN => TRUE, -- Specifies FIFO as dual-clock ("FALSE") or Synchronous ("TRUE")
FIFO_MODE => "FIFO18_36", -- Sets mode to FIFO18 or FIFO18_36
FIRST_WORD_FALL_THROUGH => FALSE, -- Sets the FIFO FWFT to "TRUE" or "FALSE"
INIT => X"000000000", -- Initial values on output port
SRVAL => X"000000000" -- Set/Reset value for output port
)
port map (
-- ALMOSTEMPTY => ALMOSTEMPTY, -- 1-bit almost empty output flag
-- ALMOSTFULL => ALMOSTFULL, -- 1-bit almost full output flag
DO => dout, -- 32-bit data output
-- DOP => DOP, -- 4-bit parity data output
EMPTY => empty_i, -- 1-bit empty output flag
FULL => full_i, -- 1-bit full output flag
-- WRCOUNT, RDCOUNT: 12-bit (each) FIFO pointers
RDCOUNT => RDCOUNT, -- 12-bit read count output
WRCOUNT => WRCOUNT, -- 12-bit write count output
-- WRERR, RDERR: 1-bit (each) FIFO full or empty error
RDERR => rderr_i, -- 1-bit read error output
WRERR => wrerr_i, -- 1-bit write error
DI => din, -- 32-bit data input
DIP => "0000", -- 4-bit parity input
RDEN => pop_i, -- 1-bit read enable input
REGCE => '1', -- 1-bit clock enable input
RST => reset_i, -- 1-bit reset input
RSTREG => reset_i, -- 1-bit output register set/reset
-- WRCLK, RDCLK: 1-bit (each) Clocks
RDCLK => clk, -- 1-bit read clock input
WRCLK => clk, -- 1-bit write clock input
WREN => push_i -- 1-bit write enable input
);
 
end Behavioral;
/Release_1.0/rtl/vhdl/core/operand_dp.vhd
0,0 → 1,195
----------------------------------------------------------------------
---- operand_dp ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- 4 x 512 bit dual port ram for the operands ----
---- 32 bit read and write for bus side and 512 bit read and ----
---- write for multiplier side ----
---- ----
---- Dependencies: none ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
----------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2009 Xilinx, Inc. --
-- All rights reserved. --
----------------------------------------------------------------------
-- You must compile the wrapper file operand_dp.vhd when simulating
-- the core, operand_dp. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
 
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
 
 
library ieee;
use ieee.std_logic_1164.ALL;
-- synthesis translate_off
library XilinxCoreLib;
-- synthesis translate_on
 
 
entity operand_dp is
port (
clka : in std_logic;
wea : in std_logic_vector(0 downto 0);
addra : in std_logic_vector(5 downto 0);
dina : in std_logic_vector(31 downto 0);
douta : out std_logic_vector(511 downto 0);
clkb : in std_logic;
web : in std_logic_vector(0 downto 0);
addrb : in std_logic_vector(5 downto 0);
dinb : in std_logic_vector(511 downto 0);
doutb : out std_logic_vector(31 downto 0)
);
end operand_dp;
 
 
architecture operand_dp_a of operand_dp is
-- synthesis translate_off
component wrapped_operand_dp
port (
clka : in std_logic;
wea : in std_logic_vector(0 downto 0);
addra : in std_logic_vector(5 downto 0);
dina : in std_logic_vector(31 downto 0);
douta : out std_logic_vector(511 downto 0);
clkb : in std_logic;
web : in std_logic_vector(0 downto 0);
addrb : in std_logic_vector(5 downto 0);
dinb : in std_logic_vector(511 downto 0);
doutb : out std_logic_vector(31 downto 0)
);
end component;
 
-- Configuration specification
for all : wrapped_operand_dp use entity XilinxCoreLib.blk_mem_gen_v3_3(behavioral)
generic map(
c_has_regceb => 0,
c_has_regcea => 0,
c_mem_type => 2,
c_rstram_b => 0,
c_rstram_a => 0,
c_has_injecterr => 0,
c_rst_type => "SYNC",
c_prim_type => 1,
c_read_width_b => 32,
c_initb_val => "0",
c_family => "virtex6",
c_read_width_a => 512,
c_disable_warn_bhv_coll => 0,
c_write_mode_b => "WRITE_FIRST",
c_init_file_name => "no_coe_file_loaded",
c_write_mode_a => "WRITE_FIRST",
c_mux_pipeline_stages => 0,
c_has_mem_output_regs_b => 0,
c_has_mem_output_regs_a => 0,
c_load_init_file => 0,
c_xdevicefamily => "virtex6",
c_write_depth_b => 4,
c_write_depth_a => 64,
c_has_rstb => 0,
c_has_rsta => 0,
c_has_mux_output_regs_b => 0,
c_inita_val => "0",
c_has_mux_output_regs_a => 0,
c_addra_width => 6,
c_addrb_width => 6,
c_default_data => "0",
c_use_ecc => 0,
c_algorithm => 1,
c_disable_warn_bhv_range => 0,
c_write_width_b => 512,
c_write_width_a => 32,
c_read_depth_b => 64,
c_read_depth_a => 4,
c_byte_size => 9,
c_sim_collision_check => "ALL",
c_common_clk => 0,
c_wea_width => 1,
c_has_enb => 0,
c_web_width => 1,
c_has_ena => 0,
c_use_byte_web => 0,
c_use_byte_wea => 0,
c_rst_priority_b => "CE",
c_rst_priority_a => "CE",
c_use_default_data => 0
);
-- synthesis translate_on
begin
-- synthesis translate_off
U0 : wrapped_operand_dp
port map (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb
);
-- synthesis translate_on
 
end operand_dp_a;
/Release_1.0/rtl/vhdl/core/operands_sp.vhd
0,0 → 1,180
----------------------------------------------------------------------
---- operands_sp ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- 512 bit single port ram for the modulus ----
---- 32 write for bus side and 512 bit read for multplier side ----
---- ----
---- Dependencies: none ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
----------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2009 Xilinx, Inc. --
-- All rights reserved. --
----------------------------------------------------------------------
-- You must compile the wrapper file operand_dp.vhd when simulating
-- the core, operand_dp. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
 
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
 
 
library ieee;
use ieee.std_logic_1164.all;
-- synthesis translate_off
library XilinxCoreLib;
-- synthesis translate_on
 
 
entity operands_sp is
port (
clka : in std_logic;
wea : in std_logic_vector(0 downto 0);
addra : in std_logic_vector(4 downto 0);
dina : in std_logic_vector(31 downto 0);
douta : out std_logic_vector(511 downto 0)
);
end operands_sp;
 
 
architecture operands_sp_a of operands_sp is
-- synthesis translate_off
component wrapped_operands_sp
port (
clka : in std_logic;
wea : in std_logic_vector(0 downto 0);
addra : in std_logic_vector(4 downto 0);
dina : in std_logic_vector(31 downto 0);
douta : out std_logic_vector(511 downto 0)
);
end component;
 
-- Configuration specification
for all : wrapped_operands_sp use entity XilinxCoreLib.blk_mem_gen_v3_3(behavioral)
generic map(
c_has_regceb => 0,
c_has_regcea => 0,
c_mem_type => 0,
c_rstram_b => 0,
c_rstram_a => 0,
c_has_injecterr => 0,
c_rst_type => "SYNC",
c_prim_type => 1,
c_read_width_b => 32,
c_initb_val => "0",
c_family => "virtex6",
c_read_width_a => 512,
c_disable_warn_bhv_coll => 0,
c_write_mode_b => "WRITE_FIRST",
c_init_file_name => "no_coe_file_loaded",
c_write_mode_a => "WRITE_FIRST",
c_mux_pipeline_stages => 0,
c_has_mem_output_regs_b => 0,
c_has_mem_output_regs_a => 0,
c_load_init_file => 0,
c_xdevicefamily => "virtex6",
c_write_depth_b => 32,
c_write_depth_a => 32,
c_has_rstb => 0,
c_has_rsta => 0,
c_has_mux_output_regs_b => 0,
c_inita_val => "0",
c_has_mux_output_regs_a => 0,
c_addra_width => 5,
c_addrb_width => 5,
c_default_data => "0",
c_use_ecc => 0,
c_algorithm => 1,
c_disable_warn_bhv_range => 0,
c_write_width_b => 32,
c_write_width_a => 32,
c_read_depth_b => 32,
c_read_depth_a => 2,
c_byte_size => 9,
c_sim_collision_check => "ALL",
c_common_clk => 0,
c_wea_width => 1,
c_has_enb => 0,
c_web_width => 1,
c_has_ena => 0,
c_use_byte_web => 0,
c_use_byte_wea => 0,
c_rst_priority_b => "CE",
c_rst_priority_a => "CE",
c_use_default_data => 0
);
-- synthesis translate_on
 
begin
-- synthesis translate_off
u0 : wrapped_operands_sp
port map (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta
);
-- synthesis translate_on
 
end operands_sp_a;
/Release_1.0/rtl/vhdl/core/operand_mem.vhd
0,0 → 1,141
----------------------------------------------------------------------
---- operand_mem ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- BRAM memory and logic to the store 4 (1536-bit) operands ----
---- and the modulus for the montgomery multiplier ----
---- ----
---- Dependencies: ----
---- - operand_ram ----
---- - modulus_ram ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
library mod_sim_exp;
use mod_sim_exp.mod_sim_exp_pkg.all;
 
 
entity operand_mem is
generic(n : integer := 1536
);
port(
-- data interface (plb side)
data_in : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(31 downto 0);
rw_address : in std_logic_vector(8 downto 0);
-- address structure:
-- bit: 8 -> '1': modulus
-- '0': operands
-- bits: 7-6 -> operand_in_sel in case of bit 8 = '0'
-- don't care in case of modulus
-- bits: 5-0 -> modulus_addr / operand_addr resp.
 
-- operand interface (multiplier side)
op_sel : in std_logic_vector(1 downto 0);
xy_out : out std_logic_vector(1535 downto 0);
m : out std_logic_vector(1535 downto 0);
result_in : in std_logic_vector(1535 downto 0);
-- control signals
load_op : in std_logic;
load_m : in std_logic;
load_result : in std_logic;
result_dest_op : in std_logic_vector(1 downto 0);
collision : out std_logic;
-- system clock
clk : in std_logic
);
end operand_mem;
 
 
architecture Behavioral of operand_mem is
signal xy_data_i : std_logic_vector(31 downto 0);
signal xy_addr_i : std_logic_vector(5 downto 0);
signal operand_in_sel_i : std_logic_vector(1 downto 0);
signal collision_i : std_logic;
 
signal xy_op_i : std_logic_vector(1535 downto 0);
 
signal m_addr_i : std_logic_vector(5 downto 0);
signal write_m_i : std_logic;
signal m_data_i : std_logic_vector(31 downto 0);
 
begin
 
-- map outputs
xy_out <= xy_op_i;
collision <= collision_i;
 
-- map inputs
xy_addr_i <= rw_address(5 downto 0);
m_addr_i <= rw_address(5 downto 0);
operand_in_sel_i <= rw_address(7 downto 6);
xy_data_i <= data_in;
m_data_i <= data_in;
write_m_i <= load_m;
 
-- xy operand storage
xy_ram : operand_ram
port map(
clk => clk,
collision => collision_i,
operand_addr => xy_addr_i,
operand_in => xy_data_i,
operand_in_sel => operand_in_sel_i,
result_out => data_out,
write_operand => load_op,
operand_out => xy_op_i,
operand_out_sel => op_sel,
result_dest_op => result_dest_op,
write_result => load_result,
result_in => result_in
);
 
-- modulus storage
m_ram : modulus_ram
port map(
clk => clk,
modulus_addr => m_addr_i,
write_modulus => write_m_i,
modulus_in => m_data_i,
modulus_out => m
);
end Behavioral;
/Release_1.0/rtl/vhdl/core/modulus_ram.vhd
0,0 → 1,113
----------------------------------------------------------------------
---- modulus_ram ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- BRAM memory and logic to store the 1536-bit modulus ----
---- ----
---- Dependencies: ----
---- - operands_sp (coregen) ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
library mod_sim_exp;
use mod_sim_exp.mod_sim_exp_pkg.all;
 
 
entity modulus_ram is
port(
clk : in std_logic;
modulus_addr : in std_logic_vector(5 downto 0);
write_modulus : in std_logic;
modulus_in : in std_logic_vector(31 downto 0);
modulus_out : out std_logic_vector(1535 downto 0)
);
end modulus_ram;
 
 
architecture Behavioral of modulus_ram is
signal part_enable : std_logic_vector(3 downto 0);
signal wea : std_logic_vector(3 downto 0);
signal addra : std_logic_vector(4 downto 0);
begin
 
-- the blockram has a write depth of 2 but we only use the lower half
addra <= '0' & modulus_addr(3 downto 0);
-- the two highest bits of the address are used to select the bloc
with modulus_addr(5 downto 4) select
part_enable <= "0001" when "00",
"0010" when "01",
"0100" when "10",
"1000" when others;
 
with write_modulus select
wea <= part_enable when '1',
"0000" when others;
-- 4 instances of 512 bits blockram
modulus_0 : operands_sp
port map (
clka => clk,
wea => wea(0 downto 0),
addra => addra,
dina => modulus_in,
douta => modulus_out(511 downto 0)
);
 
modulus_1 : operands_sp
port map (
clka => clk,
wea => wea(1 downto 1),
addra => addra,
dina => modulus_in,
douta => modulus_out(1023 downto 512)
);
 
modulus_2 : operands_sp
port map (
clka => clk,
wea => wea(2 downto 2),
addra => addra,
dina => modulus_in,
douta => modulus_out(1535 downto 1024)
);
 
end Behavioral;
/Release_1.0/rtl/vhdl/core/operand_ram.vhd
0,0 → 1,170
----------------------------------------------------------------------
---- operand_ram ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- BRAM memory and logic to the store 4 (1536-bit) operands ----
---- for the montgomery multiplier ----
---- ----
---- Dependencies: ----
---- - operand_dp (coregen) ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
library mod_sim_exp;
use mod_sim_exp.mod_sim_exp_pkg.all;
 
 
entity operand_ram is
port( -- write_operand_ack voorzien?
-- global ports
clk : in std_logic;
collision : out std_logic;
-- bus side connections (32-bit serial)
operand_addr : in std_logic_vector(5 downto 0);
operand_in : in std_logic_vector(31 downto 0);
operand_in_sel : in std_logic_vector(1 downto 0);
result_out : out std_logic_vector(31 downto 0);
write_operand : in std_logic;
-- multiplier side connections (1536 bit parallel)
result_dest_op : in std_logic_vector(1 downto 0);
operand_out : out std_logic_vector(1535 downto 0);
operand_out_sel : in std_logic_vector(1 downto 0); -- controlled by bus side
write_result : in std_logic;
result_in : in std_logic_vector(1535 downto 0)
);
end operand_ram;
 
 
architecture Behavioral of operand_ram is
-- port a signals
signal addra : std_logic_vector(5 downto 0);
signal part_enable : std_logic_vector(3 downto 0);
signal wea : std_logic_vector(3 downto 0);
signal write_operand_i : std_logic;
 
-- port b signals
signal addrb : std_logic_vector(5 downto 0);
signal web : std_logic_vector(0 downto 0);
signal doutb0 : std_logic_vector(31 downto 0);
signal doutb1 : std_logic_vector(31 downto 0);
signal doutb2 : std_logic_vector(31 downto 0);
signal doutb3 : std_logic_vector(31 downto 0);
 
begin
 
-- WARNING: Very Important!
-- wea & web signals must never be high at the same time !!
-- web has priority
write_operand_i <= write_operand and not write_result;
web(0) <= write_result;
collision <= write_operand and write_result;
-- the dual port ram has a depth of 4 (each layer contains an operand)
-- result is always stored in position 3
-- doutb is always result
with write_operand_i select
addra <= operand_in_sel & operand_addr(3 downto 0) when '1',
operand_out_sel & "0000" when others;
with operand_addr(5 downto 4) select
part_enable <= "0001" when "00",
"0010" when "01",
"0100" when "10",
"1000" when others;
 
with write_operand_i select
wea <= part_enable when '1',
"0000" when others;
-- we can only read back from the result (stored in result_dest_op)
addrb <= result_dest_op & operand_addr(3 downto 0);
with operand_addr(5 downto 4) select
result_out <= doutb0 when "00",
doutb1 when "01",
doutb2 when "10",
doutb3 when others;
-- 3 instances of a dual port ram to store the parts of the operand
op_0 : operand_dp
port map (
clka => clk,
wea => wea(0 downto 0),
addra => addra,
dina => operand_in,
douta => operand_out(511 downto 0),
clkb => clk,
web => web,
addrb => addrb,
dinb => result_in(511 downto 0),
doutb => doutb0
);
 
op_1 : operand_dp
port map (
clka => clk,
wea => wea(1 downto 1),
addra => addra,
dina => operand_in,
douta => operand_out(1023 downto 512),
clkb => clk,
web => web,
addrb => addrb,
dinb => result_in(1023 downto 512),
doutb => doutb1
);
 
op_2 : operand_dp
port map (
clka => clk,
wea => wea(2 downto 2),
addra => addra,
dina => operand_in,
douta => operand_out(1535 downto 1024),
clkb => clk,
web => web,
addrb => addrb,
dinb => result_in(1535 downto 1024),
doutb => doutb2
);
 
end Behavioral;
/Release_1.0/rtl/vhdl/interface/plb/user_logic.vhd
0,0 → 1,450
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 2.00.a
-- Description: User logic.
-- Date: Thu May 03 09:53:36 2012 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
 
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
 
-- DO NOT EDIT ABOVE THIS LINE --------------------
 
--USER libraries added here
 
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_AWIDTH -- Slave interface address bus width
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_NUM_REG -- Number of software accessible registers
-- C_NUM_MEM -- Number of memory spaces
-- C_NUM_INTR -- Number of interrupt event
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Addr -- Bus to IP address bus
-- Bus2IP_CS -- Bus to IP chip select for user logic memory selection
-- Bus2IP_RNW -- Bus to IP read/not write
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
-- IP2Bus_IntrEvent -- IP to Bus interrupt event
------------------------------------------------------------------------------
 
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
 
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 6;
C_NUM_INTR : integer := 1
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
calc_time : out std_logic;
-- ctrl_sigs : out std_logic_vector( downto );
-- ADD USER PORTS ABOVE THIS LINE ------------------
 
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to C_SLV_AWIDTH-1);
Bus2IP_CS : in std_logic_vector(0 to C_NUM_MEM-1);
Bus2IP_RNW : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic;
IP2Bus_IntrEvent : out std_logic_vector(0 to C_NUM_INTR-1)
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
 
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Reset : signal is "RST";
 
end entity user_logic;
 
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
 
architecture IMP of user_logic is
 
--USER signal declarations added here, as needed for user logic
component multiplier_core
port( clk : in std_logic;
reset : in std_logic;
-- operand memory interface (plb shared memory)
write_enable : in std_logic;
data_in : in std_logic_vector (31 downto 0);
rw_address : in std_logic_vector (8 downto 0);
data_out : out std_logic_vector (31 downto 0);
collision : out std_logic;
-- op_sel fifo interface
fifo_din : in std_logic_vector (31 downto 0);
fifo_push : in std_logic;
fifo_full : out std_logic;
fifo_nopush : out std_logic;
-- ctrl signals
start : in std_logic;
run_auto : in std_logic;
ready : out std_logic;
x_sel_single : in std_logic_vector (1 downto 0);
y_sel_single : in std_logic_vector (1 downto 0);
dest_op_single : in std_logic_vector (1 downto 0);
p_sel : in std_logic_vector (1 downto 0);
calc_time : out std_logic
);
end component;
 
------------------------------------------------------------------
-- Signals for multiplier core slave model s/w accessible register
------------------------------------------------------------------
signal slv_reg0 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg_write_sel : std_logic_vector(0 to 0);
signal slv_reg_read_sel : std_logic_vector(0 to 0);
signal slv_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
 
signal load_flags : std_logic;
 
------------------------------------------------------------------
-- Signals for multiplier core interrupt
------------------------------------------------------------------
signal core_interrupt : std_logic_vector(0 to 0);
signal core_fifo_full : std_logic;
signal core_fifo_nopush : std_logic;
signal core_ready : std_logic;
signal core_mem_collision : std_logic;
 
------------------------------------------------------------------
-- Signals for multiplier core control
------------------------------------------------------------------
signal core_start : std_logic;
signal core_run_auto : std_logic;
signal core_p_sel : std_logic_vector(1 downto 0);
signal core_dest_op_single : std_logic_vector(1 downto 0);
signal core_x_sel_single : std_logic_vector(1 downto 0);
signal core_y_sel_single : std_logic_vector(1 downto 0);
signal core_flags : std_logic_vector(15 downto 0);
 
------------------------------------------------------------------
-- Signals for multiplier core memory space
------------------------------------------------------------------
signal mem_address : std_logic_vector(0 to 5);
signal mem_select : std_logic_vector(0 to 5);
signal mem_read_enable : std_logic;
signal mem_read_enable_dly1 : std_logic;
signal mem_read_req : std_logic;
signal mem_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal mem_read_ack_dly1 : std_logic;
signal mem_read_ack : std_logic;
signal mem_write_ack : std_logic;
 
signal core_rw_address : std_logic_vector (8 downto 0);
signal core_data_in : std_logic_vector(31 downto 0);
signal core_fifo_din : std_logic_vector(31 downto 0);
signal sel_mno : std_logic;
signal sel_op : std_logic_vector(1 downto 0);
signal core_data_out : std_logic_vector(31 downto 0);
signal core_write_enable : std_logic;
signal core_fifo_push : std_logic;
begin
 
--USER logic implementation added here
--ctrl_sigs <=
 
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_sel <= Bus2IP_WrCE(0 to 0);
slv_reg_read_sel <= Bus2IP_RdCE(0 to 0);
slv_write_ack <= Bus2IP_WrCE(0);
slv_read_ack <= Bus2IP_RdCE(0);
 
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_reg0 <= (others => '0');
elsif load_flags = '1' then
slv_reg0 <= slv_reg0(0 to 15) & core_flags;
else
case slv_reg_write_sel is
when "1" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when others => null;
end case;
end if;
end if;
 
end process SLAVE_REG_WRITE_PROC;
 
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0 ) is
begin
 
case slv_reg_read_sel is
when "1" => slv_ip2bus_data <= slv_reg0;
when others => slv_ip2bus_data <= (others => '0');
end case;
 
end process SLAVE_REG_READ_PROC;
 
------------------------------------------
-- Multiplier core interrupts form IP core interrupt
------------------------------------------
 
core_interrupt(0) <= core_ready or core_mem_collision or core_fifo_full or core_fifo_nopush;
IP2Bus_IntrEvent <= core_interrupt;
 
FLAGS_CNTRL_PROC: process(Bus2IP_Clk, Bus2IP_Reset) is
begin
if Bus2IP_Reset = '1' then
core_flags <= (others => '0');
load_flags <= '0';
elsif rising_edge(Bus2IP_Clk) then
if core_start = '1' then
core_flags <= (others => '0');
else
if core_ready = '1' then
core_flags(15) <= '1';
else
core_flags(15) <= core_flags(15);
end if;
if core_mem_collision = '1' then
core_flags(14) <= '1';
else
core_flags(14) <= core_flags(14);
end if;
if core_fifo_full = '1' then
core_flags(13) <= '1';
else
core_flags(13) <= core_flags(13);
end if;
if core_fifo_nopush = '1' then
core_flags(12) <= '1';
else
core_flags(12) <= core_flags(12);
end if;
end if;
--
load_flags <= core_interrupt(0);
end if;
end process FLAGS_CNTRL_PROC;
 
------------------------------------------
-- Example code to access user logic memory region
--
-- Note:
-- The example code presented here is to show you one way of using
-- the user logic memory space features. The Bus2IP_Addr, Bus2IP_CS,
-- and Bus2IP_RNW IPIC signals are dedicated to these user logic
-- memory spaces. Each user logic memory space has its own address
-- range and is allocated one bit on the Bus2IP_CS signal to indicated
-- selection of that memory space. Typically these user logic memory
-- spaces are used to implement memory controller type cores, but it
-- can also be used in cores that need to access additional address space
-- (non C_BASEADDR based), s.t. bridges. This code snippet infers
-- 6 256x32-bit (byte accessible) single-port Block RAM by XST.
------------------------------------------
mem_select <= Bus2IP_CS;
mem_read_enable <= ( Bus2IP_CS(0) or Bus2IP_CS(1) or Bus2IP_CS(2) or Bus2IP_CS(3) or Bus2IP_CS(4) or Bus2IP_CS(5) ) and Bus2IP_RNW;
mem_read_ack <= mem_read_ack_dly1;
mem_write_ack <= ( Bus2IP_CS(0) or Bus2IP_CS(1) or Bus2IP_CS(2) or Bus2IP_CS(3) or Bus2IP_CS(4) or Bus2IP_CS(5) ) and not(Bus2IP_RNW);
mem_address <= Bus2IP_Addr(C_SLV_AWIDTH-8 to C_SLV_AWIDTH-3);
 
-- implement single clock wide read request
mem_read_req <= mem_read_enable and not(mem_read_enable_dly1);
BRAM_RD_REQ_PROC : process( Bus2IP_Clk ) is
begin
 
if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if ( Bus2IP_Reset = '1' ) then
mem_read_enable_dly1 <= '0';
else
mem_read_enable_dly1 <= mem_read_enable;
end if;
end if;
 
end process BRAM_RD_REQ_PROC;
 
-- this process generates the read acknowledge 1 clock after read enable
-- is presented to the BRAM block. The BRAM block has a 1 clock delay
-- from read enable to data out.
BRAM_RD_ACK_PROC : process( Bus2IP_Clk ) is
begin
 
if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if ( Bus2IP_Reset = '1' ) then
mem_read_ack_dly1 <= '0';
else
mem_read_ack_dly1 <= mem_read_req;
end if;
end if;
 
end process BRAM_RD_ACK_PROC;
 
-- address logic
Sel_MNO <= mem_select(0);
with mem_select(1 to 4) select
Sel_Op <= "00" when "1000",
"01" when "0100",
"10" when "0010",
"11" when others;
core_rw_address <= Sel_MNO & Sel_Op & mem_address;
-- data-in
core_data_in <= Bus2IP_Data;
core_fifo_din <= Bus2IP_Data;
core_write_enable <= (Bus2IP_CS(0) or Bus2IP_CS(1) or Bus2IP_CS(2) or Bus2IP_CS(3) or Bus2IP_CS(4)) and (not Bus2IP_RNW);
core_fifo_push <= Bus2IP_CS(5) and (not Bus2IP_RNW);
-- no read mux required, we can only read from core_data_out
mem_ip2bus_data <= core_data_out;
 
------------------------------------------
-- Map slv_reg0 bits to core control signals
------------------------------------------
core_start <= slv_reg0(8);
core_run_auto <= slv_reg0(9);
core_p_sel <= slv_reg0(0 to 1);
core_dest_op_single <= slv_reg0(2 to 3);
core_x_sel_single <= slv_reg0(4 to 5);
core_y_sel_single <= slv_reg0(6 to 7);
 
------------------------------------------
-- Multiplier core instance
------------------------------------------
the_multiplier: multiplier_core
port map( clk => Bus2IP_Clk, -- v
reset => Bus2IP_Reset, -- v
-- operand memory interface (plb shared memory)
write_enable => core_write_enable,
data_in => core_data_in,
rw_address => core_rw_address,
data_out => core_data_out,
collision => core_mem_collision, -- v
-- op_sel fifo interface
fifo_din => core_fifo_din,
fifo_push => core_fifo_push,
fifo_full => core_fifo_full, -- v
fifo_nopush => core_fifo_nopush, -- v
-- ctrl signals
start => core_start, -- v
run_auto => core_run_auto, -- v
ready => core_ready, -- v
x_sel_single => core_x_sel_single, -- v
y_sel_single => core_y_sel_single, -- v
dest_op_single => core_dest_op_single, -- v
p_sel => core_p_sel, -- v
calc_time => calc_time -- v
);
 
------------------------------------------
-- Drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
mem_ip2bus_data when mem_read_ack = '1' else
(others => '0');
 
IP2Bus_WrAck <= slv_write_ack or mem_write_ack;
IP2Bus_RdAck <= slv_read_ack or mem_read_ack;
IP2Bus_Error <= '0';
 
end IMP;
/Release_1.0/rtl/vhdl/interface/plb/mont_mult1536.vhd
0,0 → 1,630
------------------------------------------------------------------------------
-- mont_mult1536.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: mont_mult1536.vhd
-- Version: 2.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Thu May 03 09:53:36 2012 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
use proc_common_v3_00_a.soft_reset;
 
library interrupt_control_v2_01_a;
use interrupt_control_v2_01_a.interrupt_control;
 
library plbv46_slave_single_v1_01_a;
use plbv46_slave_single_v1_01_a.plbv46_slave_single;
 
library mont_mult1536_v2_00_a;
use mont_mult1536_v2_00_a.user_logic;
 
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- PLBv46 slave: base address
-- C_HIGHADDR -- PLBv46 slave: high address
-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
-- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
-- C_FAMILY -- Xilinx FPGA family
-- C_MEM0_BASEADDR -- User memory space 0 base address
-- C_MEM0_HIGHADDR -- User memory space 0 high address
-- C_MEM1_BASEADDR -- User memory space 1 base address
-- C_MEM1_HIGHADDR -- User memory space 1 high address
-- C_MEM2_BASEADDR -- User memory space 2 base address
-- C_MEM2_HIGHADDR -- User memory space 2 high address
-- C_MEM3_BASEADDR -- User memory space 3 base address
-- C_MEM3_HIGHADDR -- User memory space 3 high address
-- C_MEM4_BASEADDR -- User memory space 4 base address
-- C_MEM4_HIGHADDR -- User memory space 4 high address
-- C_MEM5_BASEADDR -- User memory space 5 base address
-- C_MEM5_HIGHADDR -- User memory space 5 high address
--
-- Definition of Ports:
-- SPLB_Clk -- PLB main bus clock
-- SPLB_Rst -- PLB main bus reset
-- PLB_ABus -- PLB address bus
-- PLB_UABus -- PLB upper address bus
-- PLB_PAValid -- PLB primary address valid indicator
-- PLB_SAValid -- PLB secondary address valid indicator
-- PLB_rdPrim -- PLB secondary to primary read request indicator
-- PLB_wrPrim -- PLB secondary to primary write request indicator
-- PLB_masterID -- PLB current master identifier
-- PLB_abort -- PLB abort request indicator
-- PLB_busLock -- PLB bus lock
-- PLB_RNW -- PLB read/not write
-- PLB_BE -- PLB byte enables
-- PLB_MSize -- PLB master data bus size
-- PLB_size -- PLB transfer size
-- PLB_type -- PLB transfer type
-- PLB_lockErr -- PLB lock error indicator
-- PLB_wrDBus -- PLB write data bus
-- PLB_wrBurst -- PLB burst write transfer indicator
-- PLB_rdBurst -- PLB burst read transfer indicator
-- PLB_wrPendReq -- PLB write pending bus request indicator
-- PLB_rdPendReq -- PLB read pending bus request indicator
-- PLB_wrPendPri -- PLB write pending request priority
-- PLB_rdPendPri -- PLB read pending request priority
-- PLB_reqPri -- PLB current request priority
-- PLB_TAttribute -- PLB transfer attribute
-- Sl_addrAck -- Slave address acknowledge
-- Sl_SSize -- Slave data bus size
-- Sl_wait -- Slave wait indicator
-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
-- Sl_wrDAck -- Slave write data acknowledge
-- Sl_wrComp -- Slave write transfer complete indicator
-- Sl_wrBTerm -- Slave terminate write burst transfer
-- Sl_rdDBus -- Slave read data bus
-- Sl_rdWdAddr -- Slave read word address
-- Sl_rdDAck -- Slave read data acknowledge
-- Sl_rdComp -- Slave read transfer complete indicator
-- Sl_rdBTerm -- Slave terminate read burst transfer
-- Sl_MBusy -- Slave busy indicator
-- Sl_MWrErr -- Slave write error indicator
-- Sl_MRdErr -- Slave read error indicator
-- Sl_MIRQ -- Slave interrupt indicator
-- IP2INTC_Irpt -- Interrupt output to processor
------------------------------------------------------------------------------
 
entity mont_mult1536 is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
 
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 0;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_INCLUDE_DPHASE_TIMER : integer := 0;
C_FAMILY : string := "virtex5";
C_MEM0_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_MEM0_HIGHADDR : std_logic_vector := X"00000000";
C_MEM1_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_MEM1_HIGHADDR : std_logic_vector := X"00000000";
C_MEM2_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_MEM2_HIGHADDR : std_logic_vector := X"00000000";
C_MEM3_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_MEM3_HIGHADDR : std_logic_vector := X"00000000";
C_MEM4_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_MEM4_HIGHADDR : std_logic_vector := X"00000000";
C_MEM5_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_MEM5_HIGHADDR : std_logic_vector := X"00000000"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
calc_time : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
 
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
IP2INTC_Irpt : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
 
attribute SIGIS : string;
attribute SIGIS of SPLB_Clk : signal is "CLK";
attribute SIGIS of SPLB_Rst : signal is "RST";
attribute SIGIS of IP2INTC_Irpt : signal is "INTR_LEVEL_HIGH";
 
end entity mont_mult1536;
 
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
 
architecture IMP of mont_mult1536 is
 
------------------------------------------
-- Array of base/high address pairs for each address range
------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR or X"00000000";
constant USER_SLV_HIGHADDR : std_logic_vector := C_BASEADDR or X"000000FF";
constant RST_BASEADDR : std_logic_vector := C_BASEADDR or X"00000100";
constant RST_HIGHADDR : std_logic_vector := C_BASEADDR or X"000001FF";
constant INTR_BASEADDR : std_logic_vector := C_BASEADDR or X"00000200";
constant INTR_HIGHADDR : std_logic_vector := C_BASEADDR or X"000002FF";
 
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR, -- user logic slave space high address
ZERO_ADDR_PAD & RST_BASEADDR, -- soft reset space base address
ZERO_ADDR_PAD & RST_HIGHADDR, -- soft reset space high address
ZERO_ADDR_PAD & INTR_BASEADDR, -- interrupt control space base address
ZERO_ADDR_PAD & INTR_HIGHADDR, -- interrupt control space high address
ZERO_ADDR_PAD & C_MEM0_BASEADDR, -- user logic memory space 0 base address
ZERO_ADDR_PAD & C_MEM0_HIGHADDR, -- user logic memory space 0 high address
ZERO_ADDR_PAD & C_MEM1_BASEADDR, -- user logic memory space 1 base address
ZERO_ADDR_PAD & C_MEM1_HIGHADDR, -- user logic memory space 1 high address
ZERO_ADDR_PAD & C_MEM2_BASEADDR, -- user logic memory space 2 base address
ZERO_ADDR_PAD & C_MEM2_HIGHADDR, -- user logic memory space 2 high address
ZERO_ADDR_PAD & C_MEM3_BASEADDR, -- user logic memory space 3 base address
ZERO_ADDR_PAD & C_MEM3_HIGHADDR, -- user logic memory space 3 high address
ZERO_ADDR_PAD & C_MEM4_BASEADDR, -- user logic memory space 4 base address
ZERO_ADDR_PAD & C_MEM4_HIGHADDR, -- user logic memory space 4 high address
ZERO_ADDR_PAD & C_MEM5_BASEADDR, -- user logic memory space 5 base address
ZERO_ADDR_PAD & C_MEM5_HIGHADDR -- user logic memory space 5 high address
);
 
------------------------------------------
-- Array of desired number of chip enables for each address range
------------------------------------------
constant USER_SLV_NUM_REG : integer := 1;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant RST_NUM_CE : integer := 1;
constant INTR_NUM_CE : integer := 16;
constant USER_NUM_MEM : integer := 6;
 
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => pad_power2(USER_SLV_NUM_REG), -- number of ce for user logic slave space
1 => RST_NUM_CE, -- number of ce for soft reset space
2 => INTR_NUM_CE, -- number of ce for interrupt control space
3 => 1, -- number of ce for user logic memory space 0 (always 1 chip enable)
4 => 1, -- number of ce for user logic memory space 1 (always 1 chip enable)
5 => 1, -- number of ce for user logic memory space 2 (always 1 chip enable)
6 => 1, -- number of ce for user logic memory space 3 (always 1 chip enable)
7 => 1, -- number of ce for user logic memory space 4 (always 1 chip enable)
8 => 1 -- number of ce for user logic memory space 5 (always 1 chip enable)
);
 
------------------------------------------
-- Ratio of bus clock to core clock (for use in dual clock systems)
-- 1 = ratio is 1:1
-- 2 = ratio is 2:1
------------------------------------------
constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
 
------------------------------------------
-- Width of the slave data bus (32 only)
------------------------------------------
constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
 
constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
 
------------------------------------------
-- Width of triggered reset in bus clocks
------------------------------------------
constant RESET_WIDTH : integer := 4;
 
------------------------------------------
-- Number of device level interrupts
------------------------------------------
constant INTR_NUM_IPIF_IRPT_SRC : integer := 4;
 
------------------------------------------
-- Capture mode for each IP interrupt (generated by user logic)
-- 1 = pass through (non-inverting)
-- 2 = pass through (inverting)
-- 3 = registered level (non-inverting)
-- 4 = registered level (inverting)
-- 5 = positive edge detect
-- 6 = negative edge detect
------------------------------------------
constant USER_NUM_INTR : integer := 1;
constant USER_INTR_CAPTURE_MODE : integer := 1;
 
constant INTR_IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => USER_INTR_CAPTURE_MODE
);
 
------------------------------------------
-- Device priority encoder feature inclusion/omission
-- true = include priority encoder
-- false = omit priority encoder
------------------------------------------
constant INTR_INCLUDE_DEV_PENCODER : boolean := false;
 
------------------------------------------
-- Device ISC feature inclusion/omission
-- true = include device ISC
-- false = omit device ISC
------------------------------------------
constant INTR_INCLUDE_DEV_ISC : boolean := false;
 
------------------------------------------
-- Width of the slave address bus (32 only)
------------------------------------------
constant USER_SLV_AWIDTH : integer := C_SPLB_AWIDTH;
 
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant RST_CS_INDEX : integer := 1;
constant RST_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, RST_CS_INDEX);
constant INTR_CS_INDEX : integer := 2;
constant INTR_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, INTR_CS_INDEX);
constant USER_MEM0_CS_INDEX : integer := 3;
constant USER_CS_INDEX : integer := USER_MEM0_CS_INDEX;
 
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
 
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Reset : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal rst_Bus2IP_Reset : std_logic;
signal rst_IP2Bus_WrAck : std_logic;
signal rst_IP2Bus_Error : std_logic;
signal intr_IPIF_Reg_Interrupts : std_logic_vector(0 to 1);
signal intr_IPIF_Lvl_Interrupts : std_logic_vector(0 to INTR_NUM_IPIF_IRPT_SRC-1);
signal intr_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal intr_IP2Bus_WrAck : std_logic;
signal intr_IP2Bus_RdAck : std_logic;
signal intr_IP2Bus_Error : std_logic;
signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
signal user_IP2Bus_IntrEvent : std_logic_vector(0 to USER_NUM_INTR-1);
 
begin
 
------------------------------------------
-- instantiate plbv46_slave_single
------------------------------------------
PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single
generic map
(
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_SPLB_P2P => C_SPLB_P2P,
C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
C_FAMILY => C_FAMILY
)
port map
(
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
IP2Bus_Data => ipif_IP2Bus_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE
);
 
------------------------------------------
-- instantiate soft_reset
------------------------------------------
SOFT_RESET_I : entity proc_common_v3_00_a.soft_reset
generic map
(
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_RESET_WIDTH => RESET_WIDTH
)
port map
(
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_WrCE => ipif_Bus2IP_WrCE(RST_CE_INDEX),
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Reset2IP_Reset => rst_Bus2IP_Reset,
Reset2Bus_WrAck => rst_IP2Bus_WrAck,
Reset2Bus_Error => rst_IP2Bus_Error,
Reset2Bus_ToutSup => open
);
 
------------------------------------------
-- instantiate interrupt_control
------------------------------------------
INTERRUPT_CONTROL_I : entity interrupt_control_v2_01_a.interrupt_control
generic map
(
C_NUM_CE => INTR_NUM_CE,
C_NUM_IPIF_IRPT_SRC => INTR_NUM_IPIF_IRPT_SRC,
C_IP_INTR_MODE_ARRAY => INTR_IP_INTR_MODE_ARRAY,
C_INCLUDE_DEV_PENCODER => INTR_INCLUDE_DEV_PENCODER,
C_INCLUDE_DEV_ISC => INTR_INCLUDE_DEV_ISC,
C_IPIF_DWIDTH => IPIF_SLV_DWIDTH
)
port map
(
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => rst_Bus2IP_Reset,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Interrupt_RdCE => ipif_Bus2IP_RdCE(INTR_CE_INDEX to INTR_CE_INDEX+INTR_NUM_CE-1),
Interrupt_WrCE => ipif_Bus2IP_WrCE(INTR_CE_INDEX to INTR_CE_INDEX+INTR_NUM_CE-1),
IPIF_Reg_Interrupts => intr_IPIF_Reg_Interrupts,
IPIF_Lvl_Interrupts => intr_IPIF_Lvl_Interrupts,
IP2Bus_IntrEvent => user_IP2Bus_IntrEvent,
Intr2Bus_DevIntr => IP2INTC_Irpt,
Intr2Bus_DBus => intr_IP2Bus_Data,
Intr2Bus_WrAck => intr_IP2Bus_WrAck,
Intr2Bus_RdAck => intr_IP2Bus_RdAck,
Intr2Bus_Error => intr_IP2Bus_Error,
Intr2Bus_Retry => open,
Intr2Bus_ToutSup => open
);
 
-- feed registered and level-pass-through interrupts into Device ISC if exists, otherwise ignored
intr_IPIF_Reg_Interrupts(0) <= '0';
intr_IPIF_Reg_Interrupts(1) <= '0';
intr_IPIF_Lvl_Interrupts(0) <= '0';
intr_IPIF_Lvl_Interrupts(1) <= '0';
intr_IPIF_Lvl_Interrupts(2) <= '0';
intr_IPIF_Lvl_Interrupts(3) <= '0';
 
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity mont_mult1536_v2_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
 
C_SLV_AWIDTH => USER_SLV_AWIDTH,
C_SLV_DWIDTH => USER_SLV_DWIDTH,
C_NUM_REG => USER_NUM_REG,
C_NUM_MEM => USER_NUM_MEM,
C_NUM_INTR => USER_NUM_INTR
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
calc_time => calc_time,
-- MAP USER PORTS ABOVE THIS LINE ------------------
 
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => rst_Bus2IP_Reset,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_CS => ipif_Bus2IP_CS(USER_CS_INDEX to USER_CS_INDEX+USER_NUM_MEM-1),
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error,
IP2Bus_IntrEvent => user_IP2Bus_IntrEvent
);
 
------------------------------------------
-- connect internal signals
------------------------------------------
IP2BUS_DATA_MUX_PROC : process( ipif_Bus2IP_CS, user_IP2Bus_Data, intr_IP2Bus_Data ) is
begin
 
case ipif_Bus2IP_CS is
when "100000000" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
when "010000000" => ipif_IP2Bus_Data <= (others => '0');
when "001000000" => ipif_IP2Bus_Data <= intr_IP2Bus_Data;
when "000100000" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
when "000010000" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
when "000001000" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
when "000000100" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
when "000000010" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
when "000000001" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
when others => ipif_IP2Bus_Data <= (others => '0');
end case;
 
end process IP2BUS_DATA_MUX_PROC;
 
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck or rst_IP2Bus_WrAck or intr_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck or intr_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error or rst_IP2Bus_Error or intr_IP2Bus_Error;
 
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
 
end IMP;
/Release_1.0/sim/Makefile
0,0 → 1,72
#VCOM = /usr/local/bin/vcom
VCOMOPS = -explicit -check_synthesis -2002 -quiet
#MAKEFLAGS = --silent
HDL_DIR = ../rtl/vhdl/
 
 
##
# avs_aes hdl files
##
CORE_SRC =$(HDL_DIR)/core/mod_sim_exp_pkg.vhd \
$(HDL_DIR)/core/adder_block.vhd \
$(HDL_DIR)/core/adder_n.vhd \
$(HDL_DIR)/core/autorun_cntrl.vhd \
$(HDL_DIR)/core/cell_1b_adder.vhd \
$(HDL_DIR)/core/cell_1b_mux.vhd \
$(HDL_DIR)/core/cell_1b.vhd \
$(HDL_DIR)/core/counter_sync.vhd \
$(HDL_DIR)/core/d_flip_flop.vhd \
$(HDL_DIR)/core/fifo_primitive.vhd \
$(HDL_DIR)/core/first_stage.vhd \
$(HDL_DIR)/core/last_stage.vhd \
$(HDL_DIR)/core/modulus_ram.vhd \
$(HDL_DIR)/core/mont_ctrl.vhd \
$(HDL_DIR)/core/mont_mult_sys_pipeline.vhd \
$(HDL_DIR)/core/mod_sim_exp_core.vhd \
$(HDL_DIR)/core/operand_dp.vhd \
$(HDL_DIR)/core/operand_mem.vhd \
$(HDL_DIR)/core/operand_ram.vhd \
$(HDL_DIR)/core/operands_sp.vhd \
$(HDL_DIR)/core/register_1b.vhd \
$(HDL_DIR)/core/register_n.vhd \
$(HDL_DIR)/core/standard_cell_block.vhd \
$(HDL_DIR)/core/standard_stage.vhd \
$(HDL_DIR)/core/stepping_logic.vhd \
$(HDL_DIR)/core/systolic_pipeline.vhd \
$(HDL_DIR)/core/x_shift_reg.vhd \
 
 
##
# Testbench HDL file
##
TB_SRC_DIR = ../bench/vhdl/
TB_SRC = $(TB_SRC_DIR)mod_sim_exp_core_tb.vhd
 
#######################################
all: mod_sim_exp
 
clean:
rm -rf *_lib
 
mod_sim_exp_lib:
vlib mod_sim_exp
 
work_lib:
vlib work
 
libs: mod_sim_exp work_lib
 
mod_sim_exp_com: mod_sim_exp_lib
#echo --
#echo building Modular Exponentiation Core
#echo --
vcom $(VCOMOPS) -work mod_sim_exp $(CORE_SRC)
 
mod_sim_exp_tb: work_lib
#echo --
#echo building Modular Exponentiation Core Testbench
#echo --
vcom $(VCOMOPS) -work work $(TB_SRC)
 
mod_sim_exp: mod_sim_exp_com mod_sim_exp_tb
vsim -c -do mod_sim_exp.do -lib work mod_sim_exp_core_tb
Release_1.0/sim/out Property changes : Added: svn:ignore ## -0,0 +1 ## +sim_output.txt Index: Release_1.0/sim/mod_sim_exp.do =================================================================== --- Release_1.0/sim/mod_sim_exp.do (nonexistent) +++ Release_1.0/sim/mod_sim_exp.do (revision 100) @@ -0,0 +1,2 @@ +nolog -all +run -all \ No newline at end of file Index: Release_1.0/sim/src/sim_input.txt =================================================================== --- Release_1.0/sim/src/sim_input.txt (nonexistent) +++ Release_1.0/sim/src/sim_input.txt (revision 100) @@ -0,0 +1,44 @@ +-- input generator program +-- generates test values per bit input pair +-- base_width, exp_width, g0, g1, e0, e1, m, R^2, result +512 +32 +de0bbade38204e63359a46e672a8d0a2fd5300692ab48f9ef732f5c3fa212b90c98229bbb79bece734a622154c904dce9a0f53d4a88b3e558ef7612f6694ce75 +2e5d3fea7d9d0d33ac553eecd5c3f27a310115d283e49377820195c8e67781b6f112a625b14b747fa4cc13d06eba0917246c775f5c732865701ae9349ea8729c +64150a6d +8593f0d7 +18f204fe6846aeb6f58174d57a3372363c0d9fcfaa3dc18b1eff7e89bf7678636580d17dd84a873b14b9c0e1680bbdc87647f3c382902d2f58d2754b39bca875 +098eb081ecfa53f3f90e7dbf1e10b6e29ee45d6b02bff85403b335c0c6d5e1ab6eec5d670afb95713ed15f9723e5faedd6a42d95effafa771cb0c72d3a73c905 +068bce0fed3d2cda68f16fa939fd89e1a777c1e359967090ca050e9e855f4c1e08f7d1158d16b7b130be7731ef8a962b61307a5ce65e3c2687c76b0fbea16b6e +14026cdda1794a94d7fa3cc76c69f6e43b5da0597c4040c6eb5cf65f677cac9bd85b08af0c998241ed365decd2d1cf2a62ccb6138a409224f7f03184d2cd77b5 +047d6c7653eca32d15971be88eba38526fea6bbb9f991ad6c8d9ede11bb11dc888444923c5732d57d31a4aeea397179007927ba14cfdd1078664dcbbfcc3aaf4 +00a84956047b71ed15148f0fc4be161c3fe4fe03650dff8e239982c0ebbbdbfbea2087f0c2f725a023e1e568e56e980e36524cbc29190b698bcb62534aa47c3b +0ae33423c12184905fb44e34ae955ac5a502c9983910135ae22ae1f477c7e4532cf1134dde48ccc4126124f91085d64d6106c503b6e71b0ce5333d679b0f016f +-- base_width, exp_width, g0, g1, e0, e1, m, R^2, result +1024 +16 +895f783fab56a353b58a8c4316eacf3012c77e6fbfdb4be7ed3cd27fc1c72a98f7733050ae2a4bd8c2b356f3f81de6f56258f69355b9321117b905723db3fe533ff94c12502b145c53e61608834634eae18e60c5b991b9f8d71b2d971cbe5ac9e09f4814addab421efdcc2870d2c92c87003fcff55ccba1d4f22f5ab90950fb0 +2a46626cf17c40bc08e57582f9852ad12cf0ee16f2440678d35a31147278a27658a66182b41c8327a559d058a9e9df5a55fe9eeccd16fd651c2d7f13a9942e7418052b4ae1b98f8ca3f3e828532a453289bd47b363738f866debf04222abeecac1e11f980b6f115f097f4540aa7735b993f17f55083caeb6a80f80d092c59d2f +7c1f +5eb8 +20f8be80ba9b4c7ca011f74c2d41581f0036d233b5e8e58b6dd5ca6db0625d764b927a43fe78844090c6843f29a331b76f8ece93e7e313eccb9bcb6ed2330923899aae43a0fd2430cb6772793755e74862e61e2ac376cfab9d61827e646421b28e9e0e2aca4625731aebbb69ea37e0fa859e499b8a186c8ee6196954170eb807 +06412c26297124ba58188bc306fa67d5e2349d33c677cb3701084ab808780e2d89f5d0b912e4866f37f4fec043a08c1991c2ef1a4d9f81b6bd6e8449cf2dfa510a0417db84ec15bea71c17b483852b918137926002c232d2adfd304c7a1beef79b83544bc405d714a10e1b2ed02e33cfbf25b0dffdda16e76d92e84d778dcc27 +1932ca7ae5c0e8979f823ceac3369726fe80409606a1b92fff2777002d4f71c3eefea8240ab4623c0a926245dc89a3fbf31859f4a8ca74866ebd6ff8409ac0073cc53c26991402aa702bdeaf7ca6ad054bb52cd4a7c0524eb2556e8b4143141e19ad9cd47814f9da438de01a9878d92658abfcbf39550817b54e1eb35e98f7cf +1563cce47758b785cfd5bf169f156b4e4328b02221faa51d65cc5e819abd176948d3262a5f54a3dd960d1aeaba079bb8ad3d9926d0b5f3ff3dada08f6219e932ff858e754ef7ccc3f3b63cb0be8d2b346ef8054ed96a1bfcb6ab110f52d2c601f4cca7149a7a3ae60aae54611266844562f93a152656d6c857bb8e41209e2904 +19d524c74c54446433fd52e430bc5ab765afcdff9f13cfe2b81958baf4c1804e6f0ded2b6e39a37d59a9d6f9f833c6225920c7700a06f308074df8027b47ee5b4e0e3a96bcf2f44f74e5ff4b9eda59538c88e9e86f321f28584be5a4738eb56925cd464b980cbca2f78c2d456fc9c46bb58d34425dfa4b12ad486a7b79982e7f +1544b14914333391b50ddc809fdd3b372f607292a3677ac566448683b734ba6feecb8ae791e6ba01dfdf37441676459f27343e727c5ce647e4e5f3fd5cea23e891525229306db57a0df7abf72d167a09cf3daf35e24628a39cd85b824dd548c516a36586e77a844677f3889a58ff57e80734c70d37e403eb0bc122825c36585c +1324646bfb0bad60a82843ae9b47e64d4fb298550061b01755aed16ba0448afc9cac7557640de2e8eda59e5c9e29483ed5181d997d9f73e8edcfd671a724cc1f2ec976ed97b392148d8f1156f0cb4cab35a2b378c7a63b539daa0588260aa6fb2ab3f8ad497c96305a0fa081ee6ab4bb7067d3ea85c6455bf6f9af37deb38eb3 +-- base_width, exp_width, g0, g1, e0, e1, m, R^2, result +1536 +16 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Release_1.0 Property changes : Added: svn:ignore ## -0,0 +1 ## +.project

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