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  • This comparison shows the changes necessary to convert path
    /mod_sim_exp/trunk/doc/src
    from Rev 88 to Rev 92
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Rev 88 → Rev 92

/axi_interface.tex
198,5 → 198,4
supported due to the structure of the RAM.
 
\section{Handling interrupts}
When the embedded processor receives an interrupt signal from this core, it is up to the controlling software to
determine the source of the interrupt by reading out the interrupt flag of the control register.
When the embedded processor receives an interrupt signal from this core, it is up to the controlling software to determine the source of the interrupt by reading out the interrupt flags of the control register. After handling the interrupt, the appropriate flag must be cleared by user. A reset or core start operation also resets the flags. The interrupt signal is high level sensitive.
/acknowl.tex
1,7 → 1,7
\chapter*{Acknowledgments}
\addcontentsline{toc}{chapter}{Acknowledgments}
This project is maintained by the DraMCo research group\footnote{\url{http://www.dramco.be/}} of KAHO Sint-Lieven\footnote{\url{http://www.kahosl.be/}}, part of the KU Leuven association\footnote{\url{http://associatie.kuleuven.be/}}.
The base design for this IP core is written by Geoffrey Ottoy, member of the DraMCo research group. Further adjustments have been made by Jonas De Craene
The base design for this IP core is written by Geoffrey Ottoy, member of the DraMCo research group. Further adjustments have been made by Jonas De Craene.
 
%\addtocontents{toc}{Document Revision History}
 
26,6 → 26,8
\hline
1.4 & April 2013 & JDC & Revision of newly added AXI4-Lite interface\\
\hline
& July 2013 & JDC & Minor update of AXI4-Lite interface interrupt structure\\
\hline
\end{tabular}%
 
\section*{Author info}

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