URL
https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk
Subversion Repositories mod_sim_exp
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- This comparison shows the changes necessary to convert path
/mod_sim_exp/trunk/rtl/vhdl/core
- from Rev 31 to Rev 30
- ↔ Reverse comparison
Rev 31 → Rev 30
/sys_first_cell_logic.vhd
File deleted
/sys_pipeline.vhd
155,20 → 155,25
|
-- first cell logic |
-------------------- |
first_stage : sys_first_cell_logic |
port map ( |
m0 => m_i(0), |
y0 => y_i(0), |
my_cout => my_cin_stage(0), |
xi => xi, |
xout => xin_stage(0), |
qout => qin_stage(0), |
cout => cin_stage(0), |
a_0 => a_0_stage(0), |
red_cout => red_cin_stage(0) |
my0 <= m_i(0) xor y_i(0); -- m0 + y0 |
-- stage 0 connections |
my_cin_stage(0) <= m_i(0) and y_i(0); -- m0 + y0 carry |
xin_stage(0) <= xi; |
qin_stage(0) <= (xi and y_i(0)) xor a_0_stage(0); |
cin_stage(0) <= my0_mux_result and a_0_stage(0); |
red_cin_stage(0) <= '1'; -- add 1 for 2s complement |
start_stage(0) <= start; |
|
my0_mux : cell_1b_mux |
port map( |
my => my0, |
m => m_i(0), |
y => y_i(0), |
x => xin_stage(0), |
q => qin_stage(0), |
result => my0_mux_result |
); |
|
start_stage(0) <= start; |
next_x <= done_stage(0); |
|
-- last cell logic |
/mod_sim_exp_pkg.vhd
713,26 → 713,6
end component sys_last_cell_logic; |
|
-------------------------------------------------------------------- |
-- sys_first_cell_logic |
-------------------------------------------------------------------- |
-- logic needed as the first piece in the systolic array pipeline |
-- calculates the first my_cout and generates q signal |
-- |
component sys_first_cell_logic is |
port ( |
m0 : in std_logic; -- lsb from m operand |
y0 : in std_logic; -- lsb from y operand |
my_cout : out std_logic; -- my_cin for first stage |
xi : in std_logic; -- xi operand input |
xout : out std_logic; -- xin for first stage |
qout : out std_logic; -- qin for first stage |
cout : out std_logic; -- cin for first stage |
a_0 : in std_logic; -- a_0 from first stage |
red_cout : out std_logic -- red_cin for first stage |
); |
end component sys_first_cell_logic; |
|
-------------------------------------------------------------------- |
-- sys_pipeline |
-------------------------------------------------------------------- |
-- the pipelined systolic array for a montgommery multiplier |