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URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

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  • This comparison shows the changes necessary to convert path
    /mod_sim_exp/trunk/rtl/vhdl/interface/plb
    from Rev 65 to Rev 45
    Reverse comparison

Rev 65 → Rev 45

/user_logic.vhd
100,7 → 100,6
C_NR_STAGES_TOTAL : integer := 96;
C_NR_STAGES_LOW : integer := 32;
C_SPLIT_PIPELINE : boolean := true;
C_FIFO_DEPTH : integer := 32;
-- ADD USER GENERICS ABOVE THIS LINE ---------------
 
-- DO NOT EDIT BELOW THIS LINE ---------------------
184,7 → 183,6
signal core_x_sel_single : std_logic_vector(1 downto 0);
signal core_y_sel_single : std_logic_vector(1 downto 0);
signal core_flags : std_logic_vector(15 downto 0);
signal core_modulus_sel : std_logic_vector(0 downto 0);
 
------------------------------------------------------------------
-- Signals for multiplier core memory space
386,14 → 384,12
------------------------------------------
-- Map slv_reg0 bits to core control signals
------------------------------------------
core_start <= slv_reg0(8);
core_exp_m <= slv_reg0(9);
core_p_sel <= slv_reg0(0 to 1);
core_dest_op_single <= slv_reg0(2 to 3);
core_x_sel_single <= slv_reg0(4 to 5);
core_y_sel_single <= slv_reg0(6 to 7);
core_start <= slv_reg0(8);
core_exp_m <= slv_reg0(9);
core_modulus_sel <= slv_reg0(10 to 10);
 
------------------------------------------
-- Multiplier core instance
403,10 → 399,7
C_NR_BITS_TOTAL => C_NR_BITS_TOTAL,
C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL,
C_NR_STAGES_LOW => C_NR_STAGES_LOW,
C_SPLIT_PIPELINE => C_SPLIT_PIPELINE,
C_NR_OP => 4,
C_NR_M => 2,
C_FIFO_DEPTH => C_FIFO_DEPTH
C_SPLIT_PIPELINE => C_SPLIT_PIPELINE
)
port map(
clk => Bus2IP_Clk,
430,8 → 423,7
y_sel_single => core_y_sel_single,
dest_op_single => core_dest_op_single,
p_sel => core_p_sel,
calc_time => calc_time,
modulus_sel => core_modulus_sel
calc_time => calc_time
);
 
 
/mod_sim_exp_IPcore.vhd
162,7 → 162,6
C_NR_STAGES_TOTAL : integer := 96;
C_NR_STAGES_LOW : integer := 32;
C_SPLIT_PIPELINE : boolean := true;
C_FIFO_DEPTH : integer := 32;
-- ADD USER GENERICS ABOVE THIS LINE ---------------
 
-- DO NOT EDIT BELOW THIS LINE ---------------------
578,7 → 577,6
C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL,
C_NR_STAGES_LOW => C_NR_STAGES_LOW,
C_SPLIT_PIPELINE => C_SPLIT_PIPELINE,
C_FIFO_DEPTH => C_FIFO_DEPTH,
-- MAP USER GENERICS ABOVE THIS LINE ---------------
 
C_SLV_AWIDTH => USER_SLV_AWIDTH,

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