URL
https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk
Subversion Repositories mod_sim_exp
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- This comparison shows the changes necessary to convert path
/mod_sim_exp/trunk/rtl/vhdl
- from Rev 12 to Rev 13
- ↔ Reverse comparison
Rev 12 → Rev 13
/core/adder_n.vhd
55,6 → 55,7
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-- n-bit adder using adder blocks. works in stages, to prevent large |
-- carry propagation |
-- Result avaiable after (width/block_width) clock cycles |
entity adder_n is |
generic ( |
width : integer := 1536; -- adder operands width |
77,9 → 78,13
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architecture Structural of adder_n is |
constant nr_of_blocks : integer := width/block_width; -- number of blocks/stages in the adder |
signal carry : std_logic_vector(nr_of_blocks downto 0); -- array for the carry bits |
signal carry : std_logic_vector(nr_of_blocks downto 0); -- vector for the carry bits |
begin |
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-- report failure if width is not dividable by block_width |
assert (width mod block_width)=0 |
report "adder_n: width is not divisible by block_width!!" severity failure; |
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-- carry in |
carry(0) <= cin; |
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