URL
https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk
Subversion Repositories mod_sim_exp
Compare Revisions
- This comparison shows the changes necessary to convert path
/mod_sim_exp/trunk/sim
- from Rev 65 to Rev 70
- ↔ Reverse comparison
Rev 65 → Rev 70
/mod_sim_exp.do
1,2 → 1,5
nolog -all |
set StdArithNoWarnings 1 |
run 5 ns; |
set StdArithNoWarnings 0 |
run -all |
out
Property changes :
Modified: svn:ignore
## -1 +1,3 ##
sim_output.txt
+debug.txt
+sim_mult_output.txt
Index: Makefile
===================================================================
--- Makefile (revision 65)
+++ Makefile (revision 70)
@@ -1,11 +1,8 @@
#VCOM = /usr/local/bin/vcom
VCOMOPS = -explicit -check_synthesis -2002 -quiet
-VLOGOPS = -vopt -nocovercells
#MAKEFLAGS = --silent
HDL_DIR = ../rtl/vhdl/
-VER_DIR = ../rtl/verilog/
-
##
# avs_aes hdl files
##
@@ -13,6 +10,12 @@
$(HDL_DIR)/core/mod_sim_exp_pkg.vhd \
$(HDL_DIR)/ram/dpram_generic.vhd \
$(HDL_DIR)/ram/tdpram_generic.vhd \
+ $(HDL_DIR)/ram/dpram_asym.vhd \
+ $(HDL_DIR)/ram/dpramblock_asym.vhd \
+ $(HDL_DIR)/core/modulus_ram_asym.vhd \
+ $(HDL_DIR)/ram/tdpram_asym.vhd \
+ $(HDL_DIR)/ram/tdpramblock_asym.vhd \
+ $(HDL_DIR)/core/operand_ram_asym.vhd \
$(HDL_DIR)/core/fifo_generic.vhd \
$(HDL_DIR)/core/modulus_ram_gen.vhd \
$(HDL_DIR)/core/operand_ram_gen.vhd \
@@ -42,11 +45,6 @@
$(HDL_DIR)/core/sys_pipeline.vhd \
$(HDL_DIR)/core/mont_multiplier.vhd \
-VER_SRC =$(VER_DIR)generic_spram.v \
- $(VER_DIR)generic_dpram.v \
- $(VER_DIR)generic_tpram.v \
- $(VER_DIR)generic_fifo_sc_a.v \
- $(VER_DIR)generic_fifo_sc_b.v \
##
# Testbench HDL file
@@ -72,7 +70,6 @@
#echo --
#echo building Modular Exponentiation Core
#echo --
- #vlog $(VLOGOPS) -work mod_sim_exp $(VER_SRC)
vcom $(VCOMOPS) -work mod_sim_exp $(CORE_SRC)
#echo Done!
.
Property changes :
Added: svn:ignore
## -0,0 +1,2 ##
+mod_sim_exp
+work