URL
https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk
Subversion Repositories mod_sim_exp
Compare Revisions
- This comparison shows the changes necessary to convert path
/mod_sim_exp/trunk/sim
- from Rev 70 to Rev 65
- ↔ Reverse comparison
Rev 70 → Rev 65
/Makefile
1,8 → 1,11
#VCOM = /usr/local/bin/vcom |
VCOMOPS = -explicit -check_synthesis -2002 -quiet |
VLOGOPS = -vopt -nocovercells |
#MAKEFLAGS = --silent |
HDL_DIR = ../rtl/vhdl/ |
VER_DIR = ../rtl/verilog/ |
|
|
## |
# avs_aes hdl files |
## |
10,12 → 13,6
$(HDL_DIR)/core/mod_sim_exp_pkg.vhd \ |
$(HDL_DIR)/ram/dpram_generic.vhd \ |
$(HDL_DIR)/ram/tdpram_generic.vhd \ |
$(HDL_DIR)/ram/dpram_asym.vhd \ |
$(HDL_DIR)/ram/dpramblock_asym.vhd \ |
$(HDL_DIR)/core/modulus_ram_asym.vhd \ |
$(HDL_DIR)/ram/tdpram_asym.vhd \ |
$(HDL_DIR)/ram/tdpramblock_asym.vhd \ |
$(HDL_DIR)/core/operand_ram_asym.vhd \ |
$(HDL_DIR)/core/fifo_generic.vhd \ |
$(HDL_DIR)/core/modulus_ram_gen.vhd \ |
$(HDL_DIR)/core/operand_ram_gen.vhd \ |
45,6 → 42,11
$(HDL_DIR)/core/sys_pipeline.vhd \ |
$(HDL_DIR)/core/mont_multiplier.vhd \ |
|
VER_SRC =$(VER_DIR)generic_spram.v \ |
$(VER_DIR)generic_dpram.v \ |
$(VER_DIR)generic_tpram.v \ |
$(VER_DIR)generic_fifo_sc_a.v \ |
$(VER_DIR)generic_fifo_sc_b.v \ |
|
## |
# Testbench HDL file |
70,6 → 72,7
#echo -- |
#echo building Modular Exponentiation Core |
#echo -- |
#vlog $(VLOGOPS) -work mod_sim_exp $(VER_SRC) |
vcom $(VCOMOPS) -work mod_sim_exp $(CORE_SRC) |
#echo Done! |
|
out
Property changes :
Modified: svn:ignore
## -1,3 +1 ##
sim_output.txt
-debug.txt
-sim_mult_output.txt
Index: mod_sim_exp.do
===================================================================
--- mod_sim_exp.do (revision 70)
+++ mod_sim_exp.do (revision 65)
@@ -1,5 +1,2 @@
nolog -all
-set StdArithNoWarnings 1
-run 5 ns;
-set StdArithNoWarnings 0
run -all
\ No newline at end of file
Index: .
===================================================================
--- . (revision 70)
+++ . (revision 65)
.
Property changes :
Deleted: svn:ignore
## -1,2 +0,0 ##
-mod_sim_exp
-work