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URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

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  • This comparison shows the changes necessary to convert path
    /mod_sim_exp/trunk
    from Rev 70 to Rev 69
    Reverse comparison

Rev 70 → Rev 69

/sim/Makefile
1,8 → 1,11
#VCOM = /usr/local/bin/vcom
VCOMOPS = -explicit -check_synthesis -2002 -quiet
VLOGOPS = -vopt -nocovercells
#MAKEFLAGS = --silent
HDL_DIR = ../rtl/vhdl/
VER_DIR = ../rtl/verilog/
 
 
##
# avs_aes hdl files
##
10,12 → 13,6
$(HDL_DIR)/core/mod_sim_exp_pkg.vhd \
$(HDL_DIR)/ram/dpram_generic.vhd \
$(HDL_DIR)/ram/tdpram_generic.vhd \
$(HDL_DIR)/ram/dpram_asym.vhd \
$(HDL_DIR)/ram/dpramblock_asym.vhd \
$(HDL_DIR)/core/modulus_ram_asym.vhd \
$(HDL_DIR)/ram/tdpram_asym.vhd \
$(HDL_DIR)/ram/tdpramblock_asym.vhd \
$(HDL_DIR)/core/operand_ram_asym.vhd \
$(HDL_DIR)/core/fifo_generic.vhd \
$(HDL_DIR)/core/modulus_ram_gen.vhd \
$(HDL_DIR)/core/operand_ram_gen.vhd \
45,6 → 42,11
$(HDL_DIR)/core/sys_pipeline.vhd \
$(HDL_DIR)/core/mont_multiplier.vhd \
 
VER_SRC =$(VER_DIR)generic_spram.v \
$(VER_DIR)generic_dpram.v \
$(VER_DIR)generic_tpram.v \
$(VER_DIR)generic_fifo_sc_a.v \
$(VER_DIR)generic_fifo_sc_b.v \
 
##
# Testbench HDL file
70,6 → 72,7
#echo --
#echo building Modular Exponentiation Core
#echo --
#vlog $(VLOGOPS) -work mod_sim_exp $(VER_SRC)
vcom $(VCOMOPS) -work mod_sim_exp $(CORE_SRC)
#echo Done!
 
sim/out Property changes : Modified: svn:ignore ## -1,3 +1 ## sim_output.txt -debug.txt -sim_mult_output.txt Index: sim/mod_sim_exp.do =================================================================== --- sim/mod_sim_exp.do (revision 70) +++ sim/mod_sim_exp.do (revision 69) @@ -1,5 +1,2 @@ nolog -all -set StdArithNoWarnings 1 -run 5 ns; -set StdArithNoWarnings 0 run -all \ No newline at end of file Index: sim =================================================================== --- sim (revision 70) +++ sim (revision 69)
sim Property changes : Deleted: svn:ignore ## -1,2 +0,0 ## -mod_sim_exp -work Index: bench/vhdl/mod_sim_exp_core_tb.vhd =================================================================== --- bench/vhdl/mod_sim_exp_core_tb.vhd (revision 70) +++ bench/vhdl/mod_sim_exp_core_tb.vhd (revision 69) @@ -75,12 +75,7 @@ constant C_NR_BITS_TOTAL : integer := 1536; constant C_NR_STAGES_TOTAL : integer := 96; constant C_NR_STAGES_LOW : integer := 32; - constant C_SPLIT_PIPELINE : boolean := true; - constant C_NR_OP : integer := 4; -- leave on 4 for simulation - constant C_NR_M : integer := 2; -- leave on 2 for simulation - constant C_FIFO_DEPTH : integer := 32; -- set to (maximum exponent width)/16 - constant C_MEM_STYLE : string := "generic"; -- xil_prim, generic, asym are valid options - constant C_DEVICE : string := "xilinx"; -- xilinx, altera are valid options + constant C_SPLIT_PIPELINE : boolean := true; -- extra calculated constants constant NR_BITS_LOW : integer := (C_NR_BITS_TOTAL/C_NR_STAGES_TOTAL)*C_NR_STAGES_LOW; @@ -559,12 +554,10 @@ for i in (exponent_width/16)-1 downto 0 loop core_fifo_din <= e1((i*16)+15 downto (i*16)) & e0((i*16)+15 downto (i*16)); wait until rising_edge(clk); - assert (core_fifo_full='0') - report "Fifo error, fifo full" severity failure; core_fifo_push <= '1'; wait until rising_edge(clk); assert (core_fifo_full='0' and core_fifo_nopush='0') - report "Fifo error, fifo nopush" severity failure; + report "Fifo error, full or nopush" severity failure; core_fifo_push <= '0'; wait until rising_edge(clk); end loop; @@ -678,12 +671,7 @@ C_NR_BITS_TOTAL => C_NR_BITS_TOTAL, C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL, C_NR_STAGES_LOW => C_NR_STAGES_LOW, - C_SPLIT_PIPELINE => C_SPLIT_PIPELINE, - C_NR_OP => C_NR_OP, - C_NR_M => C_NR_M, - C_FIFO_DEPTH => C_FIFO_DEPTH, - C_MEM_STYLE => C_MEM_STYLE, -- xil_prim, generic, asym are valid options - C_DEVICE => C_DEVICE -- xilinx, altera are valid options + C_SPLIT_PIPELINE => C_SPLIT_PIPELINE ) port map( clk => clk, @@ -707,8 +695,7 @@ y_sel_single => core_y_sel_single, dest_op_single => core_dest_op_single, p_sel => core_p_sel, - calc_time => calc_time, - modulus_sel => "0" + calc_time => calc_time ); end test;

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