OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /mod_sim_exp/trunk
    from Rev 74 to Rev 75
    ↔ Reverse comparison
  •

Rev 74 → Rev 75

/rtl/vhdl/core/mod_sim_exp_pkg.vhd
898,7 → 898,7
-- data interface (plb side)
data_in : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(31 downto 0);
rw_address : in std_logic_vector(log2(nr_op)+log2(width/32) downto 0);
rw_address : in std_logic_vector(8 downto 0);
write_enable : in std_logic;
-- operand interface (multiplier side)
op_sel : in std_logic_vector(log2(nr_op)-1 downto 0);
930,8 → 930,6
C_NR_STAGES_TOTAL : integer := 96;
C_NR_STAGES_LOW : integer := 32;
C_SPLIT_PIPELINE : boolean := true;
C_NR_OP : integer := 4;
C_NR_M : integer := 2;
C_FIFO_DEPTH : integer := 32;
C_MEM_STYLE : string := "generic"; -- xil_prim, generic, asym are valid options
C_DEVICE : string := "xilinx" -- xilinx, altera are valid options
942,7 → 940,7
-- operand memory interface (plb shared memory)
write_enable : in std_logic; -- write data to operand ram
data_in : in std_logic_vector (31 downto 0); -- operand ram data in
rw_address : in std_logic_vector (log2(C_NR_OP)+log2(C_NR_BITS_TOTAL/32) downto 0); -- operand ram address bus
rw_address : in std_logic_vector (8 downto 0); -- operand ram address bus
data_out : out std_logic_vector (31 downto 0); -- operand ram data out
collision : out std_logic; -- write collision
-- op_sel fifo interface
954,12 → 952,12
start : in std_logic; -- start multiplication/exponentiation
exp_m : in std_logic; -- single multiplication if low, exponentiation if high
ready : out std_logic; -- calculations done
x_sel_single : in std_logic_vector (log2(C_NR_OP)-1 downto 0); -- single multiplication x operand selection
y_sel_single : in std_logic_vector (log2(C_NR_OP)-1 downto 0); -- single multiplication y operand selection
dest_op_single : in std_logic_vector (log2(C_NR_OP)-1 downto 0); -- result destination operand selection
x_sel_single : in std_logic_vector (1 downto 0); -- single multiplication x operand selection
y_sel_single : in std_logic_vector (1 downto 0); -- single multiplication y operand selection
dest_op_single : in std_logic_vector (1 downto 0); -- result destination operand selection
p_sel : in std_logic_vector (1 downto 0); -- pipeline part selection
calc_time : out std_logic;
modulus_sel : in std_logic_vector(log2(C_NR_M)-1 downto 0) -- selects which modulus to use for multiplications
modulus_sel : in std_logic -- selects which modulus to use for multiplications
);
end component mod_sim_exp_core;
 
/rtl/vhdl/core/mod_sim_exp_core.vhd
66,7 → 66,7
C_NR_STAGES_LOW : integer := 32;
C_SPLIT_PIPELINE : boolean := true;
C_FIFO_DEPTH : integer := 32;
C_MEM_STYLE : string := "xil_prim"; -- xil_prim, generic, asym are valid options
C_MEM_STYLE : string := "asym"; -- xil_prim, generic, asym are valid options
C_DEVICE : string := "xilinx" -- xilinx, altera are valid options
);
port(
/rtl/vhdl/core/operand_mem.vhd
60,10 → 60,10
use mod_sim_exp.std_functions.all;
 
-- address structure:
-- bit: highest -> '1': modulus
-- '0': operands
-- bits: (highest-1)-log2(width/32) -> operand_in_sel in case of highest bit = '0'
-- modulus_in_sel in case of highest bit = '1'
-- bit: 8 -> '1': modulus
-- '0': operands
-- bits: 7-6 -> operand_in_sel in case of highest bit = '0'
-- modulus_in_sel in case of highest bit = '1'
-- bits: (log2(width/32)-1)-0 -> modulus_addr / operand_addr resp.
--
entity operand_mem is
80,7 → 80,7
-- data interface (plb side)
data_in : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(31 downto 0);
rw_address : in std_logic_vector(log2(nr_op)+log2(width/32) downto 0);
rw_address : in std_logic_vector(8 downto 0);
write_enable : in std_logic;
-- operand interface (multiplier side)
op_sel : in std_logic_vector(log2(nr_op)-1 downto 0);
119,14 → 119,14
-- map inputs
xy_addr_i <= rw_address(wordaddr_aw-1 downto 0);
m_addr_i <= rw_address(wordaddr_aw-1 downto 0);
operand_in_sel_i <= rw_address(total_aw-2 downto wordaddr_aw);
modulus_in_sel_i <= rw_address(wordaddr_aw+maddr_aw-1 downto wordaddr_aw);
operand_in_sel_i <= rw_address(7 downto 6);
modulus_in_sel_i <= rw_address(6 downto 6);
xy_data_i <= data_in;
m_data_i <= data_in;
-- select right memory with highest address bit
load_op <= write_enable when (rw_address(total_aw-1) = '0') else '0';
load_m <= write_enable when (rw_address(total_aw-1) = '1') else '0';
load_op <= write_enable when (rw_address(8) = '0') else '0';
load_m <= write_enable when (rw_address(8) = '1') else '0';
 
xil_prim_RAM : if mem_style="xil_prim" generate
-- xy operand storage

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.