URL
https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk
Subversion Repositories mod_sim_exp
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/mod_sim_exp/trunk
- from Rev 84 to Rev 83
- ↔ Reverse comparison
Rev 84 → Rev 83
/rtl/vhdl/core/mod_sim_exp_pkg.vhd
932,7 → 932,7
C_SPLIT_PIPELINE : boolean := true; |
C_FIFO_DEPTH : integer := 32; |
C_MEM_STYLE : string := "generic"; -- xil_prim, generic, asym are valid options |
C_FPGA_MAN : string := "xilinx" -- xilinx, altera are valid options |
C_DEVICE : string := "xilinx" -- xilinx, altera are valid options |
); |
port( |
clk : in std_logic; |
/rtl/vhdl/core/mod_sim_exp_core.vhd
67,7 → 67,7
C_SPLIT_PIPELINE : boolean := true; |
C_FIFO_DEPTH : integer := 32; |
C_MEM_STYLE : string := "asym"; -- xil_prim, generic, asym are valid options |
C_FPGA_MAN : string := "xilinx" -- xilinx, altera are valid options |
C_DEVICE : string := "xilinx" -- xilinx, altera are valid options |
); |
port( |
clk : in std_logic; |
122,12 → 122,7
signal fifo_nopop : std_logic; |
signal fifo_dout : std_logic_vector(31 downto 0); |
begin |
-- check the parameters |
assert (C_MEM_STYLE="xil_prim" or C_MEM_STYLE="generic" or C_MEM_STYLE="asym") |
report "C_MEM_STYLE incorrect!, it must be one of these: xil_prim, generic or asym" severity failure; |
assert (C_FPGA_MAN="xilinx" or C_FPGA_MAN="altera") |
report "C_FPGA_MAN incorrect!, it must be one of these: xilinx or altera" severity failure; |
|
|
-- The actual multiplier |
the_multiplier : mont_multiplier |
generic map( |
155,7 → 150,7
nr_op => nr_op, |
nr_m => nr_m, |
mem_style => C_MEM_STYLE, |
device => C_FPGA_MAN |
device => C_DEVICE |
) |
port map( |
data_in => data_in, |
/rtl/vhdl/interface/axi/msec_ipcore_axilite.vhd
File deleted
\ No newline at end of file
/rtl/vhdl/interface/axi/axi_lite_slave.vhd
0,0 → 1,446
------------------------------------------------------------------------------ |
-- axi_lite_test.vhd - entity/architecture pair |
------------------------------------------------------------------------------ |
-- IMPORTANT: |
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS. |
-- |
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED. |
-- |
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW |
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION |
-- OF THE USER_LOGIC ENTITY. |
------------------------------------------------------------------------------ |
-- |
-- *************************************************************************** |
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. ** |
-- ** ** |
-- ** Xilinx, Inc. ** |
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" ** |
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND ** |
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, ** |
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, ** |
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION ** |
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, ** |
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE ** |
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY ** |
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE ** |
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR ** |
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF ** |
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ** |
-- ** FOR A PARTICULAR PURPOSE. ** |
-- ** ** |
-- *************************************************************************** |
-- |
------------------------------------------------------------------------------ |
-- Filename: axi_lite_test.vhd |
-- Version: 1.00.a |
-- Description: Top level design, instantiates library components and user logic. |
-- Date: Mon Mar 11 15:48:39 2013 (by Create and Import Peripheral Wizard) |
-- VHDL Standard: VHDL'93 |
------------------------------------------------------------------------------ |
-- Naming Conventions: |
-- active low signals: "*_n" |
-- clock signals: "clk", "clk_div#", "clk_#x" |
-- reset signals: "rst", "rst_n" |
-- generics: "C_*" |
-- user defined types: "*_TYPE" |
-- state machine next state: "*_ns" |
-- state machine current state: "*_cs" |
-- combinatorial signals: "*_com" |
-- pipelined or register delay signals: "*_d#" |
-- counter signals: "*cnt*" |
-- clock enable signals: "*_ce" |
-- internal version of output port: "*_i" |
-- device pins: "*_pin" |
-- ports: "- Names begin with Uppercase" |
-- processes: "*_PROCESS" |
-- component instantiations: "<ENTITY_>I_<#|FUNC>" |
------------------------------------------------------------------------------ |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_arith.all; |
use ieee.std_logic_unsigned.all; |
|
library mod_sim_exp; |
use mod_sim_exp.mod_sim_exp_pkg; |
|
------------------------------------------------------------------------------ |
-- Entity section |
------------------------------------------------------------------------------ |
-- Definition of Generics: |
-- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width |
-- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width |
-- C_S_AXI_MIN_SIZE -- AXI4LITE slave: Min Size |
-- C_USE_WSTRB -- AXI4LITE slave: Write Strobe |
-- C_DPHASE_TIMEOUT -- AXI4LITE slave: Data Phase Timeout |
-- C_BASEADDR -- AXI4LITE slave: base address |
-- C_HIGHADDR -- AXI4LITE slave: high address |
-- C_FAMILY -- FPGA Family |
-- C_NUM_REG -- Number of software accessible registers |
-- C_NUM_MEM -- Number of address-ranges |
-- C_SLV_AWIDTH -- Slave interface address bus width |
-- C_SLV_DWIDTH -- Slave interface data bus width |
-- |
-- Definition of Ports: |
-- S_AXI_ACLK -- AXI4LITE slave: Clock |
-- S_AXI_ARESETN -- AXI4LITE slave: Reset |
-- S_AXI_AWADDR -- AXI4LITE slave: Write address |
-- S_AXI_AWVALID -- AXI4LITE slave: Write address valid |
-- S_AXI_WDATA -- AXI4LITE slave: Write data |
-- S_AXI_WSTRB -- AXI4LITE slave: Write strobe |
-- S_AXI_WVALID -- AXI4LITE slave: Write data valid |
-- S_AXI_BREADY -- AXI4LITE slave: Response ready |
-- S_AXI_ARADDR -- AXI4LITE slave: Read address |
-- S_AXI_ARVALID -- AXI4LITE slave: Read address valid |
-- S_AXI_RREADY -- AXI4LITE slave: Read data ready |
-- S_AXI_ARREADY -- AXI4LITE slave: read addres ready |
-- S_AXI_RDATA -- AXI4LITE slave: Read data |
-- S_AXI_RRESP -- AXI4LITE slave: Read data response |
-- S_AXI_RVALID -- AXI4LITE slave: Read data valid |
-- S_AXI_WREADY -- AXI4LITE slave: Write data ready |
-- S_AXI_BRESP -- AXI4LITE slave: Response |
-- S_AXI_BVALID -- AXI4LITE slave: Resonse valid |
-- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready |
------------------------------------------------------------------------------ |
|
entity axi_lite_slave is |
generic |
( |
-- ADD USER GENERICS BELOW THIS LINE --------------- |
--USER generics added here |
-- Multiplier parameters |
C_NR_BITS_TOTAL : integer := 1536; |
C_NR_STAGES_TOTAL : integer := 96; |
C_NR_STAGES_LOW : integer := 32; |
C_SPLIT_PIPELINE : boolean := true; |
C_FIFO_DEPTH : integer := 32; |
C_MEM_STYLE : string := "asym"; -- xil_prim, generic, asym are valid options |
C_DEVICE : string := "xilinx"; -- xilinx, altera are valid options |
|
-- ADD USER GENERICS ABOVE THIS LINE --------------- |
|
-- DO NOT EDIT BELOW THIS LINE --------------------- |
-- Bus protocol parameters, do not add to or delete |
C_S_AXI_DATA_WIDTH : integer := 32; |
C_S_AXI_ADDR_WIDTH : integer := 32; |
C_BASEADDR : std_logic_vector := X"FFFFFFFF"; |
C_HIGHADDR : std_logic_vector := X"00000000" |
-- DO NOT EDIT ABOVE THIS LINE --------------------- |
); |
port |
( |
--USER ports |
calc_time : out std_logic; |
IntrEvent : out std_logic; |
------------------------- |
-- AXI4lite interface |
------------------------- |
--- Global signals |
S_AXI_ACLK : in std_logic; |
S_AXI_ARESETN : in std_logic; |
--- Write address channel |
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); |
S_AXI_AWVALID : in std_logic; |
S_AXI_AWREADY : out std_logic; |
--- Write data channel |
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); |
S_AXI_WVALID : in std_logic; |
S_AXI_WREADY : out std_logic; |
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); |
--- Write response channel |
S_AXI_BVALID : out std_logic; |
S_AXI_BREADY : in std_logic; |
S_AXI_BRESP : out std_logic_vector(1 downto 0); |
--- Read address channel |
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); |
S_AXI_ARVALID : in std_logic; |
S_AXI_ARREADY : out std_logic; |
--- Read data channel |
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); |
S_AXI_RVALID : out std_logic; |
S_AXI_RREADY : in std_logic; |
S_AXI_RRESP : out std_logic_vector(1 downto 0) |
); |
|
attribute MAX_FANOUT : string; |
attribute SIGIS : string; |
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000"; |
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000"; |
attribute SIGIS of S_AXI_ACLK : signal is "Clk"; |
attribute SIGIS of S_AXI_ARESETN : signal is "Rst"; |
end entity axi_lite_slave; |
|
------------------------------------------------------------------------------ |
-- Architecture section |
------------------------------------------------------------------------------ |
|
architecture IMP of axi_lite_slave is |
type axi_states is (addr_wait, read_state, write_state, response_state); |
signal state : axi_states; |
|
signal address : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); |
signal reset : std_logic; |
|
|
|
-- selection signals |
signal cs_array : std_logic_vector(6 downto 0); |
signal core_selected : std_logic; |
signal slv_reg_selected : std_logic; |
signal op_mem_selected : std_logic; |
signal op_sel : std_logic_vector(1 downto 0); |
signal MNO_sel : std_logic; |
|
-- slave register signals |
signal slv_reg : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); |
signal slv_reg_write_enable : std_logic; |
signal load_flags : std_logic; |
|
-- core interface signeals |
signal write_enable : std_logic; |
signal core_write_enable : std_logic; |
signal core_fifo_push : std_logic; |
signal core_data_out : std_logic_vector(31 downto 0); |
signal core_rw_address : std_logic_vector(8 downto 0); |
|
------------------------------------------------------------------ |
-- Signals for multiplier core interrupt |
------------------------------------------------------------------ |
signal core_interrupt : std_logic; |
signal core_fifo_full : std_logic; |
signal core_fifo_nopush : std_logic; |
signal core_ready : std_logic; |
signal core_mem_collision : std_logic; |
|
------------------------------------------------------------------ |
-- Signals for multiplier core control |
------------------------------------------------------------------ |
signal core_start : std_logic; |
signal core_exp_m : std_logic; |
signal core_p_sel : std_logic_vector(1 downto 0); |
signal core_dest_op_single : std_logic_vector(1 downto 0); |
signal core_x_sel_single : std_logic_vector(1 downto 0); |
signal core_y_sel_single : std_logic_vector(1 downto 0); |
signal core_flags : std_logic_vector(15 downto 0); |
signal core_modulus_sel : std_logic; |
|
begin |
-- unused signals |
S_AXI_BRESP <= "00"; |
S_AXI_RRESP <= "00"; |
|
-- axi-lite slave state machine |
axi_slave_states : process (S_AXI_ACLK) |
begin |
if rising_edge(S_AXI_ACLK) then |
if S_AXI_ARESETN='0' then -- slave reset state |
S_AXI_RVALID <= '0'; |
S_AXI_BVALID <= '0'; |
S_AXI_ARREADY <= '0'; |
S_AXI_WREADY <= '0'; |
S_AXI_AWREADY <= '0'; |
state <= addr_wait; |
address <= (others=>'0'); |
write_enable <= '0'; |
else |
case state is |
when addr_wait => |
-- wait for a read or write address and latch it in |
if S_AXI_ARVALID = '1' then -- read |
state <= read_state; |
address <= S_AXI_ARADDR; |
S_AXI_ARREADY <= '1'; |
elsif S_AXI_AWVALID = '1' then -- write |
state <= write_state; |
address <= S_AXI_AWADDR; |
S_AXI_AWREADY <= '1'; |
else |
state <= addr_wait; |
end if; |
|
when read_state => |
-- place correct data on bus and generate valid pulse |
S_AXI_ARREADY <= '0'; |
S_AXI_RVALID <= '1'; |
state <= response_state; |
|
when write_state => |
-- generate a write pulse |
S_AXI_AWREADY <= '0'; |
if (S_AXI_WVALID = '1') then |
write_enable <= '1'; |
S_AXI_WREADY <= '1'; |
S_AXI_BVALID <= '1'; |
state <= response_state; |
else |
state <= write_state; |
end if; |
|
when response_state => |
write_enable <= '0'; |
S_AXI_WREADY <= '0'; |
-- wait for response from master |
if (S_AXI_RREADY = '1') or (S_AXI_BREADY = '1') then |
S_AXI_RVALID <= '0'; |
S_AXI_BVALID <= '0'; |
state <= addr_wait; |
else |
state <= response_state; |
end if; |
|
end case; |
end if; |
end if; |
end process; |
|
-- place correct data on the bus |
S_AXI_RDATA <= core_data_out when (core_selected='1') and (op_mem_selected='1') else |
slv_reg when (core_selected='1') and (slv_reg_selected='1') else |
(others=>'0'); |
|
-- SLAVE REG MAPPING |
-- core control signals |
reset <= not S_AXI_ARESETN; |
core_p_sel <= slv_reg(1 downto 0); |
core_dest_op_single <= slv_reg(3 downto 2); |
core_x_sel_single <= slv_reg(5 downto 4); |
core_y_sel_single <= slv_reg(7 downto 6); |
core_start <= slv_reg(8); |
core_exp_m <= slv_reg(9); |
core_modulus_sel <= slv_reg(10); |
|
-- implement slave register |
SLAVE_REG_WRITE_PROC : process( S_AXI_ACLK ) is |
begin |
if rising_edge(S_AXI_ACLK) then |
if S_AXI_ARESETN = '0' then |
slv_reg <= (others => '0'); |
elsif load_flags = '1' then |
slv_reg <= core_flags & slv_reg(15 downto 0) ; |
else |
if (slv_reg_write_enable='1') then |
slv_reg <= S_AXI_WDATA(31 downto 0); |
end if; |
end if; |
end if; |
end process SLAVE_REG_WRITE_PROC; |
|
-- interrupt and flags |
core_interrupt <= core_ready or core_mem_collision or core_fifo_full or core_fifo_nopush; |
|
FLAGS_CNTRL_PROC : process(S_AXI_ACLK, S_AXI_ARESETN) is |
begin |
if S_AXI_ARESETN = '0' then |
core_flags <= (others => '0'); |
load_flags <= '0'; |
elsif rising_edge(S_AXI_ACLK) then |
if core_start = '1' then |
core_flags <= (others => '0'); |
else |
if core_ready = '1' then |
core_flags(15) <= '1'; |
else |
core_flags(15) <= core_flags(15); |
end if; |
if core_mem_collision = '1' then |
core_flags(14) <= '1'; |
else |
core_flags(14) <= core_flags(14); |
end if; |
if core_fifo_full = '1' then |
core_flags(13) <= '1'; |
else |
core_flags(13) <= core_flags(13); |
end if; |
if core_fifo_nopush = '1' then |
core_flags(12) <= '1'; |
else |
core_flags(12) <= core_flags(12); |
end if; |
end if; |
load_flags <= core_interrupt; |
end if; |
end process FLAGS_CNTRL_PROC; |
|
IntrEvent <= core_interrupt; |
|
-- high if general core address space is selected |
core_selected <= '1' when address(31 downto 16)=C_BASEADDR(0 to 15) else |
'0'; |
|
-- adress decoder |
with address(14 downto 12) select |
cs_array <= "0000001" when "000", -- M |
"0000010" when "001", -- OP0 |
"0000100" when "010", -- OP1 |
"0001000" when "011", -- OP2 |
"0010000" when "100", -- OP3 |
"0100000" when "101", -- FIFO |
"1000000" when "110", -- user reg space |
"0000000" when others; |
|
slv_reg_selected <= cs_array(6); |
slv_reg_write_enable <= write_enable and slv_reg_selected; |
|
-- high if memory space is selected |
op_mem_selected <= cs_array(0) or cs_array(1) or cs_array(2) or cs_array(3) or cs_array(4); |
|
-- operand memory singals |
MNO_sel <= cs_array(0); |
|
with cs_array(4 downto 1) select |
op_sel <= "00" when "0001", |
"01" when "0010", |
"10" when "0100", |
"11" when "1000", |
"00" when others; |
|
core_rw_address <= MNO_sel & op_sel & address(7 downto 2); |
|
core_write_enable <= write_enable and op_mem_selected; |
|
|
-- FIFO signals |
core_fifo_push <= write_enable and cs_array(5); |
|
------------------------------------------ |
-- Exponentiation core instance |
------------------------------------------ |
msec: entity mod_sim_exp.mod_sim_exp_core |
generic map( |
C_NR_BITS_TOTAL => C_NR_BITS_TOTAL, |
C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL, |
C_NR_STAGES_LOW => C_NR_STAGES_LOW, |
C_SPLIT_PIPELINE => C_SPLIT_PIPELINE, |
C_FIFO_DEPTH => C_FIFO_DEPTH, |
C_MEM_STYLE => C_MEM_STYLE, |
C_DEVICE => C_DEVICE |
) |
port map( |
clk => S_AXI_ACLK, |
reset => reset, |
-- operand memory interface (plb shared memory) |
write_enable => core_write_enable, |
data_in => S_AXI_WDATA(31 downto 0), |
rw_address => core_rw_address, |
data_out => core_data_out, |
collision => core_mem_collision, |
-- op_sel fifo interface |
fifo_din => S_AXI_WDATA(31 downto 0), |
fifo_push => core_fifo_push, |
fifo_full => core_fifo_full, |
fifo_nopush => core_fifo_nopush, |
-- ctrl signals |
start => core_start, |
exp_m => core_exp_m, |
ready => core_ready, |
x_sel_single => core_x_sel_single, |
y_sel_single => core_y_sel_single, |
dest_op_single => core_dest_op_single, |
p_sel => core_p_sel, |
calc_time => calc_time, |
modulus_sel => core_modulus_sel |
); |
|
end IMP; |
/rtl/vhdl/interface/plb/user_logic.vhd
102,7 → 102,7
C_SPLIT_PIPELINE : boolean := true; |
C_FIFO_DEPTH : integer := 32; |
C_MEM_STYLE : string := "xil_prim"; -- xil_prim, generic, asym are valid options |
C_FPGA_MAN : string := "xilinx"; -- xilinx, altera are valid options |
C_DEVICE : string := "xilinx"; -- xilinx, altera are valid options |
-- ADD USER GENERICS ABOVE THIS LINE --------------- |
|
-- DO NOT EDIT BELOW THIS LINE --------------------- |
408,7 → 408,7
C_SPLIT_PIPELINE => C_SPLIT_PIPELINE, |
C_FIFO_DEPTH => C_FIFO_DEPTH, |
C_MEM_STYLE => C_MEM_STYLE, |
C_FPGA_MAN => C_FPGA_MAN |
C_DEVICE => C_DEVICE |
) |
port map( |
clk => Bus2IP_Clk, |
/rtl/vhdl/interface/plb/mod_sim_exp_IPcore.vhd
164,7 → 164,7
C_SPLIT_PIPELINE : boolean := true; |
C_FIFO_DEPTH : integer := 32; |
C_MEM_STYLE : string := "xil_prim"; -- xil_prim, generic, asym are valid options |
C_FPGA_MAN : string := "xilinx"; -- xilinx, altera are valid options |
C_DEVICE : string := "xilinx"; -- xilinx, altera are valid options |
-- ADD USER GENERICS ABOVE THIS LINE --------------- |
|
-- DO NOT EDIT BELOW THIS LINE --------------------- |
582,7 → 582,7
C_SPLIT_PIPELINE => C_SPLIT_PIPELINE, |
C_FIFO_DEPTH => C_FIFO_DEPTH, |
C_MEM_STYLE => C_MEM_STYLE, |
C_FPGA_MAN => C_FPGA_MAN, |
C_DEVICE => C_DEVICE, |
-- MAP USER GENERICS ABOVE THIS LINE --------------- |
|
C_SLV_AWIDTH => USER_SLV_AWIDTH, |
/bench/vhdl/axi_tb.vhd
1,48 → 1,10
---------------------------------------------------------------------- |
---- axi_tb ---- |
---- ---- |
---- This file is part of the ---- |
---- Modular Simultaneous Exponentiation Core project ---- |
---- http://www.opencores.org/cores/mod_sim_exp/ ---- |
---- ---- |
---- Description ---- |
---- testbench for the AXI-Lite interface, functions are ---- |
---- provided to read and write data ---- |
---- writes bus transfers to out/axi_output ---- |
---- ---- |
---- Dependencies: ---- |
---- - mod_sim_exp_core ---- |
---- ---- |
---- Authors: ---- |
---- - Geoffrey Ottoy, DraMCo research group ---- |
---- - Jonas De Craene, JonasDC@opencores.org ---- |
---- ---- |
---------------------------------------------------------------------- |
---- ---- |
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ---- |
---- ---- |
---- This source file may be used and distributed without ---- |
---- restriction provided that this copyright statement is not ---- |
---- removed from the file and that any derivative work contains ---- |
---- the original copyright notice and the associated disclaimer. ---- |
---- ---- |
---- This source file is free software; you can redistribute it ---- |
---- and/or modify it under the terms of the GNU Lesser General ---- |
---- Public License as published by the Free Software Foundation; ---- |
---- either version 2.1 of the License, or (at your option) any ---- |
---- later version. ---- |
---- ---- |
---- This source is distributed in the hope that it will be ---- |
---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- |
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- |
---- PURPOSE. See the GNU Lesser General Public License for more ---- |
---- details. ---- |
---- ---- |
---- You should have received a copy of the GNU Lesser General ---- |
---- Public License along with this source; if not, download it ---- |
---- from http://www.opencores.org/lgpl.shtml ---- |
---- ---- |
---------------------------------------------------------------------- |
-------------------------------------------------------------------------------- |
-- Entity: axi_tb |
-- Date:2013-03-26 |
-- Author: Dinghe |
-- |
-- Description ${cursor} |
-------------------------------------------------------------------------------- |
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_unsigned.all; |
63,20 → 25,7
constant C_S_AXI_ADDR_WIDTH : integer := 32; |
|
file output : text open write_mode is "out/axi_output.txt"; |
|
------------------------------------------------------------------ |
-- Core parameters |
------------------------------------------------------------------ |
constant C_NR_BITS_TOTAL : integer := 1536; |
constant C_NR_STAGES_TOTAL : integer := 96; |
constant C_NR_STAGES_LOW : integer := 32; |
constant C_SPLIT_PIPELINE : boolean := true; |
constant C_FIFO_DEPTH : integer := 32; -- set to (maximum exponent width)/16 |
constant C_MEM_STYLE : string := "generic"; -- xil_prim, generic, asym are valid options |
constant C_FPGA_MAN : string := "xilinx"; -- xilinx, altera are valid options |
constant C_BASEADDR : std_logic_vector(0 to 31) := x"A0000000"; |
constant C_HIGHADDR : std_logic_vector(0 to 31) := x"A0007FFF"; |
|
|
------------------------- |
-- AXI4lite interface |
------------------------- |
242,14 → 191,6
axi_read(x"A0005000"); |
axi_write(x"A0006000", x"EEEEEEEE"); |
axi_read(x"A0006000"); |
axi_write(x"A0007000", x"FFFFFFFF"); |
axi_read(x"A0007000"); |
axi_write(x"A0008000", x"22222222"); |
axi_read(x"A0008000"); |
axi_write(x"A0009000", x"33333333"); |
axi_read(x"A0009000"); |
axi_write(x"A000A000", x"44444444"); |
axi_read(x"A000A000"); |
waitclk(100); |
|
assert false report "End of simulation" severity failure; |
260,17 → 201,10
------------------------- |
-- Unit Under Test |
------------------------- |
uut : entity work.msec_ipcore_axilite |
uut : entity work.axi_lite_slave |
generic map( |
C_NR_BITS_TOTAL => C_NR_BITS_TOTAL, |
C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL, |
C_NR_STAGES_LOW => C_NR_STAGES_LOW, |
C_SPLIT_PIPELINE => C_SPLIT_PIPELINE, |
C_FIFO_DEPTH => C_FIFO_DEPTH, |
C_MEM_STYLE => C_MEM_STYLE, -- xil_prim, generic, asym are valid options |
C_FPGA_MAN => C_FPGA_MAN, -- xilinx, altera are valid options |
C_BASEADDR => C_BASEADDR, |
C_HIGHADDR => C_HIGHADDR |
C_BASEADDR => x"A0000000", |
C_HIGHADDR => x"A000FFFF" |
) |
port map( |
--USER ports |
/bench/vhdl/mod_sim_exp_core_tb.vhd
77,8 → 77,8
constant C_NR_STAGES_LOW : integer := 32; |
constant C_SPLIT_PIPELINE : boolean := true; |
constant C_FIFO_DEPTH : integer := 32; -- set to (maximum exponent width)/16 |
constant C_MEM_STYLE : string := "asym"; -- xil_prim, generic, asym are valid options |
constant C_FPGA_MAN : string := "xilinx"; -- xilinx, altera are valid options |
constant C_MEM_STYLE : string := "generic"; -- xil_prim, generic, asym are valid options |
constant C_DEVICE : string := "xilinx"; -- xilinx, altera are valid options |
|
-- extra calculated constants |
constant NR_BITS_LOW : integer := (C_NR_BITS_TOTAL/C_NR_STAGES_TOTAL)*C_NR_STAGES_LOW; |
679,7 → 679,7
C_SPLIT_PIPELINE => C_SPLIT_PIPELINE, |
C_FIFO_DEPTH => C_FIFO_DEPTH, |
C_MEM_STYLE => C_MEM_STYLE, -- xil_prim, generic, asym are valid options |
C_FPGA_MAN => C_FPGA_MAN -- xilinx, altera are valid options |
C_DEVICE => C_DEVICE -- xilinx, altera are valid options |
) |
port map( |
clk => clk, |
704,7 → 704,7
dest_op_single => core_dest_op_single, |
p_sel => core_p_sel, |
calc_time => calc_time, |
modulus_sel => '0' |
modulus_sel => "0" |
); |
|
end test; |
/sim/Makefile
6,59 → 6,52
## |
# avs_aes hdl files |
## |
CORE_SRC =$(HDL_DIR)core/std_functions.vhd \ |
$(HDL_DIR)core/mod_sim_exp_pkg.vhd \ |
$(HDL_DIR)ram/dpram_generic.vhd \ |
$(HDL_DIR)ram/tdpram_generic.vhd \ |
$(HDL_DIR)ram/dpram_asym.vhd \ |
$(HDL_DIR)ram/dpramblock_asym.vhd \ |
$(HDL_DIR)core/modulus_ram_asym.vhd \ |
$(HDL_DIR)ram/tdpram_asym.vhd \ |
$(HDL_DIR)ram/tdpramblock_asym.vhd \ |
$(HDL_DIR)core/operand_ram_asym.vhd \ |
$(HDL_DIR)core/fifo_generic.vhd \ |
$(HDL_DIR)core/modulus_ram_gen.vhd \ |
$(HDL_DIR)core/operand_ram_gen.vhd \ |
$(HDL_DIR)core/adder_block.vhd \ |
$(HDL_DIR)core/autorun_cntrl.vhd \ |
$(HDL_DIR)core/cell_1b_adder.vhd \ |
$(HDL_DIR)core/cell_1b_mux.vhd \ |
$(HDL_DIR)core/cell_1b.vhd \ |
$(HDL_DIR)core/counter_sync.vhd \ |
$(HDL_DIR)core/d_flip_flop.vhd \ |
$(HDL_DIR)core/fifo_primitive.vhd \ |
$(HDL_DIR)core/modulus_ram.vhd \ |
$(HDL_DIR)core/mont_ctrl.vhd \ |
$(HDL_DIR)core/mod_sim_exp_core.vhd \ |
$(HDL_DIR)core/operand_dp.vhd \ |
$(HDL_DIR)core/operand_mem.vhd \ |
$(HDL_DIR)core/operand_ram.vhd \ |
$(HDL_DIR)core/operands_sp.vhd \ |
$(HDL_DIR)core/register_1b.vhd \ |
$(HDL_DIR)core/register_n.vhd \ |
$(HDL_DIR)core/standard_cell_block.vhd \ |
$(HDL_DIR)core/stepping_logic.vhd \ |
$(HDL_DIR)core/x_shift_reg.vhd \ |
$(HDL_DIR)core/sys_stage.vhd \ |
$(HDL_DIR)core/sys_last_cell_logic.vhd \ |
$(HDL_DIR)core/sys_first_cell_logic.vhd \ |
$(HDL_DIR)core/sys_pipeline.vhd \ |
$(HDL_DIR)core/mont_multiplier.vhd \ |
CORE_SRC =$(HDL_DIR)/core/std_functions.vhd \ |
$(HDL_DIR)/core/mod_sim_exp_pkg.vhd \ |
$(HDL_DIR)/ram/dpram_generic.vhd \ |
$(HDL_DIR)/ram/tdpram_generic.vhd \ |
$(HDL_DIR)/ram/dpram_asym.vhd \ |
$(HDL_DIR)/ram/dpramblock_asym.vhd \ |
$(HDL_DIR)/core/modulus_ram_asym.vhd \ |
$(HDL_DIR)/ram/tdpram_asym.vhd \ |
$(HDL_DIR)/ram/tdpramblock_asym.vhd \ |
$(HDL_DIR)/core/operand_ram_asym.vhd \ |
$(HDL_DIR)/core/fifo_generic.vhd \ |
$(HDL_DIR)/core/modulus_ram_gen.vhd \ |
$(HDL_DIR)/core/operand_ram_gen.vhd \ |
$(HDL_DIR)/core/adder_block.vhd \ |
$(HDL_DIR)/core/autorun_cntrl.vhd \ |
$(HDL_DIR)/core/cell_1b_adder.vhd \ |
$(HDL_DIR)/core/cell_1b_mux.vhd \ |
$(HDL_DIR)/core/cell_1b.vhd \ |
$(HDL_DIR)/core/counter_sync.vhd \ |
$(HDL_DIR)/core/d_flip_flop.vhd \ |
$(HDL_DIR)/core/fifo_primitive.vhd \ |
$(HDL_DIR)/core/modulus_ram.vhd \ |
$(HDL_DIR)/core/mont_ctrl.vhd \ |
$(HDL_DIR)/core/mod_sim_exp_core.vhd \ |
$(HDL_DIR)/core/operand_dp.vhd \ |
$(HDL_DIR)/core/operand_mem.vhd \ |
$(HDL_DIR)/core/operand_ram.vhd \ |
$(HDL_DIR)/core/operands_sp.vhd \ |
$(HDL_DIR)/core/register_1b.vhd \ |
$(HDL_DIR)/core/register_n.vhd \ |
$(HDL_DIR)/core/standard_cell_block.vhd \ |
$(HDL_DIR)/core/stepping_logic.vhd \ |
$(HDL_DIR)/core/x_shift_reg.vhd \ |
$(HDL_DIR)/core/sys_stage.vhd \ |
$(HDL_DIR)/core/sys_last_cell_logic.vhd \ |
$(HDL_DIR)/core/sys_first_cell_logic.vhd \ |
$(HDL_DIR)/core/sys_pipeline.vhd \ |
$(HDL_DIR)/core/mont_multiplier.vhd \ |
|
|
## |
# Testbench HDL files |
# Testbench HDL file |
## |
TB_SRC_DIR = ../bench/vhdl/ |
TB_SRC = $(TB_SRC_DIR)mod_sim_exp_core_tb.vhd \ |
$(TB_SRC_DIR)msec_axi_tb.vhd |
TB_SRC = $(TB_SRC_DIR)mod_sim_exp_core_tb.vhd |
|
## |
# Interface HDL files |
## |
IF_SRC_DIR = ../rtl/vhdl/interface/ |
IF_SRC = $(IF_SRC_DIR)axi/msec_ipcore_axilite.vhd |
|
####################################### |
all: mod_sim_exp |
|
71,7 → 64,7
work_lib: |
vlib work |
|
libs: mod_sim_exp_lib work_lib |
libs: mod_sim_exp work_lib |
|
mod_sim_exp_com: mod_sim_exp_lib |
#echo -- |
82,18 → 75,9
|
mod_sim_exp_tb: work_lib |
#echo -- |
#echo building Modular Exponentiation Core Testbenches |
#echo building Modular Exponentiation Core Testbench |
#echo -- |
vcom $(VCOMOPS) -work work $(TB_SRC) |
|
msec_if: work_lib |
#echo -- |
#echo building Modular Exponentiation Core Interface |
#echo -- |
vcom $(VCOMOPS) -work work $(IF_SRC) |
|
mod_sim_exp: mod_sim_exp_com mod_sim_exp_tb |
vsim -c -do mod_sim_exp.do -lib work mod_sim_exp_core_tb |
|
mod_sim_exp_axi: mod_sim_exp_com msec_if mod_sim_exp_tb |
vsim -c -do mod_sim_exp.do -lib work msec_axi_tb |