OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /mod_sim_exp
    from Rev 19 to Rev 20
    ↔ Reverse comparison
  •

Rev 19 → Rev 20

/trunk/rtl/vhdl/core/x_shift_reg.vhd
6,7 → 6,8
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- 1536 bit shift register with lsb output ----
---- n bit shift register for the x operand of the multiplier ----
---- with bit output ----
---- ----
---- Dependencies: none ----
---- ----
46,28 → 47,34
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
 
-- shift register for the x operand of the multiplier
-- outputs the lsb of the register or bit at offset according to the
-- selected pipeline part
entity x_shift_reg is
generic(
n : integer := 1536;
t : integer := 48;
tl : integer := 16
n : integer := 1536; -- width of the operands (# bits)
t : integer := 48; -- total number of stages
tl : integer := 16 -- lower number of stages
);
port(
-- clock input
clk : in std_logic;
reset : in std_logic;
-- x operand in (n-bit)
x_in : in std_logic_vector((n-1) downto 0);
load_x : in std_logic;
next_x : in std_logic;
p_sel : in std_logic_vector(1 downto 0);
x_i : out std_logic
-- control signals
reset : in std_logic; -- reset, clears register
load_x : in std_logic; -- load operand into shift register
next_x : in std_logic; -- next bit of x
p_sel : in std_logic_vector(1 downto 0); -- pipeline selection
-- x operand bit out (serial)
x_i : out std_logic
);
end x_shift_reg;
 
 
architecture Behavioral of x_shift_reg is
signal x_reg_i : std_logic_vector((n-1) downto 0); -- register
constant s : integer := n/t; -- nr of stages
signal x_reg : std_logic_vector((n-1) downto 0); -- register
constant s : integer := n/t; -- stage width
constant offset : integer := s*tl; -- calculate startbit pos of higher part of pipeline
begin
 
74,20 → 81,20
REG_PROC: process(reset, clk)
begin
if reset = '1' then -- Reset, clear the register
x_reg_i <= (others => '0');
x_reg <= (others => '0');
elsif rising_edge(clk) then
if load_x = '1' then -- Load_x, load the register with x_in
x_reg_i <= x_in;
x_reg <= x_in;
elsif next_x = '1' then -- next_x, shift to right. LSbit gets lost and zero's are shifted in
x_reg_i((n-2) downto 0) <= x_reg_i((n-1) downto 1);
x_reg((n-2) downto 0) <= x_reg((n-1) downto 1);
else -- else remember state
x_reg_i <= x_reg_i;
x_reg <= x_reg;
end if;
end if;
end process;
 
with p_sel select -- pipeline select
x_i <= x_reg_i(offset) when "10", -- use bit at offset for high part of pipeline
x_reg_i(0) when others; -- use LS bit for lower part of pipeline
x_i <= x_reg(offset) when "10", -- use bit at offset for high part of pipeline
x_reg(0) when others; -- use LS bit for lower part of pipeline
 
end Behavioral;
/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
381,6 → 381,34
);
end component stepping_logic;
 
--------------------------------------------------------------------
-- x_shift_reg
--------------------------------------------------------------------
-- shift register for the x operand of the multiplier
-- outputs the lsb of the register or bit at offset according to the
-- selected pipeline part
--
component x_shift_reg is
generic(
n : integer := 1536; -- width of the operands (# bits)
t : integer := 48; -- total number of stages
tl : integer := 16 -- lower number of stages
);
port(
-- clock input
clk : in std_logic;
-- x operand in (n-bit)
x_in : in std_logic_vector((n-1) downto 0);
-- control signals
reset : in std_logic; -- reset, clears register
load_x : in std_logic; -- load operand into shift register
next_x : in std_logic; -- next bit of x
p_sel : in std_logic_vector(1 downto 0); -- pipeline selection
-- x operand bit out (serial)
x_i : out std_logic
);
end component x_shift_reg;
component autorun_cntrl is
port (
clk : in std_logic;
588,21 → 616,4
);
end component systolic_pipeline;
component x_shift_reg is
generic(
n : integer := 1536;
t : integer := 48;
tl : integer := 16
);
port(
clk : in std_logic;
reset : in std_logic;
x_in : in std_logic_vector((n-1) downto 0);
load_x : in std_logic;
next_x : in std_logic;
p_sel : in std_logic_vector(1 downto 0);
x_i : out std_logic
);
end component x_shift_reg;
end package mod_sim_exp_pkg;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.