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URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

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  • This comparison shows the changes necessary to convert path
    /mod_sim_exp
    from Rev 44 to Rev 45
    Reverse comparison

Rev 44 → Rev 45

/trunk/rtl/vhdl/interface/plb/user_logic.vhd
168,7 → 168,7
-- Signals for multiplier core interrupt
------------------------------------------------------------------
signal core_interrupt : std_logic_vector(0 to 0);
signal core_fifo_full : std_logic;
signal core_fifo_full : std_logic;
signal core_fifo_nopush : std_logic;
signal core_ready : std_logic;
signal core_mem_collision : std_logic;
177,7 → 177,7
-- Signals for multiplier core control
------------------------------------------------------------------
signal core_start : std_logic;
signal core_run_auto : std_logic;
signal core_exp_m : std_logic;
signal core_p_sel : std_logic_vector(1 downto 0);
signal core_dest_op_single : std_logic_vector(1 downto 0);
signal core_x_sel_single : std_logic_vector(1 downto 0);
385,7 → 385,7
-- Map slv_reg0 bits to core control signals
------------------------------------------
core_start <= slv_reg0(8);
core_run_auto <= slv_reg0(9);
core_exp_m <= slv_reg0(9);
core_p_sel <= slv_reg0(0 to 1);
core_dest_op_single <= slv_reg0(2 to 3);
core_x_sel_single <= slv_reg0(4 to 5);
417,7 → 417,7
fifo_nopush => core_fifo_nopush,
-- ctrl signals
start => core_start,
run_auto => core_run_auto,
exp_m => core_exp_m,
ready => core_ready,
x_sel_single => core_x_sel_single,
y_sel_single => core_y_sel_single,
/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
313,7 → 313,7
fifo_nopush : out std_logic; -- high if error during push
-- control signals
start : in std_logic; -- start multiplication/exponentiation
run_auto : in std_logic; -- single multiplication if low, exponentiation if high
exp_m : in std_logic; -- single multiplication if low, exponentiation if high
ready : out std_logic; -- calculations done
x_sel_single : in std_logic_vector (1 downto 0); -- single multiplication x operand selection
y_sel_single : in std_logic_vector (1 downto 0); -- single multiplication y operand selection
/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
81,7 → 81,7
fifo_nopush : out std_logic; -- high if error during push
-- control signals
start : in std_logic; -- start multiplication/exponentiation
run_auto : in std_logic; -- single multiplication if low, exponentiation if high
exp_m : in std_logic; -- single multiplication if low, exponentiation if high
ready : out std_logic; -- calculations done
x_sel_single : in std_logic_vector (1 downto 0); -- single multiplication x operand selection
y_sel_single : in std_logic_vector (1 downto 0); -- single multiplication y operand selection
153,7 → 153,7
clk => clk
);
result_dest_op <= dest_op_single when run_auto = '0' else "11"; -- in autorun mode we always store the result in operand3
result_dest_op <= dest_op_single when exp_m = '0' else "11"; -- in autorun mode we always store the result in operand3
-- A fifo for auto-run operand selection
the_exponent_fifo : fifo_primitive
178,7 → 178,7
start => start,
x_sel_single => x_sel_single,
y_sel_single => y_sel_single,
run_auto => run_auto,
run_auto => exp_m,
op_buffer_empty => fifo_empty,
op_sel_buffer => fifo_dout,
read_buffer => fifo_pop,

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