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/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
47,6 → 47,8
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
library mod_sim_exp;
use mod_sim_exp.std_functions.all;
 
package mod_sim_exp_pkg is
--------------------------------------------------------------------
53,6 → 55,8
---------------------- COMPONENT DECLARATIONS ----------------------
--------------------------------------------------------------------
--------------------------- MULTIPLIER -----------------------------
--------------------------------------------------------------------
-- d_flip_flop
--------------------------------------------------------------------
282,47 → 286,7
xi : out std_logic
);
end component x_shift_reg;
 
--------------------------------------------------------------------
-- mod_sim_exp_core
--------------------------------------------------------------------
-- toplevel of the modular simultaneous exponentiation core
-- contains an operand and modulus ram, multiplier, an exponent fifo
-- and control logic
--
component mod_sim_exp_core is
generic(
C_NR_BITS_TOTAL : integer := 1536;
C_NR_STAGES_TOTAL : integer := 96;
C_NR_STAGES_LOW : integer := 32;
C_SPLIT_PIPELINE : boolean := true
);
port(
clk : in std_logic;
reset : in std_logic;
-- operand memory interface (plb shared memory)
write_enable : in std_logic; -- write data to operand ram
data_in : in std_logic_vector (31 downto 0); -- operand ram data in
rw_address : in std_logic_vector (8 downto 0); -- operand ram address bus
data_out : out std_logic_vector (31 downto 0); -- operand ram data out
collision : out std_logic; -- write collision
-- op_sel fifo interface
fifo_din : in std_logic_vector (31 downto 0); -- exponent fifo data in
fifo_push : in std_logic; -- push data in exponent fifo
fifo_full : out std_logic; -- high if fifo is full
fifo_nopush : out std_logic; -- high if error during push
-- control signals
start : in std_logic; -- start multiplication/exponentiation
exp_m : in std_logic; -- single multiplication if low, exponentiation if high
ready : out std_logic; -- calculations done
x_sel_single : in std_logic_vector (1 downto 0); -- single multiplication x operand selection
y_sel_single : in std_logic_vector (1 downto 0); -- single multiplication y operand selection
dest_op_single : in std_logic_vector (1 downto 0); -- result destination operand selection
p_sel : in std_logic_vector (1 downto 0); -- pipeline part selection
calc_time : out std_logic
);
end component mod_sim_exp_core;
 
component autorun_cntrl is
port (
clk : in std_logic;
338,31 → 302,6
);
end component autorun_cntrl;
component fifo_primitive is
port (
clk : in std_logic;
din : in std_logic_vector (31 downto 0);
dout : out std_logic_vector (31 downto 0);
empty : out std_logic;
full : out std_logic;
push : in std_logic;
pop : in std_logic;
reset : in std_logic;
nopop : out std_logic;
nopush : out std_logic
);
end component fifo_primitive;
component modulus_ram is
port(
clk : in std_logic;
modulus_addr : in std_logic_vector(5 downto 0);
write_modulus : in std_logic;
modulus_in : in std_logic_vector(31 downto 0);
modulus_out : out std_logic_vector(1535 downto 0)
);
end component modulus_ram;
--------------------------------------------------------------------
-- mont_ctrl
--------------------------------------------------------------------
392,83 → 331,6
);
end component mont_ctrl;
component operand_dp is
port (
clka : in std_logic;
wea : in std_logic_vector(0 downto 0);
addra : in std_logic_vector(5 downto 0);
dina : in std_logic_vector(31 downto 0);
douta : out std_logic_vector(511 downto 0);
clkb : in std_logic;
web : in std_logic_vector(0 downto 0);
addrb : in std_logic_vector(5 downto 0);
dinb : in std_logic_vector(511 downto 0);
doutb : out std_logic_vector(31 downto 0)
);
end component operand_dp;
component operand_mem is
generic(
n : integer := 1536
);
port(
-- data interface (plb side)
data_in : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(31 downto 0);
rw_address : in std_logic_vector(8 downto 0);
write_enable : in std_logic;
-- address structure:
-- bit: 8 -> '1': modulus
-- '0': operands
-- bits: 7-6 -> operand_in_sel in case of bit 8 = '0'
-- don't care in case of modulus
-- bits: 5-0 -> modulus_addr / operand_addr resp.
-- operand interface (multiplier side)
op_sel : in std_logic_vector(1 downto 0);
xy_out : out std_logic_vector((n-1) downto 0);
m : out std_logic_vector((n-1) downto 0);
result_in : in std_logic_vector((n-1) downto 0);
-- control signals
load_result : in std_logic;
result_dest_op : in std_logic_vector(1 downto 0);
collision : out std_logic;
-- system clock
clk : in std_logic
);
end component operand_mem;
component operand_ram is
port( -- write_operand_ack voorzien?
-- global ports
clk : in std_logic;
collision : out std_logic;
-- bus side connections (32-bit serial)
operand_addr : in std_logic_vector(5 downto 0);
operand_in : in std_logic_vector(31 downto 0);
operand_in_sel : in std_logic_vector(1 downto 0);
result_out : out std_logic_vector(31 downto 0);
write_operand : in std_logic;
-- multiplier side connections (1536 bit parallel)
result_dest_op : in std_logic_vector(1 downto 0);
operand_out : out std_logic_vector(1535 downto 0);
operand_out_sel : in std_logic_vector(1 downto 0); -- controlled by bus side
write_result : in std_logic;
result_in : in std_logic_vector(1535 downto 0)
);
end component operand_ram;
component operands_sp is
port (
clka : in std_logic;
wea : in std_logic_vector(0 downto 0);
addra : in std_logic_vector(4 downto 0);
dina : in std_logic_vector(31 downto 0);
douta : out std_logic_vector(511 downto 0)
);
end component operands_sp;
component sys_stage is
generic(
width : integer := 32 -- width of the stage
601,5 → 463,345
ready : out std_logic
);
end component mont_multiplier;
 
 
------------------------------ MEMORY ------------------------------
--------------------------------------------------------------------
-- operand_dp
--------------------------------------------------------------------
-- true dual port RAM 512x4, uses xilinx primitives
--
component operand_dp is
port (
clka : in std_logic;
wea : in std_logic_vector(0 downto 0);
addra : in std_logic_vector(5 downto 0);
dina : in std_logic_vector(31 downto 0);
douta : out std_logic_vector(511 downto 0);
clkb : in std_logic;
web : in std_logic_vector(0 downto 0);
addrb : in std_logic_vector(5 downto 0);
dinb : in std_logic_vector(511 downto 0);
doutb : out std_logic_vector(31 downto 0)
);
end component operand_dp;
--------------------------------------------------------------------
-- operand_sp
--------------------------------------------------------------------
-- dual port RAM 512x2, uses xilinx primitives
--
component operands_sp is
port (
clka : in std_logic;
wea : in std_logic_vector(0 downto 0);
addra : in std_logic_vector(4 downto 0);
dina : in std_logic_vector(31 downto 0);
douta : out std_logic_vector(511 downto 0)
);
end component operands_sp;
--------------------------------------------------------------------
-- dpram_generic
--------------------------------------------------------------------
-- behavorial description of a dual port ram with one 32-bit
-- write port and one 32-bit read port
--
component dpram_generic is
generic (
depth : integer := 2
);
port (
clk : in std_logic;
-- write port
waddr : in std_logic_vector(log2(depth)-1 downto 0);
we : in std_logic;
din : in std_logic_vector(31 downto 0);
-- read port
raddr : in std_logic_vector(log2(depth)-1 downto 0);
dout : out std_logic_vector(31 downto 0)
);
end component dpram_generic;
--------------------------------------------------------------------
-- tdpram_generic
--------------------------------------------------------------------
-- behavorial description of a true dual port ram with 2
-- 32-bit write/read ports
--
component tdpram_generic is
generic (
depth : integer := 9
);
port (
-- port A
clkA : in std_logic;
addrA : in std_logic_vector(log2(depth)-1 downto 0);
weA : in std_logic;
dinA : in std_logic_vector(31 downto 0);
doutA : out std_logic_vector(31 downto 0);
-- port B
clkB : in std_logic;
addrB : in std_logic_vector(log2(depth)-1 downto 0);
weB : in std_logic;
dinB : in std_logic_vector(31 downto 0);
doutB : out std_logic_vector(31 downto 0)
);
end component tdpram_generic;
--------------------------------------------------------------------
-- fifo_primitive
--------------------------------------------------------------------
-- a xilinx fifo primitive wrapper
--
component fifo_primitive is
port (
clk : in std_logic;
din : in std_logic_vector (31 downto 0);
dout : out std_logic_vector (31 downto 0);
empty : out std_logic;
full : out std_logic;
push : in std_logic;
pop : in std_logic;
reset : in std_logic;
nopop : out std_logic;
nopush : out std_logic
);
end component fifo_primitive;
--------------------------------------------------------------------
-- fifo_generic
--------------------------------------------------------------------
-- a behavorial implementation of a fifo that is designed to
-- infer blockram
--
component fifo_generic is
generic (
depth : integer := 32
);
port (
clk : in std_logic; -- clock input
din : in std_logic_vector (31 downto 0); -- 32 bit input data for push
dout : out std_logic_vector (31 downto 0); -- 32 bit output data for pop
empty : out std_logic; -- empty flag, 1 when FIFO is empty
full : out std_logic; -- full flag, 1 when FIFO is full
push : in std_logic;
pop : in std_logic;
reset : in std_logic;
nopop : out std_logic;
nopush : out std_logic
);
end component fifo_generic;
--------------------------------------------------------------------
-- modulus_ram
--------------------------------------------------------------------
-- RAM for the modulus, fixed width of 1536-bit, uses xilinx primitives
--
component modulus_ram is
port(
clk : in std_logic;
modulus_addr : in std_logic_vector(5 downto 0);
write_modulus : in std_logic;
modulus_in : in std_logic_vector(31 downto 0);
modulus_out : out std_logic_vector(1535 downto 0)
);
end component modulus_ram;
--------------------------------------------------------------------
-- modulus_ram_gen
--------------------------------------------------------------------
-- behavorial description of a RAM to hold the modulus, with
-- adjustable width and depth(nr of moduluses)
--
component modulus_ram_gen is
generic(
width : integer := 1536; -- must be a multiple of 32
depth : integer := 2 -- nr of moduluses
);
port(
clk : in std_logic;
-- bus side
write_modulus : in std_logic; -- write enable
modulus_in_sel : in std_logic_vector(log2(depth)-1 downto 0); -- modulus operand to write to
modulus_addr : in std_logic_vector(log2((width)/32)-1 downto 0); -- modulus word(32-bit) address
modulus_in : in std_logic_vector(31 downto 0); -- modulus word data in
modulus_sel : in std_logic_vector(log2(depth)-1 downto 0); -- selects the modulus to use for multiplications
-- multiplier side
modulus_out : out std_logic_vector(width-1 downto 0)
);
end component modulus_ram_gen;
--------------------------------------------------------------------
-- operand_ram_gen
--------------------------------------------------------------------
-- behavorial description of a RAM to hold the operands, with
-- adjustable width and depth(nr of operands)
--
component operand_ram_gen is
generic(
width : integer := 1536; -- width of the operands
depth : integer := 4 -- nr of operands
);
port(
-- global ports
clk : in std_logic;
collision : out std_logic; -- 1 if simultaneous write on RAM
-- bus side connections (32-bit serial)
write_operand : in std_logic; -- write_enable
operand_in_sel : in std_logic_vector(log2(depth)-1 downto 0); -- operand to write to
operand_addr : in std_logic_vector(log2(width/32)-1 downto 0); -- address of operand word to write
operand_in : in std_logic_vector(31 downto 0); -- operand word(32-bit) to write
result_out : out std_logic_vector(31 downto 0); -- operand out, reading is always result operand
operand_out_sel : in std_logic_vector(log2(depth)-1 downto 0); -- operand to give to multiplier
-- multiplier side connections (width-bit parallel)
result_dest_op : in std_logic_vector(log2(depth)-1 downto 0); -- operand select for result
operand_out : out std_logic_vector(width-1 downto 0); -- operand out to multiplier
write_result : in std_logic; -- write enable for multiplier side
result_in : in std_logic_vector(width-1 downto 0) -- result to write from multiplier
);
end component operand_ram_gen;
--------------------------------------------------------------------
-- operand_ram
--------------------------------------------------------------------
-- RAM for the operands, fixed width of 1536-bit and depth of 4
-- uses xilinx primitives
--
component operand_ram is
port( -- write_operand_ack voorzien?
-- global ports
clk : in std_logic;
collision : out std_logic;
-- bus side connections (32-bit serial)
operand_addr : in std_logic_vector(5 downto 0);
operand_in : in std_logic_vector(31 downto 0);
operand_in_sel : in std_logic_vector(1 downto 0);
result_out : out std_logic_vector(31 downto 0);
write_operand : in std_logic;
-- multiplier side connections (1536 bit parallel)
result_dest_op : in std_logic_vector(1 downto 0);
operand_out : out std_logic_vector(1535 downto 0);
operand_out_sel : in std_logic_vector(1 downto 0); -- controlled by bus side
write_result : in std_logic;
result_in : in std_logic_vector(1535 downto 0)
);
end component operand_ram;
component operand_mem is
generic(
n : integer := 1536
);
port(
-- data interface (plb side)
data_in : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(31 downto 0);
rw_address : in std_logic_vector(8 downto 0);
write_enable : in std_logic;
-- address structure:
-- bit: 8 -> '1': modulus
-- '0': operands
-- bits: 7-6 -> operand_in_sel in case of bit 8 = '0'
-- don't care in case of modulus
-- bits: 5-0 -> modulus_addr / operand_addr resp.
-- operand interface (multiplier side)
op_sel : in std_logic_vector(1 downto 0);
xy_out : out std_logic_vector((n-1) downto 0);
m : out std_logic_vector((n-1) downto 0);
result_in : in std_logic_vector((n-1) downto 0);
-- control signals
load_result : in std_logic;
result_dest_op : in std_logic_vector(1 downto 0);
collision : out std_logic;
-- system clock
clk : in std_logic
);
end component operand_mem;
--------------------------------------------------------------------
-- operand_mem_gen
--------------------------------------------------------------------
-- generic description of the cores memory, places the modulus
-- and operands in one addres and data bus
--
-- address structure:
-- bit: highest -> '1': modulus
-- '0': operands
-- bits: (highest-1)-log2(width/32) -> operand_in_sel in case of highest bit = '0'
-- modulus_in_sel in case of highest bit = '1'
-- bits: (log2(width/32)-1)-0 -> modulus_addr / operand_addr resp.
--
component operand_mem_gen is
generic(
width : integer := 1536; -- width of the operands
nr_op : integer := 4; -- nr of operand storages, has to be greater than nr_m
nr_m : integer := 2 -- nr of modulus storages
);
port(
-- system clock
clk : in std_logic;
-- data interface (plb side)
data_in : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(31 downto 0);
rw_address : in std_logic_vector(log2(nr_op)+log2(width/32) downto 0);
write_enable : in std_logic;
-- operand interface (multiplier side)
op_sel : in std_logic_vector(log2(nr_op)-1 downto 0);
xy_out : out std_logic_vector((width-1) downto 0);
m : out std_logic_vector((width-1) downto 0);
result_in : in std_logic_vector((width-1) downto 0);
-- control signals
load_result : in std_logic;
result_dest_op : in std_logic_vector(log2(nr_op)-1 downto 0);
collision : out std_logic;
modulus_sel : in std_logic_vector(log2(nr_m)-1 downto 0)
);
end component operand_mem_gen;
---------------------------- TOP LEVEL -----------------------------
--------------------------------------------------------------------
-- mod_sim_exp_core
--------------------------------------------------------------------
-- toplevel of the modular simultaneous exponentiation core
-- contains an operand and modulus ram, multiplier, an exponent fifo
-- and control logic
--
component mod_sim_exp_core is
generic(
C_NR_BITS_TOTAL : integer := 1536;
C_NR_STAGES_TOTAL : integer := 96;
C_NR_STAGES_LOW : integer := 32;
C_SPLIT_PIPELINE : boolean := true
);
port(
clk : in std_logic;
reset : in std_logic;
-- operand memory interface (plb shared memory)
write_enable : in std_logic; -- write data to operand ram
data_in : in std_logic_vector (31 downto 0); -- operand ram data in
rw_address : in std_logic_vector (8 downto 0); -- operand ram address bus
data_out : out std_logic_vector (31 downto 0); -- operand ram data out
collision : out std_logic; -- write collision
-- op_sel fifo interface
fifo_din : in std_logic_vector (31 downto 0); -- exponent fifo data in
fifo_push : in std_logic; -- push data in exponent fifo
fifo_full : out std_logic; -- high if fifo is full
fifo_nopush : out std_logic; -- high if error during push
-- control signals
start : in std_logic; -- start multiplication/exponentiation
exp_m : in std_logic; -- single multiplication if low, exponentiation if high
ready : out std_logic; -- calculations done
x_sel_single : in std_logic_vector (1 downto 0); -- single multiplication x operand selection
y_sel_single : in std_logic_vector (1 downto 0); -- single multiplication y operand selection
dest_op_single : in std_logic_vector (1 downto 0); -- result destination operand selection
p_sel : in std_logic_vector (1 downto 0); -- pipeline part selection
calc_time : out std_logic
);
end component mod_sim_exp_core;
end package mod_sim_exp_pkg;
/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
54,6 → 54,7
 
library mod_sim_exp;
use mod_sim_exp.mod_sim_exp_pkg.all;
use mod_sim_exp.std_functions.all;
 
-- toplevel of the modular simultaneous exponentiation core
-- contains an operand and modulus ram, multiplier, an exponent fifo
63,7 → 64,10
C_NR_BITS_TOTAL : integer := 1536;
C_NR_STAGES_TOTAL : integer := 96;
C_NR_STAGES_LOW : integer := 32;
C_SPLIT_PIPELINE : boolean := true
C_SPLIT_PIPELINE : boolean := true;
C_NR_OP : integer := 4;
C_NR_M : integer := 2;
C_FIFO_DEPTH : integer := 32
);
port(
clk : in std_logic;
71,7 → 75,7
-- operand memory interface (plb shared memory)
write_enable : in std_logic; -- write data to operand ram
data_in : in std_logic_vector (31 downto 0); -- operand ram data in
rw_address : in std_logic_vector (8 downto 0); -- operand ram address bus
rw_address : in std_logic_vector (log2(C_NR_OP)+log2(C_NR_BITS_TOTAL/32) downto 0); -- operand ram address bus
data_out : out std_logic_vector (31 downto 0); -- operand ram data out
collision : out std_logic; -- write collision
-- op_sel fifo interface
83,11 → 87,12
start : in std_logic; -- start multiplication/exponentiation
exp_m : in std_logic; -- single multiplication if low, exponentiation if high
ready : out std_logic; -- calculations done
x_sel_single : in std_logic_vector (1 downto 0); -- single multiplication x operand selection
y_sel_single : in std_logic_vector (1 downto 0); -- single multiplication y operand selection
dest_op_single : in std_logic_vector (1 downto 0); -- result destination operand selection
x_sel_single : in std_logic_vector (log2(C_NR_OP)-1 downto 0); -- single multiplication x operand selection
y_sel_single : in std_logic_vector (log2(C_NR_OP)-1 downto 0); -- single multiplication y operand selection
dest_op_single : in std_logic_vector (log2(C_NR_OP)-1 downto 0); -- result destination operand selection
p_sel : in std_logic_vector (1 downto 0); -- pipeline part selection
calc_time : out std_logic
calc_time : out std_logic;
modulus_sel : in std_logic_vector(log2(C_NR_M)-1 downto 0)
);
end mod_sim_exp_core;
 
134,9 → 139,11
);
 
-- Block ram memory for storing the operands and the modulus
the_memory : operand_mem
the_memory : operand_mem_gen
generic map(
n => C_NR_BITS_TOTAL
width => C_NR_BITS_TOTAL,
nr_op => C_NR_OP,
nr_m => C_NR_M
)
port map(
data_in => data_in,
150,13 → 157,17
load_result => load_result,
result_dest_op => result_dest_op,
collision => collision,
clk => clk
clk => clk,
modulus_sel => modulus_sel
);
result_dest_op <= dest_op_single when exp_m = '0' else "11"; -- in autorun mode we always store the result in operand3
-- A fifo for auto-run operand selection
the_exponent_fifo : fifo_primitive
the_exponent_fifo : fifo_generic
generic map(
depth => C_FIFO_DEPTH
)
port map(
clk => clk,
din => fifo_din,
/trunk/rtl/vhdl/core/operand_mem_gen.vhd
0,0 → 1,157
----------------------------------------------------------------------
---- operand_mem_gen ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- BRAM memory and logic to the store 4 (1536-bit) operands ----
---- and the modulus for the montgomery multiplier ----
---- ----
---- Dependencies: ----
---- - operand_ram_gen ----
---- - modulus_ram_gen ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
library mod_sim_exp;
use mod_sim_exp.mod_sim_exp_pkg.all;
use mod_sim_exp.std_functions.all;
 
-- address structure:
-- bit: highest -> '1': modulus
-- '0': operands
-- bits: (highest-1)-log2(width/32) -> operand_in_sel in case of highest bit = '0'
-- modulus_in_sel in case of highest bit = '1'
-- bits: (log2(width/32)-1)-0 -> modulus_addr / operand_addr resp.
--
entity operand_mem_gen is
generic(
width : integer := 1536; -- width of the operands
nr_op : integer := 4; -- nr of operand storages, has to be greater than nr_m
nr_m : integer := 2 -- nr of modulus storages
);
port(
-- system clock
clk : in std_logic;
-- data interface (plb side)
data_in : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(31 downto 0);
rw_address : in std_logic_vector(log2(nr_op)+log2(width/32) downto 0);
write_enable : in std_logic;
-- operand interface (multiplier side)
op_sel : in std_logic_vector(log2(nr_op)-1 downto 0);
xy_out : out std_logic_vector((width-1) downto 0);
m : out std_logic_vector((width-1) downto 0);
result_in : in std_logic_vector((width-1) downto 0);
-- control signals
load_result : in std_logic;
result_dest_op : in std_logic_vector(log2(nr_op)-1 downto 0);
collision : out std_logic;
modulus_sel : in std_logic_vector(log2(nr_m)-1 downto 0)
);
end operand_mem_gen;
 
architecture Behavioral of operand_mem_gen is
constant wordaddr_aw : integer := log2(width/32);
constant opaddr_aw : integer := log2(nr_op);
constant maddr_aw : integer := log2(nr_m);
constant total_aw : integer := 1+opaddr_aw+wordaddr_aw;
 
signal xy_data_i : std_logic_vector(31 downto 0);
signal xy_addr_i : std_logic_vector(wordaddr_aw-1 downto 0);
signal operand_in_sel_i : std_logic_vector(opaddr_aw-1 downto 0);
signal modulus_in_sel_i : std_logic_vector(maddr_aw-1 downto 0);
 
signal load_op : std_logic;
 
signal m_addr_i : std_logic_vector(wordaddr_aw-1 downto 0);
signal load_m : std_logic;
signal m_data_i : std_logic_vector(31 downto 0);
 
begin
 
-- map inputs
xy_addr_i <= rw_address(wordaddr_aw-1 downto 0);
m_addr_i <= rw_address(wordaddr_aw-1 downto 0);
operand_in_sel_i <= rw_address(total_aw-2 downto wordaddr_aw);
modulus_in_sel_i <= rw_address(wordaddr_aw+maddr_aw-1 downto wordaddr_aw);
xy_data_i <= data_in;
m_data_i <= data_in;
load_op <= write_enable when (rw_address(total_aw-1) = '0') else '0';
load_m <= write_enable when (rw_address(total_aw-1) = '1') else '0';
 
-- xy operand storage
xy_ram : operand_ram_gen
generic map(
width => width,
depth => nr_op
)
port map(
clk => clk,
collision => collision,
operand_addr => xy_addr_i,
operand_in => xy_data_i,
operand_in_sel => operand_in_sel_i,
result_out => data_out,
write_operand => load_op,
operand_out => xy_out,
operand_out_sel => op_sel,
result_dest_op => result_dest_op,
write_result => load_result,
result_in => result_in
);
 
-- modulus storage
m_ram : modulus_ram_gen
generic map(
width => width,
depth => nr_m
)
port map(
clk => clk,
modulus_in_sel => modulus_in_sel_i,
modulus_addr => m_addr_i,
write_modulus => load_m,
modulus_in => m_data_i,
modulus_out => m,
modulus_sel => modulus_sel
);
end Behavioral;
/trunk/rtl/vhdl/core/modulus_ram_gen.vhd
0,0 → 1,120
----------------------------------------------------------------------
---- modulus_ram_gen ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- BRAM memory and logic to store the modulus, due to the ----
---- achitecture, a minimum depth of 2 is needed for this ----
---- module to be inferred into blockram ----
---- ----
---- Dependencies: ----
---- - dpram_generic ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
library mod_sim_exp;
use mod_sim_exp.mod_sim_exp_pkg.all;
use mod_sim_exp.std_functions.all;
 
-- behavorial description of a RAM to hold the modulus, with
-- adjustable width and depth(nr of moduluses)
entity modulus_ram_gen is
generic(
width : integer := 1536; -- must be a multiple of 32
depth : integer := 2 -- nr of moduluses
);
port(
clk : in std_logic;
-- bus side
write_modulus : in std_logic; -- write enable
modulus_in_sel : in std_logic_vector(log2(depth)-1 downto 0); -- modulus operand to write to
modulus_addr : in std_logic_vector(log2((width)/32)-1 downto 0); -- modulus word(32-bit) address
modulus_in : in std_logic_vector(31 downto 0); -- modulus word data in
modulus_sel : in std_logic_vector(log2(depth)-1 downto 0); -- selects the modulus to use for multiplications
-- multiplier side
modulus_out : out std_logic_vector(width-1 downto 0)
);
end modulus_ram_gen;
 
architecture Behavioral of modulus_ram_gen is
--- constants
constant nrRAMs : integer := width/32;
constant RAMselect_aw : integer := log2(nrRAMs);
constant RAMdepth_aw : integer := log2(depth);
constant total_aw : integer := RAMdepth_aw+RAMselect_aw;
 
-- interconnection signals
signal modulus_rdaddr : std_logic_vector(RAMdepth_aw-1 downto 0);
signal modulus_wraddr : std_logic_vector(total_aw-1 downto 0);
signal we : std_logic_vector(nrRAMs-1 downto 0);
begin
modulus_wraddr(RAMselect_aw-1 downto 0) <= modulus_addr;
modulus_wraddr(total_aw-1 downto RAMselect_aw) <= modulus_in_sel;
-- generate (width/32) blocks of 32-bit ram with a given depth
-- these rams outputs are concatenated to a width-bit signal
ramblocks : for i in 0 to nrRAMs-1 generate
ramblock: dpram_generic
generic map(
depth => depth
)
port map(
clk => clk,
-- write port
waddr => modulus_wraddr(total_aw-1 downto RAMselect_aw),
we => we(i),
din => modulus_in,
-- read port
raddr => modulus_rdaddr,
dout => modulus_out(((i+1)*32)-1 downto i*32)
);
-- connect the w
process (write_modulus, modulus_wraddr)
begin
if modulus_wraddr(RAMselect_aw-1 downto 0) = conv_std_logic_vector(i,RAMselect_aw) then
we(i) <= write_modulus;
else
we(i) <= '0';
end if;
end process;
end generate;
modulus_rdaddr <= modulus_sel;
end Behavioral;
/trunk/rtl/vhdl/core/operand_ram_gen.vhd
0,0 → 1,177
----------------------------------------------------------------------
---- operand_ram_gen ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- BRAM memory and logic to the store the operands ----
---- for the montgomery multiplier ----
---- ----
---- Dependencies: ----
---- - tdpram_generic ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
library mod_sim_exp;
use mod_sim_exp.mod_sim_exp_pkg.all;
use mod_sim_exp.std_functions.all;
 
-- behavorial description of a RAM to hold the operands, with
-- adjustable width and depth(nr of operands)
entity operand_ram_gen is
generic(
width : integer := 1536; -- width of the operands
depth : integer := 4 -- nr of operands
);
port(
-- global ports
clk : in std_logic;
collision : out std_logic; -- 1 if simultaneous write on RAM
-- bus side connections (32-bit serial)
write_operand : in std_logic; -- write_enable
operand_in_sel : in std_logic_vector(log2(depth)-1 downto 0); -- operand to write to
operand_addr : in std_logic_vector(log2(width/32)-1 downto 0); -- address of operand word to write
operand_in : in std_logic_vector(31 downto 0); -- operand word(32-bit) to write
result_out : out std_logic_vector(31 downto 0); -- operand out, reading is always result operand
operand_out_sel : in std_logic_vector(log2(depth)-1 downto 0); -- operand to give to multiplier
-- multiplier side connections (width-bit parallel)
result_dest_op : in std_logic_vector(log2(depth)-1 downto 0); -- operand select for result
operand_out : out std_logic_vector(width-1 downto 0); -- operand out to multiplier
write_result : in std_logic; -- write enable for multiplier side
result_in : in std_logic_vector(width-1 downto 0) -- result to write from multiplier
);
end operand_ram_gen;
 
 
architecture Behavioral of operand_ram_gen is
constant nrRAMs : integer := width/32;
constant RAMselect_aw : integer := log2(nrRAMs);
constant RAMdepth_aw : integer := log2(depth);
constant total_aw : integer := RAMdepth_aw+RAMselect_aw;
-- total RAM structure signals
signal weA_RAM : std_logic_vector(nrRAMs-1 downto 0);
type wordsplit is array (nrRAMs-1 downto 0) of std_logic_vector(31 downto 0);
signal doutB_RAM : wordsplit;
--- PORT A : 32-bit write | (width)-bit read
signal dinA : std_logic_vector(31 downto 0);
signal doutA : std_logic_vector(width-1 downto 0);
signal weA : std_logic;
signal addrA : std_logic_vector(RAMselect_aw-1 downto 0);
signal op_selA : std_logic_vector(RAMdepth_aw-1 downto 0);
--- PORT B : 32-bit read | (width)-bit write
signal dinB : std_logic_vector(width-1 downto 0);
signal doutB : std_logic_vector(31 downto 0);
signal weB : std_logic;
signal addrB : std_logic_vector(RAMselect_aw-1 downto 0);
signal op_selB : std_logic_vector(RAMdepth_aw-1 downto 0);
signal write_operand_i : std_logic;
signal op_selA_i : std_logic_vector(RAMdepth_aw-1 downto 0);
begin
 
-- WARNING: Very Important!
-- wea & web signals must never be high at the same time !!
-- web has priority
write_operand_i <= write_operand and not write_result; -- portB has write priority
collision <= write_operand and write_result;
-- the dual port ram has a depth of 4 (each layer contains an operand)
-- result is always stored in position 3
-- doutb is always result
with write_operand_i select
op_selA_i <= operand_in_sel when '1',
operand_out_sel when others;
-- map signals to RAM
-- PORTA
weA <= write_operand_i;
op_selA <= op_selA_i;
addrA <= operand_addr;
dinA <= operand_in;
operand_out <= doutA;
-- PORT B
weB <= write_result;
op_selB <= result_dest_op; -- portB locked to result operand
addrB <= operand_addr;
dinB <= result_in;
result_out <= doutB;
-- generate (width/32) blocks of 32-bit ram with a given depth
-- these rams are tyed together to form the following structure
-- True dual port ram:
-- - PORT A : 32-bit write | (width)-bit read
-- - PORT B : 32-bit read | (width)-bit write
-- ^ ^
-- addres addr op_sel
--
ramblocks : for i in 0 to nrRAMs-1 generate
ramblock: tdpram_generic
generic map(
depth => depth
)
port map(
-- port A : 32-bit
clkA => clk,
addrA => op_selA,
weA => weA_RAM(i),
dinA => dinA,
doutA => doutA(((i+1)*32)-1 downto i*32),
-- port B : 32-bit
clkB => clk,
addrB => op_selB,
weB => weB,
dinB => dinB(((i+1)*32)-1 downto i*32),
doutB => doutB_RAM(i)
);
-- demultiplexer for write enable A signal
process (addrA, weA)
begin
if addrA(RAMselect_aw-1 downto 0) = conv_std_logic_vector(i,RAMselect_aw) then
weA_RAM(i) <= weA;
else
weA_RAM(i) <= '0';
end if;
end process;
end generate;
-- PORTB 32-bit read
doutB <= doutB_RAM(conv_integer(addrB)) when (conv_integer(addrB)<nrRAMs)
else (others=>'0');
end Behavioral;

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