OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /
    from Rev 59 to Rev 60
    Reverse comparison

Rev 59 → Rev 60

/mod_sim_exp/trunk/rtl/vhdl/ram/dpram_generic.vhd
6,7 → 6,7
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- behovorial description of a dual port ram with one 32-bit ----
---- behavorial description of a dual port ram with one 32-bit ----
---- write port and one 32-bit read port ----
---- ----
---- Dependencies: none ----
75,9 → 75,13
-- xilinx constraint to use blockram resources
attribute ram_style : string;
attribute ram_style of ram:signal is "block";
-- altera constraint
attribute ramstyle : string;
attribute ramstyle of ram : signal is "M9K, no_rw_check";
-- altera constraints:
-- for smal depths:
-- if the synthesis option : allow any size of RAM to be inferred, is on these lines
-- may be left uncommented.
-- uncomment this attribute if that option is of and you know wich primitives should be used.
--attribute ramstyle : string;
--attribute ramstyle of ram : signal is "M9K, no_rw_check";
begin
process (clk)
begin
/mod_sim_exp/trunk/rtl/vhdl/ram/tdpram_generic.vhd
1,5 → 1,5
----------------------------------------------------------------------
---- dpram_generic ----
---- tdpram_generic ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
6,8 → 6,8
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- behovorial description of a dual port ram with one 32-bit ----
---- write port and one 32-bit read port ----
---- behavorial description of a true dual port ram with 2 ----
---- 32-bit write/read ports ----
---- ----
---- Dependencies: none ----
---- ----
79,9 → 79,13
-- xilinx constraint to use blockram resources
attribute ram_style : string;
attribute ram_style of RAM:variable is "block";
-- altera constraint
-- altera constraints:
-- for smal depths:
-- if the synthesis option : allow any size of RAM to be inferred, is on these lines
-- may be left uncommented.
-- uncomment this attribute if that option is of and you know wich primitives should be used.
--attribute ramstyle : string;
--attribute ramstyle of RAM:variable is "M9K, no_rw_check";
--attribute ramstyle of ram : signal is "M9K, no_rw_check";
begin
-- port A
process (clkA)
/mod_sim_exp/trunk/rtl/vhdl/core/fifo_generic.vhd
53,15 → 53,14
use ieee.std_logic_arith.all;
 
library mod_sim_exp;
use mod_sim_exp.all;
use mod_sim_exp.std_functions.all;
 
entity fifo_generic is
generic (
aw : integer := 6;
depth : integer := 32
);
port (
clk : in std_logic; -- clock input
port (
clk : in std_logic; -- clock input
din : in std_logic_vector (31 downto 0); -- 32 bit input data for push
dout : out std_logic_vector (31 downto 0); -- 32 bit output data for pop
empty : out std_logic; -- empty flag, 1 when FIFO is empty
71,10 → 70,13
reset : in std_logic;
nopop : out std_logic;
nopush : out std_logic
);
);
end fifo_generic;
 
architecture arch of fifo_generic is
-- calculate the width for the address-pointers
constant aw : integer := log2(depth+1);
 
-- read and write pointer
signal rd_addr : std_logic_vector(aw-1 downto 0);
signal wr_addr : std_logic_vector(aw-1 downto 0);
85,10 → 87,6
signal push_i : std_logic;
signal push_i_d : std_logic;
signal pop_i : std_logic;
 
-- the memory
type ram_type is array (depth downto 0) of std_logic_vector (31 downto 0);
signal RAM : ram_type;
begin
empty <= empty_i;
134,14 → 132,19
pop_i <= pop and not empty_i;
-- Block RAM
process (clk)
begin
if (clk'event and clk = '1') then
if (push_i_d = '1') then
RAM(conv_integer(wr_addr)) <= din;
end if;
dout <= RAM(conv_integer(rd_addr));
end if;
end process;
ramblock: entity mod_sim_exp.dpram_generic
generic map(
depth => depth+1
)
port map(
clk => clk,
-- write port
waddr => wr_addr,
we => push_i_d,
din => din,
-- read port
raddr => rd_addr,
dout => dout
);
 
end arch;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.