URL
https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk
Subversion Repositories mod_sim_exp
Compare Revisions
- This comparison shows the changes necessary to convert path
/mod_sim_exp/trunk/bench/vhdl
- from Rev 90 to Rev 94
- ↔ Reverse comparison
Rev 90 → Rev 94
/mod_sim_exp_core_tb.vhd
65,6 → 65,8
architecture test of mod_sim_exp_core_tb is |
constant CLK_PERIOD : time := 10 ns; |
signal clk : std_logic := '0'; |
constant CORE_CLK_PERIOD : time := 4 ns; |
signal core_clk : std_logic := '0'; |
signal reset : std_logic := '1'; |
file input : text open read_mode is "src/sim_input.txt"; |
file output : text open write_mode is "out/sim_output.txt"; |
76,7 → 78,7
constant C_NR_STAGES_TOTAL : integer := 96; |
constant C_NR_STAGES_LOW : integer := 32; |
constant C_SPLIT_PIPELINE : boolean := true; |
constant C_FIFO_DEPTH : integer := 32; -- set to (maximum exponent width)/16 |
constant C_FIFO_AW : integer := 7; -- set to log2( (maximum exponent width)/16 ) |
constant C_MEM_STYLE : string := "asym"; -- xil_prim, generic, asym are valid options |
constant C_FPGA_MAN : string := "xilinx"; -- xilinx, altera are valid options |
|
126,6 → 128,16
end loop; |
end process; |
|
core_clk_process : process |
begin |
while (true) loop |
core_clk <= '0'; |
wait for CORE_CLK_PERIOD/2; |
core_clk <= '1'; |
wait for CORE_CLK_PERIOD/2; |
end loop; |
end process; |
|
------------------------------------------ |
-- Stimulus Process |
------------------------------------------ |
677,13 → 689,14
C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL, |
C_NR_STAGES_LOW => C_NR_STAGES_LOW, |
C_SPLIT_PIPELINE => C_SPLIT_PIPELINE, |
C_FIFO_DEPTH => C_FIFO_DEPTH, |
C_FIFO_AW => C_FIFO_AW, |
C_MEM_STYLE => C_MEM_STYLE, -- xil_prim, generic, asym are valid options |
C_FPGA_MAN => C_FPGA_MAN -- xilinx, altera are valid options |
) |
port map( |
clk => clk, |
reset => reset, |
bus_clk => clk, |
core_clk => core_clk, |
reset => reset, |
-- operand memory interface (plb shared memory) |
write_enable => core_write_enable, |
data_in => core_data_in, |
/axi_tb.vhd
59,6 → 59,7
architecture arch of axi_tb is |
-- constants |
constant CLK_PERIOD : time := 10 ns; |
constant CORE_CLK_PERIOD : time := 4 ns; |
constant C_S_AXI_DATA_WIDTH : integer := 32; |
constant C_S_AXI_ADDR_WIDTH : integer := 32; |
|
71,12 → 72,14
constant C_NR_STAGES_TOTAL : integer := 96; |
constant C_NR_STAGES_LOW : integer := 32; |
constant C_SPLIT_PIPELINE : boolean := true; |
constant C_FIFO_DEPTH : integer := 32; -- set to (maximum exponent width)/16 |
constant C_FIFO_AW : integer := 7; -- set to log2( (maximum exponent width)/16 ) |
constant C_MEM_STYLE : string := "generic"; -- xil_prim, generic, asym are valid options |
constant C_FPGA_MAN : string := "xilinx"; -- xilinx, altera are valid options |
constant C_BASEADDR : std_logic_vector(0 to 31) := x"A0000000"; |
constant C_HIGHADDR : std_logic_vector(0 to 31) := x"A0007FFF"; |
|
|
signal core_clk : std_logic := '0'; |
------------------------- |
-- AXI4lite interface |
------------------------- |
120,8 → 123,18
wait for CLK_PERIOD/2; |
end loop; |
end process; |
|
core_clk_process : process |
begin |
while (true) loop |
core_clk <= '0'; |
wait for CORE_CLK_PERIOD/2; |
core_clk <= '1'; |
wait for CORE_CLK_PERIOD/2; |
end loop; |
end process; |
|
|
|
stim_proc : process |
|
variable Lw : line; |
266,7 → 279,7
C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL, |
C_NR_STAGES_LOW => C_NR_STAGES_LOW, |
C_SPLIT_PIPELINE => C_SPLIT_PIPELINE, |
C_FIFO_DEPTH => C_FIFO_DEPTH, |
C_FIFO_AW => C_FIFO_AW, |
C_MEM_STYLE => C_MEM_STYLE, -- xil_prim, generic, asym are valid options |
C_FPGA_MAN => C_FPGA_MAN, -- xilinx, altera are valid options |
C_BASEADDR => C_BASEADDR, |
274,7 → 287,7
) |
port map( |
--USER ports |
|
core_clk => core_clk, |
------------------------- |
-- AXI4lite interface |
------------------------- |
/msec_axi_tb.vhd
79,8 → 79,8
constant C_NR_STAGES_TOTAL : integer := 96; |
constant C_NR_STAGES_LOW : integer := 32; |
constant C_SPLIT_PIPELINE : boolean := true; |
constant C_FIFO_DEPTH : integer := 32; -- set to (maximum exponent width)/16 |
constant C_MEM_STYLE : string := "generic"; -- xil_prim, generic, asym are valid options |
constant C_FIFO_AW : integer := 7; -- set to log2( (maximum exponent width)/16 ) |
constant C_MEM_STYLE : string := "xil_prim"; -- xil_prim, generic, asym are valid options |
constant C_FPGA_MAN : string := "xilinx"; -- xilinx, altera are valid options |
constant C_BASEADDR : std_logic_vector(0 to 31) := x"A0000000"; |
constant C_HIGHADDR : std_logic_vector(0 to 31) := x"A0007FFF"; |
821,7 → 821,7
C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL, |
C_NR_STAGES_LOW => C_NR_STAGES_LOW, |
C_SPLIT_PIPELINE => C_SPLIT_PIPELINE, |
C_FIFO_DEPTH => C_FIFO_DEPTH, |
C_FIFO_AW => C_FIFO_AW, |
C_MEM_STYLE => C_MEM_STYLE, -- xil_prim, generic, asym are valid options |
C_FPGA_MAN => C_FPGA_MAN, -- xilinx, altera are valid options |
C_BASEADDR => C_BASEADDR, |
831,6 → 831,7
--USER ports |
calc_time => calc_time, |
IntrEvent => IntrEvent, |
core_clk => core_clk, |
------------------------- |
-- AXI4lite interface |
------------------------- |