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    /mod_sim_exp/trunk/rtl/vhdl/core
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Rev 23 → Rev 24

/multiplier_core.vhd File deleted
/mont_ctrl.vhd
52,6 → 52,8
use mod_sim_exp.mod_sim_exp_pkg.all;
 
 
-- This module controls the montgommery mutliplier and controls traffic between
-- RAM and multiplier. Also contains the autorun logic for exponentiations.
entity mont_ctrl is
port (
clk : in std_logic;
78,33 → 80,20
 
 
architecture Behavioral of mont_ctrl is
signal start_delayed_i : std_logic; -- delayed version of start input
signal start_pulse_i : std_logic;
signal auto_start_pulse_i : std_logic;
signal start_d : std_logic; -- delayed version of start input
signal start_pulse : std_logic;
signal auto_start_pulse : std_logic;
signal start_multiplier_i : std_logic;
signal start_up_counter_i : std_logic_vector(2 downto 0) := "100"; -- used in op_sel at multiplier start
signal auto_start_i : std_logic := '0';
signal store_autorun_i : std_logic;
signal run_auto_i : std_logic;
signal run_auto_stored_i : std_logic := '0';
signal single_start_pulse_i : std_logic;
signal start_up_counter : std_logic_vector(2 downto 0) := "100"; -- used in op_sel at multiplier start
 
signal calc_time_i : std_logic; -- high ('1') during multiplication
 
signal x_sel_i : std_logic_vector(1 downto 0); -- the operand used as x input
signal y_sel_i : std_logic_vector(1 downto 0); -- the operand used as y input
signal x_sel_buffer_i : std_logic_vector(1 downto 0); -- x operand as specified by fifo buffer (autorun)
signal x_sel : std_logic_vector(1 downto 0); -- the operand used as x input
signal y_sel : std_logic_vector(1 downto 0); -- the operand used as y input
signal x_sel_buffer : std_logic_vector(1 downto 0); -- x operand as specified by fifo buffer (autorun)
 
signal auto_done_i : std_logic;
signal start_auto_i : std_logic;
signal new_buf_part_i : std_logic;
signal new_buf_word_i : std_logic;
signal buf_part_i : std_logic_vector(3 downto 0);
signal pop_i : std_logic;
signal start_autorun_cycle_i : std_logic;
signal start_autorun_cycle_1_i : std_logic;
signal autorun_counter_i : std_logic_vector(1 downto 0);
signal part_counter_i : std_logic_vector(2 downto 0);
signal auto_done : std_logic;
signal start_auto : std_logic;
signal auto_multiplier_done_i : std_logic;
begin
116,44 → 105,48
START_PULSE_PROC: process(clk)
begin
if rising_edge(clk) then
start_delayed_i <= start;
start_d <= start;
end if;
end process START_PULSE_PROC;
start_pulse_i <= start and (not start_delayed_i);
single_start_pulse_i <= start_pulse_i and (not run_auto_i);
start_auto_i <= start_pulse_i and run_auto_i;
start_pulse <= start and (not start_d);
start_auto <= start_pulse and run_auto;
 
-- to start the multiplier we first need to select the y_operand and
-- clock it in the y_register
-- the we select the x_operand and start the multiplier
-- to start the multiplier we first need to select the x_operand and
-- clock it in the x shift register
-- the we select the y_operand and start the multiplier
-- start_up_counter
-- default state : "100"
-- at start pulse counter resets to 0 and counts up to "100"
START_MULT_PROC: process(clk, reset)
begin
if reset = '1' then
start_up_counter_i <= "100";
start_up_counter <= "100";
elsif rising_edge(clk) then
if start_pulse_i = '1' or auto_start_pulse_i = '1' then
start_up_counter_i <= "000";
elsif start_up_counter_i(2) /= '1' then
start_up_counter_i <= start_up_counter_i + '1';
if start_pulse = '1' or auto_start_pulse = '1' then
start_up_counter <= "000";
elsif start_up_counter(2) /= '1' then
start_up_counter <= start_up_counter + '1';
else
start_up_counter_i <= "100";
start_up_counter <= "100";
end if;
else
start_up_counter_i <= start_up_counter_i;
start_up_counter <= start_up_counter;
end if;
end process;
-- select operands (autorun/single run)
x_sel_i <= x_sel_buffer_i when (run_auto_i = '1') else x_sel_single;
y_sel_i <= "11" when (run_auto_i = '1') else y_sel_single; -- y is operand3 in auto mode
x_sel <= x_sel_buffer when (run_auto = '1') else x_sel_single;
y_sel <= "11" when (run_auto = '1') else y_sel_single; -- y is operand3 in auto mode
-- clock operands to operand_mem output (first y, then x)
with start_up_counter_i(2 downto 1) select
op_sel <= y_sel_i when "00",
x_sel_i when others;
load_x <= start_up_counter_i(0) and (not start_up_counter_i(1));
-- start multiplier
start_multiplier_i <= start_up_counter_i(1) and start_up_counter_i(0);
-- clock operands to operand_mem output (first x, then y)
with start_up_counter(2 downto 1) select
op_sel <= x_sel when "00", -- start_up_counter="00x" (first 2 cycles)
y_sel when others; --
load_x <= start_up_counter(0) and (not start_up_counter(1)); -- latch x operand if start_up_counter="x01"
-- start multiplier when start_up_counter="x11"
start_multiplier_i <= start_up_counter(1) and start_up_counter(0);
start_multiplier <= start_multiplier_i;
 
-- signal calc time is high during multiplication
177,42 → 170,29
-- what happens when a multiplication has finished
load_result <= multiplier_ready;
-- ignore multiplier_ready when in automode, the logic will assert auto_done_i when finished
done <= ((not run_auto_i) and multiplier_ready) or auto_done_i;
-- ignore multiplier_ready when in automode, the logic will assert auto_done when finished
done <= ((not run_auto) and multiplier_ready) or auto_done;
-----------------------------------------------------------------------------------
-- Processes related to op_buffer cntrl and auto_run mode
-- start_auto_i -> start autorun mode operation
-- start_auto -> start autorun mode operation
-- auto_start_pulse <- autorun logic starts the multiplier
-- auto_done <- autorun logic signals when autorun operation has finished
-- x_sel_buffer_i <- autorun logic determines which operand is used as x
-- x_sel_buffer <- autorun logic determines which operand is used as x
-- check buffer empty signal
-----------------------------------------------------------------------------------
-- at the beginning of each new multiplication we store the current autorun bit
-- STORE_AUTORUN_PROC: process(clk)
-- begin
-- if rising_edge(clk) then
-- if store_autorun_i = '1' then
-- run_auto_stored_i <= run_auto;
-- else
-- run_auto_stored_i <= run_auto_stored_i;
-- end if;
-- end if;
-- end process STORE_AUTORUN_PROC;
run_auto_i <= run_auto;
 
-- multiplier_ready is only passed to autorun control when in autorun mode
auto_multiplier_done_i <= (multiplier_ready and run_auto_i);
auto_multiplier_done_i <= (multiplier_ready and run_auto);
autorun_control_logic : autorun_cntrl port map(
clk => clk,
reset => reset,
start => start_auto_i,
done => auto_done_i,
op_sel => x_sel_buffer_i,
start_multiplier => auto_start_pulse_i,
start => start_auto,
done => auto_done,
op_sel => x_sel_buffer,
start_multiplier => auto_start_pulse,
multiplier_done => auto_multiplier_done_i,
read_buffer => read_buffer,
buffer_din => op_sel_buffer,
/mod_sim_exp_pkg.vhd
481,6 → 481,40
);
end component mont_mult_sys_pipeline;
 
--------------------------------------------------------------------
-- mod_sim_exp_core
--------------------------------------------------------------------
-- toplevel of the modular simultaneous exponentiation core
-- contains an operand and modulus ram, multiplier, an exponent fifo
-- and control logic
--
component mod_sim_exp_core is
port(
clk : in std_logic;
reset : in std_logic;
-- operand memory interface (plb shared memory)
write_enable : in std_logic; -- write data to operand ram
data_in : in std_logic_vector (31 downto 0); -- operand ram data in
rw_address : in std_logic_vector (8 downto 0); -- operand ram address bus
data_out : out std_logic_vector (31 downto 0); -- operand ram data out
collision : out std_logic; -- write collision
-- op_sel fifo interface
fifo_din : in std_logic_vector (31 downto 0); -- exponent fifo data in
fifo_push : in std_logic; -- push data in exponent fifo
fifo_full : out std_logic; -- high if fifo is full
fifo_nopush : out std_logic; -- high if error during push
-- control signals
start : in std_logic; -- start multiplication/exponentiation
run_auto : in std_logic; -- single multiplication if low, exponentiation if high
ready : out std_logic; -- calculations done
x_sel_single : in std_logic_vector (1 downto 0); -- single multiplication x operand selection
y_sel_single : in std_logic_vector (1 downto 0); -- single multiplication y operand selection
dest_op_single : in std_logic_vector (1 downto 0); -- result destination operand selection
p_sel : in std_logic_vector (1 downto 0); -- pipeline part selection
calc_time : out std_logic
);
end component mod_sim_exp_core;
 
component autorun_cntrl is
port (
clk : in std_logic;
545,33 → 579,6
);
end component mont_ctrl;
component multiplier_core is
port(
clk : in std_logic;
reset : in std_logic;
-- operand memory interface (plb shared memory)
write_enable : in std_logic;
data_in : in std_logic_vector (31 downto 0);
rw_address : in std_logic_vector (8 downto 0);
data_out : out std_logic_vector (31 downto 0);
collision : out std_logic;
-- op_sel fifo interface
fifo_din : in std_logic_vector (31 downto 0);
fifo_push : in std_logic;
fifo_full : out std_logic;
fifo_nopush : out std_logic;
-- ctrl signals
start : in std_logic;
run_auto : in std_logic;
ready : out std_logic;
x_sel_single : in std_logic_vector (1 downto 0);
y_sel_single : in std_logic_vector (1 downto 0);
dest_op_single : in std_logic_vector (1 downto 0);
p_sel : in std_logic_vector (1 downto 0);
calc_time : out std_logic
);
end component multiplier_core;
component operand_dp is
port (
clka : in std_logic;
/mod_sim_exp_core.vhd
0,0 → 1,194
----------------------------------------------------------------------
---- mod_sim_exp_core ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- toplevel of a modular simultaneous exponentiation core ----
---- using a pipelined montgommery multiplier with split ----
---- pipeline and auto-run support ----
---- ----
---- Dependencies: ----
---- - mont_mult_sys_pipeline ----
---- - operand_mem ----
---- - fifo_primitive ----
---- - mont_ctrl ----
---- ----
---- Authors: ----
---- - Geoffrey Ottoy, DraMCo research group ----
---- - Jonas De Craene, JonasDC@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
library mod_sim_exp;
use mod_sim_exp.mod_sim_exp_pkg.all;
 
-- toplevel of the modular simultaneous exponentiation core
-- contains an operand and modulus ram, multiplier, an exponent fifo
-- and control logic
entity mod_sim_exp_core is
port(
clk : in std_logic;
reset : in std_logic;
-- operand memory interface (plb shared memory)
write_enable : in std_logic; -- write data to operand ram
data_in : in std_logic_vector (31 downto 0); -- operand ram data in
rw_address : in std_logic_vector (8 downto 0); -- operand ram address bus
data_out : out std_logic_vector (31 downto 0); -- operand ram data out
collision : out std_logic; -- write collision
-- op_sel fifo interface
fifo_din : in std_logic_vector (31 downto 0); -- exponent fifo data in
fifo_push : in std_logic; -- push data in exponent fifo
fifo_full : out std_logic; -- high if fifo is full
fifo_nopush : out std_logic; -- high if error during push
-- control signals
start : in std_logic; -- start multiplication/exponentiation
run_auto : in std_logic; -- single multiplication if low, exponentiation if high
ready : out std_logic; -- calculations done
x_sel_single : in std_logic_vector (1 downto 0); -- single multiplication x operand selection
y_sel_single : in std_logic_vector (1 downto 0); -- single multiplication y operand selection
dest_op_single : in std_logic_vector (1 downto 0); -- result destination operand selection
p_sel : in std_logic_vector (1 downto 0); -- pipeline part selection
calc_time : out std_logic
);
end mod_sim_exp_core;
 
 
architecture Structural of mod_sim_exp_core is
constant n : integer := 1536;
constant t : integer := 96;
constant tl : integer := 32;
-- data busses
signal xy : std_logic_vector(n-1 downto 0); -- x and y operand data bus RAM -> multiplier
signal m : std_logic_vector(n-1 downto 0); -- modulus data bus RAM -> multiplier
signal r : std_logic_vector(n-1 downto 0); -- result data bus RAM <- multiplier
-- control signals
signal op_sel : std_logic_vector(1 downto 0); -- operand selection
signal result_dest_op : std_logic_vector(1 downto 0); -- result destination operand
signal mult_ready : std_logic;
signal start_mult : std_logic;
signal load_op : std_logic;
signal load_x : std_logic;
signal load_m : std_logic;
signal load_result : std_logic;
-- fifo signals
signal fifo_empty : std_logic;
signal fifo_pop : std_logic;
signal fifo_nopop : std_logic;
signal fifo_dout : std_logic_vector(31 downto 0);
begin
 
-- The actual multiplier
the_multiplier : mont_mult_sys_pipeline
generic map(
n => n,
nr_stages => t, --(divides n, bits_low & (n-bits_low))
stages_low => tl
)
port map(
core_clk => clk,
xy => xy,
m => m,
r => r,
start => start_mult,
reset => reset,
p_sel => p_sel,
load_x => load_x,
ready => mult_ready
);
 
-- Block ram memory for storing the operands and the modulus
the_memory : operand_mem
port map(
data_in => data_in,
data_out => data_out,
rw_address => rw_address,
op_sel => op_sel,
xy_out => xy,
m => m,
result_in => r,
load_op => load_op,
load_m => load_m,
load_result => load_result,
result_dest_op => result_dest_op,
collision => collision,
clk => clk
);
 
load_op <= write_enable when (rw_address(8) = '0') else '0';
load_m <= write_enable when (rw_address(8) = '1') else '0';
result_dest_op <= dest_op_single when run_auto = '0' else "11"; -- in autorun mode we always store the result in operand3
-- A fifo for auto-run operand selection
the_exponent_fifo : fifo_primitive
port map(
clk => clk,
din => fifo_din,
dout => fifo_dout,
empty => fifo_empty,
full => fifo_full,
push => fifo_push,
pop => fifo_pop,
reset => reset,
nopop => fifo_nopop,
nopush => fifo_nopush
);
-- The control logic for the core
the_control_unit : mont_ctrl
port map(
clk => clk,
reset => reset,
start => start,
x_sel_single => x_sel_single,
y_sel_single => y_sel_single,
run_auto => run_auto,
op_buffer_empty => fifo_empty,
op_sel_buffer => fifo_dout,
read_buffer => fifo_pop,
buffer_noread => fifo_nopop,
done => ready,
calc_time => calc_time,
op_sel => op_sel,
load_x => load_x,
load_result => load_result,
start_multiplier => start_mult,
multiplier_ready => mult_ready
);
 
end Structural;

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