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  • This comparison shows the changes necessary to convert path 
    /mod_sim_exp/trunk/rtl/vhdl/core
    from Rev 36 to Rev 37
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  •

Rev 36 → Rev 37

/sys_pipeline.vhd
58,8 → 58,10
entity sys_pipeline is
generic(
n : integer := 1536; -- width of the operands (# bits)
t : integer := 192; -- total number of stages (divider of n) >= 2
tl : integer := 64 -- lower number of stages (best take t = sqrt(n))
t : integer := 192; -- total number of stages (minimum 2)
tl : integer := 64; -- lower number of stages (minimum 1)
split : boolean := true -- if true the pipeline wil be split in 2 parts,
-- if false there are no lower stages, only t counts
);
port(
-- clock input
82,42 → 84,45
architecture Structural of sys_pipeline is
constant s : integer := n/t;
signal m_i : std_logic_vector(n downto 0);
signal y_i : std_logic_vector(n downto 0);
signal m_i : std_logic_vector(n downto 0);
signal y_i : std_logic_vector(n downto 0);
-- systolic stages signals
signal my_cin_stage : std_logic_vector((t-1) downto 0);
signal my_cout_stage : std_logic_vector((t-1) downto 0);
signal xin_stage : std_logic_vector((t-1) downto 0);
signal qin_stage : std_logic_vector((t-1) downto 0);
signal xout_stage : std_logic_vector((t-1) downto 0);
signal qout_stage : std_logic_vector((t-1) downto 0);
signal a_msb_stage : std_logic_vector((t-1) downto 0);
signal a_0_stage : std_logic_vector((t-1) downto 0);
signal cin_stage : std_logic_vector((t-1) downto 0);
signal cout_stage : std_logic_vector((t-1) downto 0);
signal red_cin_stage : std_logic_vector((t-1) downto 0);
signal red_cout_stage : std_logic_vector((t-1) downto 0);
signal start_stage : std_logic_vector((t-1) downto 0);
signal done_stage : std_logic_vector((t-1) downto 0);
signal r_sel_stage : std_logic_vector((t-1) downto 0);
-- end logic signals
signal r_sel_end : std_logic;
-- signals needed if pipeline is split
---------------------------------------
signal r_sel_l : std_logic;
signal r_sel_h : std_logic;
-- systolic stages signals
signal my_cin_stage : std_logic_vector((t-1) downto 0);
signal my_cout_stage : std_logic_vector((t-1) downto 0);
signal xin_stage : std_logic_vector((t-1) downto 0);
signal qin_stage : std_logic_vector((t-1) downto 0);
signal xout_stage : std_logic_vector((t-1) downto 0);
signal qout_stage : std_logic_vector((t-1) downto 0);
signal a_msb_stage : std_logic_vector((t-1) downto 0);
signal a_0_stage : std_logic_vector((t-1) downto 0);
signal cin_stage : std_logic_vector((t-1) downto 0);
signal cout_stage : std_logic_vector((t-1) downto 0);
signal red_cin_stage : std_logic_vector((t-1) downto 0);
signal red_cout_stage : std_logic_vector((t-1) downto 0);
signal start_stage : std_logic_vector((t-1) downto 0);
signal done_stage : std_logic_vector((t-1) downto 0);
signal r_sel_stage : std_logic_vector((t-1) downto 0);
 
-- mid end signals
signal a_0_midend : std_logic;
-- mid end logic signals
signal a_0_midend : std_logic;
signal r_sel_midend : std_logic;
-- mid start signals
signal my_cout_midstart : std_logic;
signal xout_midstart : std_logic;
signal qout_midstart : std_logic;
signal cout_midstart : std_logic;
signal red_cout_midstart : std_logic;
-- mid start logic signals
signal my_cout_midstart : std_logic;
signal xout_midstart : std_logic;
signal qout_midstart : std_logic;
signal cout_midstart : std_logic;
signal red_cout_midstart : std_logic;
-- end signals
signal r_sel_end : std_logic;
 
begin
 
m_i <= '0' & m;
168,11 → 173,50
red_cout => red_cin_stage(0)
);
-- last cell logic
-------------------
last_cell : sys_last_cell_logic
port map (
core_clk => core_clk,
reset => reset,
a_0 => a_msb_stage(t-1),
cin => cout_stage(t-1),
red_cin => red_cout_stage(t-1),
r_sel => r_sel_end,
start => done_stage(t-1)
);
------------------------------------
-- SINGLE PART PIPELINE CONNECTIONS
------------------------------------
single_pipeline : if split=false generate
-- link stages to eachother
stage_connect : for i in 1 to (t-1) generate
my_cin_stage(i) <= my_cout_stage(i-1);
cin_stage(i) <= cout_stage(i-1);
xin_stage(i) <= xout_stage(i-1);
qin_stage(i) <= qout_stage(i-1);
red_cin_stage(i) <= red_cout_stage(i-1);
start_stage(i) <= done_stage(i-1);
a_msb_stage(i-1) <= a_0_stage(i);
r_sel_stage(i) <= r_sel_end;
end generate;
r_sel_stage(0) <= r_sel_end;
start_stage(0) <= start;
next_x <= done_stage(0);
end generate;
 
----------------------------------------
-- SPLIT PIPELINE CONNECTIONS AND LOGIC
----------------------------------------
split_pipeline : if split=true generate
-- only start first stage if lower part is used
with p_sel select
start_stage(0) <= '0' when "10",
start when others;
-- select start or midstart stage for requesting new xi bit
with p_sel select
next_x <= done_stage(tl) when "10",
done_stage(0) when others;
256,19 → 300,6
r_sel_stage(i) <= r_sel_h;
end generate;
r_sel_stage(tl) <= r_sel_h;
-- last cell logic
-------------------
last_cell : sys_last_cell_logic
port map (
core_clk => core_clk,
reset => reset,
a_0 => a_msb_stage(t-1),
cin => cout_stage(t-1),
red_cin => red_cout_stage(t-1),
r_sel => r_sel_end,
start => done_stage(t-1)
);
with p_sel select
r_sel_l <= r_sel_midend when "01",
278,5 → 309,6
with p_sel select
r_sel_h <= '0' when "01",
r_sel_end when others;
end generate;
 
end Structural;
/mont_multiplier.vhd
65,9 → 65,11
--
entity mont_multiplier is
generic (
n : integer := 1536; -- width of the operands
nr_stages : integer := 96; -- total number of stages
stages_low : integer := 32 -- lower number of stages
n : integer := 1536; -- width of the operands
t : integer := 96; -- total number of stages (minimum 2)
tl : integer := 32; -- lower number of stages (minimum 1)
split : boolean := true -- if true the pipeline wil be split in 2 parts,
-- if false there are no lower stages, only t counts
);
port (
-- clock input
87,9 → 89,7
end mont_multiplier;
 
architecture Structural of mont_multiplier is
constant t : integer := nr_stages;
constant tl : integer := stages_low;
constant s : integer := n/nr_stages; -- stage width (# bits)
constant s : integer := n/t; -- stage width (# bits)
constant nl : integer := s*tl; -- lower pipeline width (# bits)
constant nh : integer := n - nl; -- higher pipeline width (# bits)
96,6 → 96,7
signal reset_multiplier : std_logic;
signal start_multiplier : std_logic;
signal p_sel_i : std_logic_vector(1 downto 0);
signal t_sel : integer range 0 to t; -- width in stages of selected pipeline part
signal n_sel : integer range 0 to n; -- width in bits of selected pipeline part
105,7 → 106,7
signal start_first_stage : std_logic;
begin
 
-- multiplier is reset every calculation or reset
reset_multiplier <= reset or start;
 
123,8 → 124,8
x_selection : x_shift_reg
generic map(
n => n,
t => nr_stages,
tl => stages_low
t => t,
tl => tl
)
port map(
clk => core_clk,
132,10 → 133,23
x_in => xy,
load_x => load_x,
next_x => next_xi,
p_sel => p_sel,
p_sel => p_sel_i,
xi => xi
);
----------------------------------------
-- SINGLE PIPELINE ASSIGNMENTS
----------------------------------------
single_pipeline : if split=false generate
p_sel_i <= "11";
t_sel <= t;
n_sel <= n-1;
end generate;
 
----------------------------------------
-- SPLIT PIPELINE ASSIGNMENTS
----------------------------------------
split_pipeline : if split=true generate
-- this module controls the pipeline operation
-- width in stages for selected pipeline
with p_sel select
149,11 → 163,14
nh-1 when "10", -- higher pipeline part
n-1 when others; -- full pipeline
p_sel_i <= p_sel;
end generate;
 
-- stepping control logic to keep track off the multiplication and when it is done
stepping_control : stepping_logic
generic map(
n => n, -- max nr of steps required to complete a multiplication
t => nr_stages -- total nr of steps in the pipeline
t => t -- total nr of steps in the pipeline
)
port map(
core_clk => core_clk,
168,8 → 185,9
systolic_array : sys_pipeline
generic map(
n => n,
t => nr_stages,
tl => stages_low
t => t,
tl => tl,
split => split
)
port map(
core_clk => core_clk,
179,9 → 197,8
next_x => next_xi,
start => start_first_stage,
reset => reset_multiplier,
p_sel => p_sel,
p_sel => p_sel_i,
r => r
);
end Structural;
 
/mont_mult_sys_pipeline.vhd
68,9 → 68,9
--
entity mont_mult_sys_pipeline is
generic (
n : integer := 1536; -- width of the operands
nr_stages : integer := 96; -- total number of stages
stages_low : integer := 32 -- lower number of stages
n : integer := 1536; -- width of the operands
t : integer := 96; -- total number of stages
tl : integer := 32 -- lower number of stages
);
port (
-- clock input
90,8 → 90,8
end mont_mult_sys_pipeline;
 
architecture Structural of mont_mult_sys_pipeline is
constant stage_width : integer := n/nr_stages;
constant bits_l : integer := stage_width * stages_low;
constant stage_width : integer := n/t;
constant bits_l : integer := stage_width * tl;
constant bits_h : integer := n - bits_l;
 
signal my : std_logic_vector(n downto 0);
117,8 → 117,8
x_selection : x_shift_reg
generic map(
n => n,
t => nr_stages,
tl => stages_low
t => t,
tl => tl
)
port map(
clk => core_clk,
179,8 → 179,8
the_multiplier : systolic_pipeline
generic map(
n => n, -- width of the operands (# bits)
t => nr_stages, -- number of stages (divider of n) >= 2
tl => stages_low
t => t, -- number of stages (divider of n) >= 2
tl => tl
)
port map(
core_clk => core_clk,
/mod_sim_exp_pkg.vhd
49,8 → 49,26
 
 
package mod_sim_exp_pkg is
--------------------------------------------------------------------
------------------------- CORE PARAMETERS --------------------------
--------------------------------------------------------------------
-- These 4 parameters affect core workings
constant nr_bits_total : integer := 1536;
constant nr_stages_total : integer := 96;
constant nr_stages_low : integer := 32;
constant split_pipeline : boolean := true;
-- extra calculated parameters
constant nr_bits_low : integer := (nr_bits_total/nr_stages_total)*nr_stages_low;
constant nr_bits_high : integer := nr_bits_total-nr_bits_low;
constant nr_stages_high : integer := nr_stages_total-nr_stages_low;
--------------------------------------------------------------------
---------------------- COMPONENT DECLARATIONS ----------------------
--------------------------------------------------------------------
--------------------------------------------------------------------
-- d_flip_flop
--------------------------------------------------------------------
-- 1-bit D flip-flop with asynchronous active high reset
460,9 → 478,9
--
component mont_mult_sys_pipeline is
generic (
n : integer := 1536; -- width of the operands
nr_stages : integer := 96; -- total number of stages
stages_low : integer := 32 -- lower number of stages
n : integer := 1536; -- width of the operands
t : integer := 96; -- total number of stages
tl : integer := 32 -- lower number of stages
);
port (
-- clock input
741,8 → 759,10
component sys_pipeline is
generic(
n : integer := 1536; -- width of the operands (# bits)
t : integer := 192; -- total number of stages (divider of n) >= 2
tl : integer := 64 -- lower number of stages (best take t = sqrt(n))
t : integer := 192; -- total number of stages (minimum 2)
tl : integer := 64; -- lower number of stages (minimum 1)
split : boolean := true -- if true the pipeline wil be split in 2 parts,
-- if false there are no lower stages, only t counts
);
port(
-- clock input
764,9 → 784,11
component mont_multiplier is
generic (
n : integer := 1536; -- width of the operands
nr_stages : integer := 96; -- total number of stages
stages_low : integer := 32 -- lower number of stages
n : integer := 1536; -- width of the operands
t : integer := 96; -- total number of stages (minimum 2)
tl : integer := 32; -- lower number of stages (minimum 1)
split : boolean := true -- if true the pipeline wil be split in 2 parts,
-- if false there are no lower stages, only t counts
);
port (
-- clock input
/mod_sim_exp_core.vhd
87,14 → 87,10
 
 
architecture Structural of mod_sim_exp_core is
constant n : integer := 1536;
constant t : integer := 96;
constant tl : integer := 32;
-- data busses
signal xy : std_logic_vector(n-1 downto 0); -- x and y operand data bus RAM -> multiplier
signal m : std_logic_vector(n-1 downto 0); -- modulus data bus RAM -> multiplier
signal r : std_logic_vector(n-1 downto 0); -- result data bus RAM <- multiplier
signal xy : std_logic_vector(nr_bits_total-1 downto 0); -- x and y operand data bus RAM -> multiplier
signal m : std_logic_vector(nr_bits_total-1 downto 0); -- modulus data bus RAM -> multiplier
signal r : std_logic_vector(nr_bits_total-1 downto 0); -- result data bus RAM <- multiplier
-- control signals
signal op_sel : std_logic_vector(1 downto 0); -- operand selection
116,9 → 112,10
-- The actual multiplier
the_multiplier : mont_multiplier
generic map(
n => n,
nr_stages => t, --(divides n, bits_low & (n-bits_low))
stages_low => tl
n => nr_bits_total,
t => nr_stages_total,
tl => nr_stages_low,
split => split_pipeline
)
port map(
core_clk => clk,
135,7 → 132,7
-- Block ram memory for storing the operands and the modulus
the_memory : operand_mem
generic map(
n => n
n => nr_bits_total
)
port map(
data_in => data_in,

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