URL
https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk
Subversion Repositories mod_sim_exp
Compare Revisions
- This comparison shows the changes necessary to convert path
/mod_sim_exp/trunk/rtl/vhdl/core
- from Rev 41 to Rev 43
- ↔ Reverse comparison
Rev 41 → Rev 43
/mod_sim_exp_pkg.vhd
50,21 → 50,6
|
package mod_sim_exp_pkg is |
-------------------------------------------------------------------- |
------------------------- CORE PARAMETERS -------------------------- |
-------------------------------------------------------------------- |
-- These 4 parameters affect core workings |
constant nr_bits_total : integer := 1536; |
constant nr_stages_total : integer := 96; |
constant nr_stages_low : integer := 32; |
constant split_pipeline : boolean := true; |
|
-- extra calculated parameters |
constant nr_bits_low : integer := (nr_bits_total/nr_stages_total)*nr_stages_low; |
constant nr_bits_high : integer := nr_bits_total-nr_bits_low; |
constant nr_stages_high : integer := nr_stages_total-nr_stages_low; |
|
|
-------------------------------------------------------------------- |
---------------------- COMPONENT DECLARATIONS ---------------------- |
-------------------------------------------------------------------- |
|
306,6 → 291,12
-- and control logic |
-- |
component mod_sim_exp_core is |
generic( |
C_NR_BITS_TOTAL : integer := 1536; |
C_NR_STAGES_TOTAL : integer := 96; |
C_NR_STAGES_LOW : integer := 32; |
C_SPLIT_PIPELINE : boolean := true |
); |
port( |
clk : in std_logic; |
reset : in std_logic; |
/mod_sim_exp_core.vhd
59,6 → 59,12
-- contains an operand and modulus ram, multiplier, an exponent fifo |
-- and control logic |
entity mod_sim_exp_core is |
generic( |
C_NR_BITS_TOTAL : integer := 1536; |
C_NR_STAGES_TOTAL : integer := 96; |
C_NR_STAGES_LOW : integer := 32; |
C_SPLIT_PIPELINE : boolean := true |
); |
port( |
clk : in std_logic; |
reset : in std_logic; |
88,9 → 94,9
|
architecture Structural of mod_sim_exp_core is |
-- data busses |
signal xy : std_logic_vector(nr_bits_total-1 downto 0); -- x and y operand data bus RAM -> multiplier |
signal m : std_logic_vector(nr_bits_total-1 downto 0); -- modulus data bus RAM -> multiplier |
signal r : std_logic_vector(nr_bits_total-1 downto 0); -- result data bus RAM <- multiplier |
signal xy : std_logic_vector(C_NR_BITS_TOTAL-1 downto 0); -- x and y operand data bus RAM -> multiplier |
signal m : std_logic_vector(C_NR_BITS_TOTAL-1 downto 0); -- modulus data bus RAM -> multiplier |
signal r : std_logic_vector(C_NR_BITS_TOTAL-1 downto 0); -- result data bus RAM <- multiplier |
|
-- control signals |
signal op_sel : std_logic_vector(1 downto 0); -- operand selection |
110,10 → 116,10
-- The actual multiplier |
the_multiplier : mont_multiplier |
generic map( |
n => nr_bits_total, |
t => nr_stages_total, |
tl => nr_stages_low, |
split => split_pipeline |
n => C_NR_BITS_TOTAL, |
t => C_NR_STAGES_TOTAL, |
tl => C_NR_STAGES_LOW, |
split => C_SPLIT_PIPELINE |
) |
port map( |
core_clk => clk, |
130,7 → 136,7
-- Block ram memory for storing the operands and the modulus |
the_memory : operand_mem |
generic map( |
n => nr_bits_total |
n => C_NR_BITS_TOTAL |
) |
port map( |
data_in => data_in, |