URL
https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk
Subversion Repositories mod_sim_exp
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- This comparison shows the changes necessary to convert path
/mod_sim_exp/trunk/rtl/vhdl/core
- from Rev 8 to Rev 9
- ↔ Reverse comparison
Rev 8 → Rev 9
/cell_1b_adder.vhd
49,24 → 49,26
use ieee.std_logic_unsigned.all; |
|
-- 1-bit full adder cell |
-- for use in the montgommery multiplier systolic array cells |
entity cell_1b_adder is |
port ( |
a : in std_logic; -- adder input operand a |
mux_result : in std_logic; -- adder input muxed result |
cin : in std_logic; -- carry in |
cout : out std_logic; -- carry out |
r : out std_logic -- result out |
-- input operands a, b |
a : in std_logic; |
b : in std_logic; |
-- carry in, out |
cin : in std_logic; |
cout : out std_logic; |
-- result out |
r : out std_logic |
); |
end cell_1b_adder; |
|
|
architecture Behavioral of cell_1b_adder is |
signal a_xor_mux_result : std_logic; |
signal a_xor_b : std_logic; |
begin |
-- 1-bit full adder with combinatorial logic |
-- uses 2 XOR's, 2 AND's and 1 OR port |
a_xor_mux_result <= a xor mux_result; |
r <= a_xor_mux_result xor cin; |
cout <= (a and mux_result) or (cin and a_xor_mux_result); |
a_xor_b <= a xor b; |
r <= a_xor_b xor cin; |
cout <= (a and b) or (cin and a_xor_b); |
end Behavioral; |
/cell_1b.vhd
6,7 → 6,7
---- http://www.opencores.org/cores/mod_sim_exp/ ---- |
---- ---- |
---- Description ---- |
---- 1 bit cell for use in the montgommery multiplier systolic ---- |
---- 1-bit cell for use in the montgommery multiplier systolic ---- |
---- array ---- |
---- ---- |
---- Dependencies: ---- |
52,17 → 52,22
library mod_sim_exp; |
use mod_sim_exp.mod_sim_exp_pkg.all; |
|
|
-- 1-bit cell for the systolic array |
entity cell_1b is |
port ( |
-- operand input bits (m+y, y and m) |
my : in std_logic; |
y : in std_logic; |
m : in std_logic; |
-- operand x input bit and q (serial) |
x : in std_logic; |
q : in std_logic; |
-- previous result input bit |
a : in std_logic; |
-- carry's |
cin : in std_logic; |
cout : out std_logic; |
-- cell result out |
r : out std_logic |
); |
end cell_1b; |
69,9 → 74,11
|
|
architecture Structural of cell_1b is |
-- mux to adder connection |
signal mux2adder : std_logic; |
begin |
|
|
-- mux for my, y and m input bits |
cell_mux : cell_1b_mux |
port map( |
my => my, |
81,14 → 88,15
q => q, |
result => mux2adder |
); |
|
|
-- full adder for a+mux2adder |
cell_adder : cell_1b_adder |
port map( |
a => a, |
mux_result => mux2adder, |
cin => cin, |
cout => cout, |
r => r |
a => a, |
b => mux2adder, |
cin => cin, |
cout => cout, |
r => r |
); |
|
end Structural; |
/mod_sim_exp_pkg.vhd
1,89 → 1,195
---------------------------------------------------------------------- |
---- mod_sim_exp_pkg ---- |
---- ---- |
---- This file is part of the ---- |
---- Modular Simultaneous Exponentiation Core project ---- |
---- http://www.opencores.org/cores/mod_sim_exp/ ---- |
---- ---- |
---- Description ---- |
---- Package for the Modular Simultaneous Exponentiation Core ---- |
---- Project. Contains the component declarations and used ---- |
---- constants. ---- |
---- ---- |
---- Dependencies: none ---- |
---- ---- |
---- Authors: ---- |
---- - Geoffrey Ottoy, DraMCo research group ---- |
---- - Jonas De Craene, JonasDC@opencores.org ---- |
---- ---- |
---------------------------------------------------------------------- |
---- ---- |
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ---- |
---- ---- |
---- This source file may be used and distributed without ---- |
---- restriction provided that this copyright statement is not ---- |
---- removed from the file and that any derivative work contains ---- |
---- the original copyright notice and the associated disclaimer. ---- |
---- ---- |
---- This source file is free software; you can redistribute it ---- |
---- and/or modify it under the terms of the GNU Lesser General ---- |
---- Public License as published by the Free Software Foundation; ---- |
---- either version 2.1 of the License, or (at your option) any ---- |
---- later version. ---- |
---- ---- |
---- This source is distributed in the hope that it will be ---- |
---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- |
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- |
---- PURPOSE. See the GNU Lesser General Public License for more ---- |
---- details. ---- |
---- ---- |
---- You should have received a copy of the GNU Lesser General ---- |
---- Public License along with this source; if not, download it ---- |
---- from http://www.opencores.org/lgpl.shtml ---- |
---- ---- |
---------------------------------------------------------------------- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_unsigned.all; |
|
|
package mod_sim_exp_pkg is |
|
component adder_n is |
generic ( |
width : integer := 1536; |
block_width : integer := 8 |
-- 1-bit D flip-flop with asynchronous active high reset |
component d_flip_flop is |
port( |
core_clk : in std_logic; -- clock signal |
reset : in std_logic; -- active high reset |
din : in std_logic; -- data in |
dout : out std_logic -- data out |
); |
port ( |
core_clk : in std_logic; |
a : in std_logic_vector((width-1) downto 0); |
b : in std_logic_vector((width-1) downto 0); |
cin : in std_logic; |
cout : out std_logic; |
s : out std_logic_vector((width-1) downto 0) |
end component d_flip_flop; |
|
-- 1-bit register with asynchronous reset and clock enable |
component register_1b is |
port( |
core_clk : in std_logic; -- clock input |
ce : in std_logic; -- clock enable (active high) |
reset : in std_logic; -- reset (active high) |
din : in std_logic; -- data in |
dout : out std_logic -- data out |
); |
end component adder_n; |
end component register_1b; |
|
component adder_block is |
generic ( |
width : integer := 32 |
-- n-bit register with asynchronous reset and clock enable |
component register_n is |
generic( |
n : integer := 4 |
); |
port ( |
core_clk : in std_logic; |
a : in std_logic_vector((width-1) downto 0); |
b : in std_logic_vector((width-1) downto 0); |
cin : in std_logic; |
cout : out std_logic; |
s : out std_logic_vector((width-1) downto 0) |
port( |
core_clk : in std_logic; -- clock input |
ce : in std_logic; -- clock enable (active high) |
reset : in std_logic; -- reset (active high) |
din : in std_logic_vector((n-1) downto 0); -- data in (n-bit) |
dout : out std_logic_vector((n-1) downto 0) -- data out (n-bit) |
); |
end component adder_block; |
end component register_n; |
|
component autorun_cntrl is |
port ( |
clk : in std_logic; |
reset : in std_logic; |
start : in std_logic; |
done : out std_logic; |
op_sel : out std_logic_vector (1 downto 0); |
start_multiplier : out std_logic; |
multiplier_done : in std_logic; |
read_buffer : out std_logic; |
buffer_din : in std_logic_vector (31 downto 0); |
buffer_empty : in std_logic |
); |
end component autorun_cntrl; |
|
-- 1-bit full adder cell |
component cell_1b_adder is |
port ( |
a : in std_logic; |
mux_result : in std_logic; |
cin : in std_logic; |
cout : out std_logic; |
r : out std_logic |
-- input operands a, b |
a : in std_logic; |
b : in std_logic; |
-- carry in, out |
cin : in std_logic; |
cout : out std_logic; |
-- result out |
r : out std_logic |
); |
end component cell_1b_adder; |
|
-- 1-bit mux for a standard cell in the montgommery multiplier systolic array |
component cell_1b_mux is |
port ( |
my : in std_logic; |
-- input bits |
my : in std_logic; |
y : in std_logic; |
m : in std_logic; |
-- selection bits |
x : in std_logic; |
q : in std_logic; |
-- mux out |
result : out std_logic |
); |
end component cell_1b_mux; |
|
-- 1-bit cell for the systolic array |
component cell_1b is |
port ( |
-- operand input bits (m+y, y and m) |
my : in std_logic; |
y : in std_logic; |
m : in std_logic; |
-- operand x input bit and q (serial) |
x : in std_logic; |
q : in std_logic; |
-- previous result input bit |
a : in std_logic; |
-- carry's |
cin : in std_logic; |
cout : out std_logic; |
-- cell result out |
r : out std_logic |
); |
end component cell_1b; |
|
-- (width)-bit full adder block using cell_1b_adders |
-- with buffered carry out |
component adder_block is |
generic ( |
width : integer := 32 --adder operand widths |
); |
port ( |
-- clock input |
core_clk : in std_logic; |
-- adder input operands a, b (width)-bit |
a : in std_logic_vector((width-1) downto 0); |
b : in std_logic_vector((width-1) downto 0); |
-- carry in, out |
cin : in std_logic; |
cout : out std_logic; |
-- adder result out (width)-bit |
r : out std_logic_vector((width-1) downto 0) |
); |
end component adder_block; |
|
-- n-bit adder using adder blocks. works in stages, to prevent large |
-- carry propagation |
component adder_n is |
generic ( |
width : integer := 1536; -- adder operands width |
block_width : integer := 8 -- adder blocks size |
); |
port ( |
-- clock input |
core_clk : in std_logic; |
-- adder input operands (width)-bit |
a : in std_logic_vector((width-1) downto 0); |
b : in std_logic_vector((width-1) downto 0); |
-- carry in, out |
cin : in std_logic; |
cout : out std_logic; |
-- adder output result (width)-bit |
r : out std_logic_vector((width-1) downto 0) |
); |
end component adder_n; |
|
component autorun_cntrl is |
port ( |
clk : in std_logic; |
reset : in std_logic; |
start : in std_logic; |
done : out std_logic; |
op_sel : out std_logic_vector (1 downto 0); |
start_multiplier : out std_logic; |
multiplier_done : in std_logic; |
read_buffer : out std_logic; |
buffer_din : in std_logic_vector (31 downto 0); |
buffer_empty : in std_logic |
); |
end component autorun_cntrl; |
|
component counter_sync is |
generic( |
max_value : integer := 1024 |
97,15 → 203,6
); |
end component counter_sync; |
|
component d_flip_flop is |
port( |
core_clk : in std_logic; |
reset : in std_logic; |
din : in std_logic; |
dout : out std_logic |
); |
end component d_flip_flop; |
|
component fifo_primitive is |
port ( |
clk : in std_logic; |
316,29 → 413,6
); |
end component operands_sp; |
|
component register_1b is |
port( |
core_clk : in std_logic; |
ce : in std_logic; |
reset : in std_logic; |
din : in std_logic; |
dout : out std_logic |
); |
end component register_1b; |
|
component register_n is |
generic( |
n : integer := 4 |
); |
port( |
core_clk : in std_logic; |
ce : in std_logic; |
reset : in std_logic; |
din : in std_logic_vector((n-1) downto 0); |
dout : out std_logic_vector((n-1) downto 0) |
); |
end component register_n; |
|
component standard_cell_block is |
generic ( |
width : integer := 16 |
/adder_block.vhd
53,39 → 53,48
library mod_sim_exp; |
use mod_sim_exp.mod_sim_exp_pkg.all; |
|
-- (width)-bit full adder block using cell_1b_adders |
-- with buffered carry out |
entity adder_block is |
generic ( |
width : integer := 32 |
width : integer := 32 --adder operand widths |
); |
port ( |
core_clk : in std_logic; |
a : in std_logic_vector((width-1) downto 0); |
b : in std_logic_vector((width-1) downto 0); |
cin : in std_logic; |
cout : out std_logic; |
s : out std_logic_vector((width-1) downto 0) |
-- clock input |
core_clk : in std_logic; |
-- adder input operands a, b (width)-bit |
a : in std_logic_vector((width-1) downto 0); |
b : in std_logic_vector((width-1) downto 0); |
-- carry in, out |
cin : in std_logic; |
cout : out std_logic; |
-- adder result out (width)-bit |
r : out std_logic_vector((width-1) downto 0) |
); |
end adder_block; |
|
|
architecture Structural of adder_block is |
-- array for the carry bits |
signal carry : std_logic_vector(width downto 0); |
begin |
|
-- carry in |
carry(0) <= cin; |
|
-- structure of (width) cell_1b_adders |
adder_chain : for i in 0 to (width-1) generate |
adders : cell_1b_adder |
port map( |
a => a(i), |
mux_result => b(i), |
cin => carry(i), |
cout => carry(i+1), |
r => s(i) |
a => a(i), |
b => b(i), |
cin => carry(i), |
cout => carry(i+1), |
r => r(i) |
); |
end generate; |
|
delay_1_cycle : d_flip_flop |
|
-- buffer the carry every clock cycle |
carry_reg : d_flip_flop |
port map( |
core_clk => core_clk, |
reset => '0', |
/cell_1b_mux.vhd
6,7 → 6,8
---- http://www.opencores.org/cores/mod_sim_exp/ ---- |
---- ---- |
---- Description ---- |
---- mux for use in the montgommery multiplier systolic array ---- |
---- 1-bit mux for a standard cell in the montgommery ---- |
---- multiplier systolic array ---- |
---- ---- |
---- Dependencies: none ---- |
---- ---- |
46,14 → 47,17
use ieee.std_logic_arith.all; |
use ieee.std_logic_unsigned.all; |
|
|
-- 1-bit mux for a standard cell in the montgommery multiplier systolic array |
entity cell_1b_mux is |
port ( |
my : in std_logic; |
-- input bits |
my : in std_logic; |
y : in std_logic; |
m : in std_logic; |
-- selection bits |
x : in std_logic; |
q : in std_logic; |
-- mux out |
result : out std_logic |
); |
end cell_1b_mux; |
62,9 → 66,9
architecture Behavioral of cell_1b_mux is |
signal sel : std_logic_vector(1 downto 0); |
begin |
|
-- selection bits |
sel <= x & q; |
|
-- multipexer |
with sel select |
result <= my when "11", |
y when "10", |
/adder_n.vhd
7,7 → 7,7
---- ---- |
---- Description ---- |
---- This file contains the implementation of a n-bit adder ---- |
---- using adder_blocks ---- |
---- using adder_blocks, divides the adder in stages ---- |
---- used for the montgommery multiplier pre- and post- ---- |
---- computation adder ---- |
---- ---- |
53,30 → 53,37
library mod_sim_exp; |
use mod_sim_exp.mod_sim_exp_pkg.all; |
|
|
-- n-bit adder using adder blocks. works in stages, to prevent large |
-- carry propagation |
entity adder_n is |
generic ( |
width : integer := 1536; |
block_width : integer := 8 |
width : integer := 1536; -- adder operands width |
block_width : integer := 8 -- adder blocks size |
); |
port ( |
core_clk : in std_logic; |
a : in std_logic_vector((width-1) downto 0); |
b : in std_logic_vector((width-1) downto 0); |
cin : in std_logic; |
cout : out std_logic; |
s : out std_logic_vector((width-1) downto 0) |
-- clock input |
core_clk : in std_logic; |
-- adder input operands (width)-bit |
a : in std_logic_vector((width-1) downto 0); |
b : in std_logic_vector((width-1) downto 0); |
-- carry in, out |
cin : in std_logic; |
cout : out std_logic; |
-- adder output result (width)-bit |
r : out std_logic_vector((width-1) downto 0) |
); |
end adder_n; |
|
|
architecture Structural of adder_n is |
constant nr_of_blocks : integer := width/block_width; |
signal carry : std_logic_vector(nr_of_blocks downto 0); |
constant nr_of_blocks : integer := width/block_width; -- number of blocks/stages in the adder |
signal carry : std_logic_vector(nr_of_blocks downto 0); -- array for the carry bits |
begin |
|
|
-- carry in |
carry(0) <= cin; |
|
-- structure of (nr_of_blocks) adder_blocks |
adder_block_chain : for i in 0 to (nr_of_blocks-1) generate |
adder_blocks : adder_block |
generic map( |
88,10 → 95,11
b => b((((i+1)*block_width)-1) downto (i*block_width)), |
cin => carry(i), |
cout => carry(i+1), |
s => s((((i+1)*block_width)-1) downto (i*block_width)) |
r => r((((i+1)*block_width)-1) downto (i*block_width)) |
); |
end generate; |
|
-- carry out |
cout <= carry(nr_of_blocks); |
|
end Structural; |