URL
https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk
Subversion Repositories mod_sim_exp
Compare Revisions
- This comparison shows the changes necessary to convert path
/mod_sim_exp/trunk/rtl/vhdl/interface/axi
- from Rev 89 to Rev 90
- ↔ Reverse comparison
Rev 89 → Rev 90
/msec_ipcore_axilite.vhd
112,7 → 112,6
--USER ports |
calc_time : out std_logic; |
IntrEvent : out std_logic; |
core_clk : in std_logic; |
------------------------- |
-- AXI4lite interface |
------------------------- |
388,8 → 387,7
C_FPGA_MAN => C_FPGA_MAN |
) |
port map( |
bus_clk => S_AXI_ACLK, |
core_clk => core_clk, |
clk => S_AXI_ACLK, |
reset => reset, |
-- operand memory interface (plb shared memory) |
write_enable => core_write_enable, |