URL
https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk
Subversion Repositories mod_sim_exp
Compare Revisions
- This comparison shows the changes necessary to convert path
/mod_sim_exp/trunk/rtl/vhdl/interface/plb
- from Rev 77 to Rev 84
- ↔ Reverse comparison
Rev 77 → Rev 84
/mod_sim_exp_IPcore.vhd
164,7 → 164,7
C_SPLIT_PIPELINE : boolean := true; |
C_FIFO_DEPTH : integer := 32; |
C_MEM_STYLE : string := "xil_prim"; -- xil_prim, generic, asym are valid options |
C_DEVICE : string := "xilinx"; -- xilinx, altera are valid options |
C_FPGA_MAN : string := "xilinx"; -- xilinx, altera are valid options |
-- ADD USER GENERICS ABOVE THIS LINE --------------- |
|
-- DO NOT EDIT BELOW THIS LINE --------------------- |
582,7 → 582,7
C_SPLIT_PIPELINE => C_SPLIT_PIPELINE, |
C_FIFO_DEPTH => C_FIFO_DEPTH, |
C_MEM_STYLE => C_MEM_STYLE, |
C_DEVICE => C_DEVICE, |
C_FPGA_MAN => C_FPGA_MAN, |
-- MAP USER GENERICS ABOVE THIS LINE --------------- |
|
C_SLV_AWIDTH => USER_SLV_AWIDTH, |
/user_logic.vhd
102,7 → 102,7
C_SPLIT_PIPELINE : boolean := true; |
C_FIFO_DEPTH : integer := 32; |
C_MEM_STYLE : string := "xil_prim"; -- xil_prim, generic, asym are valid options |
C_DEVICE : string := "xilinx"; -- xilinx, altera are valid options |
C_FPGA_MAN : string := "xilinx"; -- xilinx, altera are valid options |
-- ADD USER GENERICS ABOVE THIS LINE --------------- |
|
-- DO NOT EDIT BELOW THIS LINE --------------------- |
408,7 → 408,7
C_SPLIT_PIPELINE => C_SPLIT_PIPELINE, |
C_FIFO_DEPTH => C_FIFO_DEPTH, |
C_MEM_STYLE => C_MEM_STYLE, |
C_DEVICE => C_DEVICE |
C_FPGA_MAN => C_FPGA_MAN |
) |
port map( |
clk => Bus2IP_Clk, |