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Subversion Repositories mod_sim_exp

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  • This comparison shows the changes necessary to convert path 
    /mod_sim_exp/trunk/rtl/vhdl/interface
    from Rev 42 to Rev 43
    ↔ Reverse comparison
  •

Rev 42 → Rev 43

/plb/user_logic.vhd
95,6 → 95,11
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- Multiplier parameters
C_NR_BITS_TOTAL : integer := 1536;
C_NR_STAGES_TOTAL : integer := 96;
C_NR_STAGES_LOW : integer := 32;
C_SPLIT_PIPELINE : boolean := true;
-- ADD USER GENERICS ABOVE THIS LINE ---------------
 
-- DO NOT EDIT BELOW THIS LINE ---------------------
390,30 → 395,38
-- Multiplier core instance
------------------------------------------
the_multiplier: mod_sim_exp_core
port map( clk => Bus2IP_Clk, -- v
reset => Bus2IP_Reset, -- v
-- operand memory interface (plb shared memory)
write_enable => core_write_enable,
data_in => core_data_in,
rw_address => core_rw_address,
data_out => core_data_out,
collision => core_mem_collision, -- v
-- op_sel fifo interface
fifo_din => core_fifo_din,
fifo_push => core_fifo_push,
fifo_full => core_fifo_full, -- v
fifo_nopush => core_fifo_nopush, -- v
-- ctrl signals
start => core_start, -- v
run_auto => core_run_auto, -- v
ready => core_ready, -- v
x_sel_single => core_x_sel_single, -- v
y_sel_single => core_y_sel_single, -- v
dest_op_single => core_dest_op_single, -- v
p_sel => core_p_sel, -- v
calc_time => calc_time -- v
generic map(
C_NR_BITS_TOTAL => C_NR_BITS_TOTAL,
C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL,
C_NR_STAGES_LOW => C_NR_STAGES_LOW,
C_SPLIT_PIPELINE => C_SPLIT_PIPELINE
)
port map(
clk => Bus2IP_Clk,
reset => Bus2IP_Reset,
-- operand memory interface (plb shared memory)
write_enable => core_write_enable,
data_in => core_data_in,
rw_address => core_rw_address,
data_out => core_data_out,
collision => core_mem_collision,
-- op_sel fifo interface
fifo_din => core_fifo_din,
fifo_push => core_fifo_push,
fifo_full => core_fifo_full,
fifo_nopush => core_fifo_nopush,
-- ctrl signals
start => core_start,
run_auto => core_run_auto,
ready => core_ready,
x_sel_single => core_x_sel_single,
y_sel_single => core_y_sel_single,
dest_op_single => core_dest_op_single,
p_sel => core_p_sel,
calc_time => calc_time
);
 
 
------------------------------------------
-- Drive IP to Bus signals
------------------------------------------
/plb/mont_mult1536.vhd
73,8 → 73,8
library plbv46_slave_single_v1_01_a;
use plbv46_slave_single_v1_01_a.plbv46_slave_single;
 
library mont_mult1536_v2_00_a;
use mont_mult1536_v2_00_a.user_logic;
library mod_sim_exp;
use mod_sim_exp.user_logic;
 
------------------------------------------------------------------------------
-- Entity section
157,6 → 157,11
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- Multiplier parameters
C_NR_BITS_TOTAL : integer := 1536;
C_NR_STAGES_TOTAL : integer := 96;
C_NR_STAGES_LOW : integer := 32;
C_SPLIT_PIPELINE : boolean := true;
-- ADD USER GENERICS ABOVE THIS LINE ---------------
 
-- DO NOT EDIT BELOW THIS LINE ---------------------
563,11 → 568,16
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity mont_mult1536_v2_00_a.user_logic
USER_LOGIC_I : entity mod_sim_exp.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- Multiplier parameters
C_NR_BITS_TOTAL => C_NR_BITS_TOTAL,
C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL,
C_NR_STAGES_LOW => C_NR_STAGES_LOW,
C_SPLIT_PIPELINE => C_SPLIT_PIPELINE,
-- MAP USER GENERICS ABOVE THIS LINE ---------------
 
C_SLV_AWIDTH => USER_SLV_AWIDTH,

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