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URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

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  • This comparison shows the changes necessary to convert path
    /mod_sim_exp/trunk/rtl/vhdl/ram
    from Rev 59 to Rev 60
    Reverse comparison

Rev 59 → Rev 60

/dpram_generic.vhd
6,7 → 6,7
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- behovorial description of a dual port ram with one 32-bit ----
---- behavorial description of a dual port ram with one 32-bit ----
---- write port and one 32-bit read port ----
---- ----
---- Dependencies: none ----
75,9 → 75,13
-- xilinx constraint to use blockram resources
attribute ram_style : string;
attribute ram_style of ram:signal is "block";
-- altera constraint
attribute ramstyle : string;
attribute ramstyle of ram : signal is "M9K, no_rw_check";
-- altera constraints:
-- for smal depths:
-- if the synthesis option : allow any size of RAM to be inferred, is on these lines
-- may be left uncommented.
-- uncomment this attribute if that option is of and you know wich primitives should be used.
--attribute ramstyle : string;
--attribute ramstyle of ram : signal is "M9K, no_rw_check";
begin
process (clk)
begin
/tdpram_generic.vhd
1,5 → 1,5
----------------------------------------------------------------------
---- dpram_generic ----
---- tdpram_generic ----
---- ----
---- This file is part of the ----
---- Modular Simultaneous Exponentiation Core project ----
6,8 → 6,8
---- http://www.opencores.org/cores/mod_sim_exp/ ----
---- ----
---- Description ----
---- behovorial description of a dual port ram with one 32-bit ----
---- write port and one 32-bit read port ----
---- behavorial description of a true dual port ram with 2 ----
---- 32-bit write/read ports ----
---- ----
---- Dependencies: none ----
---- ----
79,9 → 79,13
-- xilinx constraint to use blockram resources
attribute ram_style : string;
attribute ram_style of RAM:variable is "block";
-- altera constraint
-- altera constraints:
-- for smal depths:
-- if the synthesis option : allow any size of RAM to be inferred, is on these lines
-- may be left uncommented.
-- uncomment this attribute if that option is of and you know wich primitives should be used.
--attribute ramstyle : string;
--attribute ramstyle of RAM:variable is "M9K, no_rw_check";
--attribute ramstyle of ram : signal is "M9K, no_rw_check";
begin
-- port A
process (clkA)

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