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URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

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  • This comparison shows the changes necessary to convert path 
    /mod_sim_exp/trunk/rtl/vhdl
    from Rev 38 to Rev 39
    ↔ Reverse comparison
  •

Rev 38 → Rev 39

/core/autorun_cntrl.vhd
70,13 → 70,11
signal bit_counter_0_i : std_logic;
signal bit_counter_15_i : std_logic;
signal next_bit_i : std_logic := '0';
signal next_bit_del_i : std_logic;
signal start_cycle_i : std_logic := '0';
signal start_cycle_del_i : std_logic;
signal done_i : std_logic;
signal start_i : std_logic;
signal running_i : std_logic;
signal start_multiplier_i : std_logic;
168,7 → 166,7
end process DEL_PROC;
-- process for delaying signals with 1 clock cycle
CYCLE_CNTR_PROC: process(clk, start)
CYCLE_CNTR_PROC: process(clk, start, reset)
begin
if start = '1' or reset = '1' then
cycle_counter_i <= '0';
/core/mont_ctrl.vhd
66,7 → 66,6
op_buffer_empty : in std_logic;
op_sel_buffer : in std_logic_vector(31 downto 0);
read_buffer : out std_logic;
buffer_noread : in std_logic;
done : out std_logic;
calc_time : out std_logic;
-- multiplier side
130,8 → 129,6
else
start_up_counter <= "100";
end if;
else
start_up_counter <= start_up_counter;
end if;
end process;
162,8 → 159,6
else
calc_time_i <= calc_time_i;
end if;
else
calc_time_i <= calc_time_i;
end if;
end process CALC_TIME_PROC;
calc_time <= calc_time_i;
/core/mod_sim_exp_pkg.vhd
573,6 → 573,12
);
end component modulus_ram;
--------------------------------------------------------------------
-- mont_ctrl
--------------------------------------------------------------------
-- This module controls the montgommery mutliplier and controls traffic between
-- RAM and multiplier. Also contains the autorun logic for exponentiations.
--
component mont_ctrl is
port (
clk : in std_logic;
585,7 → 591,6
op_buffer_empty : in std_logic;
op_sel_buffer : in std_logic_vector(31 downto 0);
read_buffer : out std_logic;
buffer_noread : in std_logic;
done : out std_logic;
calc_time : out std_logic;
-- multiplier side
613,7 → 618,8
end component operand_dp;
component operand_mem is
generic(n : integer := 1536
generic(
n : integer := 1536
);
port(
-- data interface (plb side)
620,6 → 626,7
data_in : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(31 downto 0);
rw_address : in std_logic_vector(8 downto 0);
write_enable : in std_logic;
-- address structure:
-- bit: 8 -> '1': modulus
-- '0': operands
632,9 → 639,7
xy_out : out std_logic_vector((n-1) downto 0);
m : out std_logic_vector((n-1) downto 0);
result_in : in std_logic_vector((n-1) downto 0);
-- control signals
load_op : in std_logic;
load_m : in std_logic;
-- control signals
load_result : in std_logic;
result_dest_op : in std_logic_vector(1 downto 0);
collision : out std_logic;
/core/mod_sim_exp_core.vhd
97,9 → 97,7
signal result_dest_op : std_logic_vector(1 downto 0); -- result destination operand
signal mult_ready : std_logic;
signal start_mult : std_logic;
signal load_op : std_logic;
signal load_x : std_logic;
signal load_m : std_logic;
signal load_result : std_logic;
-- fifo signals
138,20 → 136,17
data_in => data_in,
data_out => data_out,
rw_address => rw_address,
write_enable => write_enable,
op_sel => op_sel,
xy_out => xy,
m => m,
result_in => r,
load_op => load_op,
load_m => load_m,
load_result => load_result,
result_dest_op => result_dest_op,
collision => collision,
clk => clk
);
 
load_op <= write_enable when (rw_address(8) = '0') else '0';
load_m <= write_enable when (rw_address(8) = '1') else '0';
result_dest_op <= dest_op_single when run_auto = '0' else "11"; -- in autorun mode we always store the result in operand3
-- A fifo for auto-run operand selection
181,7 → 176,6
op_buffer_empty => fifo_empty,
op_sel_buffer => fifo_dout,
read_buffer => fifo_pop,
buffer_noread => fifo_nopop,
done => ready,
calc_time => calc_time,
op_sel => op_sel,
/core/counter_sync.vhd
67,7 → 67,7
begin
-- counter process with asynchronous active high reset
count_proc: process(core_clk, ce, reset)
count_proc: process(core_clk, reset)
variable steps_counter : integer range 0 to max_value-1;
begin
if reset = '1' then -- reset counter
/core/sys_last_cell_logic.vhd
68,44 → 68,27
 
 
architecture Behavorial of sys_last_cell_logic is
signal cell_result_high : std_logic_vector(1 downto 0);
signal cell_result_high_reg : std_logic_vector(1 downto 0);
signal red_cout_end : std_logic;
signal cin_reg : std_logic;
begin
 
-- half adder: cout_last_stage + cell_result_high_reg(1)
cell_result_high(0) <= cin xor cell_result_high_reg(1); --result
cell_result_high(1) <= cin and cell_result_high_reg(1); --cout
a_0 <= cell_result_high_reg(0);
a_0 <= cin_reg;
last_reg : register_n
generic map(
width => 2
)
last_reg : register_1b
port map(
core_clk => core_clk,
ce => start,
reset => reset,
din => cell_result_high,
dout => cell_result_high_reg
din => cin,
dout => cin_reg
);
-- reduction, finishing last 2 bits
reduction_adder_a : cell_1b_adder
-- reduction, finishing last bit
reduction_adder : cell_1b_adder
port map(
a => '1', -- for 2s complement of m
b => cell_result_high_reg(0),
b => cin_reg,
cin => red_cin,
cout => red_cout_end
cout => r_sel
);
 
reduction_adder_b : cell_1b_adder
port map(
a => '1', -- for 2s complement of m
b => cell_result_high_reg(1),
cin => red_cout_end,
cout => r_sel
);
end Behavorial;
/core/operand_mem.vhd
54,7 → 54,8
 
 
entity operand_mem is
generic(n : integer := 1536
generic(
n : integer := 1536
);
port(
-- data interface (plb side)
61,6 → 62,7
data_in : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(31 downto 0);
rw_address : in std_logic_vector(8 downto 0);
write_enable : in std_logic;
-- address structure:
-- bit: 8 -> '1': modulus
-- '0': operands
74,8 → 76,6
m : out std_logic_vector((n-1) downto 0);
result_in : in std_logic_vector((n-1) downto 0);
-- control signals
load_op : in std_logic;
load_m : in std_logic;
load_result : in std_logic;
result_dest_op : in std_logic_vector(1 downto 0);
collision : out std_logic;
94,9 → 94,10
signal xy_out_i : std_logic_vector(1535 downto 0);
signal m_i : std_logic_vector(1535 downto 0);
signal result_in_i : std_logic_vector(1535 downto 0);
signal load_op : std_logic;
 
signal m_addr_i : std_logic_vector(5 downto 0);
signal write_m_i : std_logic;
signal load_m : std_logic;
signal m_data_i : std_logic_vector(31 downto 0);
 
begin
113,7 → 114,9
operand_in_sel_i <= rw_address(7 downto 6);
xy_data_i <= data_in;
m_data_i <= data_in;
write_m_i <= load_m;
load_op <= write_enable when (rw_address(8) = '0') else '0';
load_m <= write_enable when (rw_address(8) = '1') else '0';
 
-- xy operand storage
xy_ram : operand_ram
137,7 → 140,7
port map(
clk => clk,
modulus_addr => m_addr_i,
write_modulus => write_m_i,
write_modulus => load_m,
modulus_in => m_data_i,
modulus_out => m_i
);
/core/operand_ram.vhd
86,7 → 86,6
signal doutb0 : std_logic_vector(31 downto 0);
signal doutb1 : std_logic_vector(31 downto 0);
signal doutb2 : std_logic_vector(31 downto 0);
signal doutb3 : std_logic_vector(31 downto 0);
 
begin
 
121,8 → 120,7
with operand_addr(5 downto 4) select
result_out <= doutb0 when "00",
doutb1 when "01",
doutb2 when "10",
doutb3 when others;
doutb2 when others;
-- 3 instances of a dual port ram to store the parts of the operand
op_0 : operand_dp

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