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  • This comparison shows the changes necessary to convert path
    /mod_sim_exp/trunk/rtl/vhdl
    from Rev 60 to Rev 61
    Reverse comparison

Rev 60 → Rev 61

/ram/dpram_generic.vhd
70,7 → 70,7
architecture behavorial of dpram_generic is
-- the memory
type ram_type is array (depth-1 downto 0) of std_logic_vector (31 downto 0);
signal ram : ram_type;
signal RAM : ram_type := (others => (others => '0'));
-- xilinx constraint to use blockram resources
attribute ram_style : string;
77,19 → 77,19
attribute ram_style of ram:signal is "block";
-- altera constraints:
-- for smal depths:
-- if the synthesis option : allow any size of RAM to be inferred, is on these lines
-- may be left uncommented.
-- uncomment this attribute if that option is of and you know wich primitives should be used.
-- if the synthesis option "allow any size of RAM to be inferred" is on, these lines
-- may be left commented.
-- uncomment this attribute if that option is off and you know wich primitives should be used.
--attribute ramstyle : string;
--attribute ramstyle of ram : signal is "M9K, no_rw_check";
--attribute ramstyle of RAM : signal is "M9K, no_rw_check";
begin
process (clk)
begin
if (clk'event and clk = '1') then
if (we = '1') then
ram(conv_integer(waddr)) <= din;
RAM(conv_integer(waddr)) <= din;
end if;
dout <= ram(conv_integer(raddr));
dout <= RAM(conv_integer(raddr));
end if;
end process;
end behavorial;
/ram/tdpram_generic.vhd
59,15 → 59,15
-- port A
clkA : in std_logic;
addrA : in std_logic_vector(log2(depth)-1 downto 0);
weA : in std_logic;
dinA : in std_logic_vector(31 downto 0);
doutA : out std_logic_vector(31 downto 0);
weA : in std_logic;
dinA : in std_logic_vector(31 downto 0);
doutA : out std_logic_vector(31 downto 0);
-- port B
clkB : in std_logic;
addrB : in std_logic_vector(log2(depth)-1 downto 0);
weB : in std_logic;
dinB : in std_logic_vector(31 downto 0);
doutB : out std_logic_vector(31 downto 0)
weB : in std_logic;
dinB : in std_logic_vector(31 downto 0);
doutB : out std_logic_vector(31 downto 0)
);
end tdpram_generic;
 
74,7 → 74,7
architecture behavorial of tdpram_generic is
-- the memory
type ram_type is array (depth-1 downto 0) of std_logic_vector (31 downto 0);
shared variable RAM: ram_type;
shared variable RAM: ram_type := (others => (others => '0'));
-- xilinx constraint to use blockram resources
attribute ram_style : string;
81,11 → 81,11
attribute ram_style of RAM:variable is "block";
-- altera constraints:
-- for smal depths:
-- if the synthesis option : allow any size of RAM to be inferred, is on these lines
-- may be left uncommented.
-- uncomment this attribute if that option is of and you know wich primitives should be used.
-- if the synthesis option "allow any size of RAM to be inferred" is on, these lines
-- may be left commented.
-- uncomment this attribute if that option is off and you know wich primitives should be used.
--attribute ramstyle : string;
--attribute ramstyle of ram : signal is "M9K, no_rw_check";
--attribute ramstyle of RAM : signal is "M9K, no_rw_check";
begin
-- port A
process (clkA)

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