Synthesis Report
di 26. feb 15:21:57 2013

Release 12.4 - xst M.81d (nt)
Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.11 secs
 
--> Parameter xsthdpdir set to xst


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.11 secs
 
--> Reading design: mod_sim_exp_core.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Parsing
  3) HDL Elaboration
  4) HDL Synthesis
       4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
       5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Partition Report
  8) Design Summary
       8.1) Primitive and Black Box Usage
       8.2) Device utilization summary
       8.3) Partition Resource Summary
       8.4) Timing Report
            8.4.1) Clock Information
            8.4.2) Asynchronous Control Signals Information
            8.4.3) Timing Summary
            8.4.4) Timing Details
            8.4.5) Cross Clock Domains Report


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "mod_sim_exp_core.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "mod_sim_exp_core"
Output Format                      : NGC
Target Device                      : xc6vlx240t-1-ff1156

---- Source Options
Top Module Name                    : mod_sim_exp_core
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : LUT
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Shift Register Extraction          : YES
ROM Style                          : Auto
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Shift Register Minimum Size        : 2
Use DSP Block                      : Auto
Automatic Register Balancing       : No

---- Target Options
LUT Combining                      : Auto
Reduce Control Sets                : Auto
Add IO Buffers                     : NO
Global Maximum Fanout              : 100000
Add Generic Clock Buffer(BUFG)     : 32
Register Duplication               : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Auto
Use Synchronous Set                : Auto
Use Synchronous Reset              : Auto
Pack IO Registers into IOBs        : Auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Area
Optimization Effort                : 2
Power Reduction                    : NO
Keep Hierarchy                     : No
Netlist Hierarchy                  : As_Optimized
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : Maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
DSP48 Utilization Ratio            : 100
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

---- Other Options
Cores Search Directories           : {"../../SVN/mod_sim_exp/rtl/vhdl/core"  }

=========================================================================


=========================================================================
*                          HDL Parsing                                  *
=========================================================================
Analyzing Verilog file \"\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/operand_dp.v\" into library work
Parsing module .
Analyzing Verilog file \"\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/operands_sp.v\" into library work
Parsing module .
Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/std_functions.vhd" into library mod_sim_exp
Parsing package .
Parsing package body .
Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/mod_sim_exp_pkg.vhd" into library mod_sim_exp
Parsing package .
Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/cell_1b_mux.vhd" into library mod_sim_exp
Parsing entity .
Parsing architecture  of entity .
Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/cell_1b_adder.vhd" into library mod_sim_exp
Parsing entity .
Parsing architecture  of entity .
Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/d_flip_flop.vhd" into library mod_sim_exp
Parsing entity .
Parsing architecture  of entity .
Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/cell_1b.vhd" into library mod_sim_exp
Parsing entity .
Parsing architecture  of entity .
Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/standard_cell_block.vhd" into library mod_sim_exp
Parsing entity .
Parsing architecture  of entity .
Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/register_n.vhd" into library mod_sim_exp
Parsing entity .
Parsing architecture  of entity .
Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/register_1b.vhd" into library mod_sim_exp
Parsing entity .
Parsing architecture  of entity .
Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/adder_block.vhd" into library mod_sim_exp
Parsing entity .
Parsing architecture  of entity .
Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/sys_stage.vhd" into library mod_sim_exp
Parsing entity .
Parsing architecture  of entity .
Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/sys_last_cell_logic.vhd" into library mod_sim_exp
Parsing entity .
Parsing architecture  of entity .
Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/sys_first_cell_logic.vhd" into library mod_sim_exp
Parsing entity .
Parsing architecture  of entity .
Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/counter_sync.vhd" into library mod_sim_exp
Parsing entity .
Parsing architecture  of entity .
Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/x_shift_reg.vhd" into library mod_sim_exp
Parsing entity .
Parsing architecture  of entity .
Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/sys_pipeline.vhd" into library mod_sim_exp
Parsing entity .
Parsing architecture  of entity .
Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/stepping_logic.vhd" into library mod_sim_exp
Parsing entity .
Parsing architecture  of entity .
Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/operand_ram.vhd" into library mod_sim_exp
Parsing entity .
Parsing architecture  of entity .
Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/modulus_ram.vhd" into library mod_sim_exp
Parsing entity .
Parsing architecture  of entity .
Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/autorun_cntrl.vhd" into library mod_sim_exp
Parsing entity .
Parsing architecture  of entity .
Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/operand_mem.vhd" into library mod_sim_exp
Parsing entity .
Parsing architecture  of entity .
Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/mont_multiplier.vhd" into library mod_sim_exp
Parsing entity .
Parsing architecture  of entity .
Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/mont_ctrl.vhd" into library mod_sim_exp
Parsing entity .
Parsing architecture  of entity .
Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/fifo_primitive.vhd" into library mod_sim_exp
Parsing entity .
Parsing architecture  of entity .
Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/mod_sim_exp_core.vhd" into library mod_sim_exp
Parsing entity .
Parsing architecture  of entity .

=========================================================================
*                            HDL Elaboration                            *
=========================================================================

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) from library .

Elaborating entity  (architecture ) from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) from library .

Elaborating entity  (architecture ) from library .

Elaborating entity  (architecture ) from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) from library .
WARNING:HDLCompiler:89 - "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/mod_sim_exp_pkg.vhd" Line 475:  remains a black-box since it has no binding entity.

Elaborating entity  (architecture ) from library .
WARNING:HDLCompiler:89 - "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/mod_sim_exp_pkg.vhd" Line 495:  remains a black-box since it has no binding entity.

Elaborating entity  (architecture ) from library .

Elaborating entity  (architecture ) from library .

Elaborating entity  (architecture ) from library .

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit .
    Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/mod_sim_exp_core.vhd".
        C_NR_BITS_TOTAL = 1536
        C_NR_STAGES_TOTAL = 96
        C_NR_STAGES_LOW = 32
        C_SPLIT_PIPELINE = true
        C_NR_OP = 4
        C_NR_M = 2
        C_FIFO_DEPTH = 32
INFO:Xst:3010 - "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/mod_sim_exp_core.vhd" line 167: Output port  of the instance  is unconnected or connected to loadless signal.
    Summary:
	inferred   1 Multiplexer(s).
Unit  synthesized.

Synthesizing Unit .
    Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/mont_multiplier.vhd".
        n = 1536
        t = 96
        tl = 32
        split = true
    Found 4x18-bit Read Only RAM for signal <_n0015>
    Summary:
	inferred   1 RAM(s).
Unit  synthesized.

Synthesizing Unit .
    Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/d_flip_flop.vhd".
    Found 1-bit register for signal .
    Summary:
	inferred   1 D-type flip-flop(s).
Unit  synthesized.

Synthesizing Unit .
    Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/x_shift_reg.vhd".
        n = 1536
        t = 96
        tl = 32
    Found 1536-bit register for signal .
    Summary:
	inferred 1536 D-type flip-flop(s).
	inferred 1536 Multiplexer(s).
Unit  synthesized.

Synthesizing Unit .
    Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/stepping_logic.vhd".
        n = 1536
        t = 96
    Summary:
	no macro.
Unit  synthesized.

Synthesizing Unit .
    Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/counter_sync.vhd".
        max_value = 96
    Found 7-bit register for signal .
    Found 1-bit register for signal .
    Found 7-bit adder for signal  created at line 83.
    Found 32-bit subtractor for signal > created at line 79.
    Found 32-bit comparator equal for signal  created at line 79
    Summary:
	inferred   2 Adder/Subtractor(s).
	inferred   8 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred   2 Multiplexer(s).
Unit  synthesized.

Synthesizing Unit .
    Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/counter_sync.vhd".
        max_value = 1536
    Found 11-bit register for signal .
    Found 1-bit register for signal .
    Found 11-bit adder for signal  created at line 83.
    Found 32-bit subtractor for signal > created at line 79.
    Found 32-bit comparator equal for signal  created at line 79
    Summary:
	inferred   2 Adder/Subtractor(s).
	inferred  12 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred   2 Multiplexer(s).
Unit  synthesized.

Synthesizing Unit .
    Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/counter_sync.vhd".
        max_value = 2
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit adder for signal > created at line 83.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred   2 D-type flip-flop(s).
	inferred   2 Multiplexer(s).
Unit  synthesized.

Synthesizing Unit .
    Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/sys_pipeline.vhd".
        n = 1536
        t = 96
        tl = 32
        split = true
INFO:Xst:3010 - "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/sys_pipeline.vhd" line 133: Output port  of the instance  is unconnected or connected to loadless signal.
INFO:Xst:3010 - "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/sys_pipeline.vhd" line 133: Output port  of the instance  is unconnected or connected to loadless signal.
INFO:Xst:3010 - "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/sys_pipeline.vhd" line 133: Output port  of the instance  is unconnected or connected to loadless signal.
    Found 1-bit 3-to-1 multiplexer for signal > created at line 270.
    Found 1-bit 4-to-1 multiplexer for signal  created at line 304.
    Summary:
	inferred  11 Multiplexer(s).
Unit  synthesized.

Synthesizing Unit .
    Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/sys_stage.vhd".
        width = 16
    Summary:
	inferred   1 Multiplexer(s).
Unit  synthesized.

Synthesizing Unit .
    Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/adder_block.vhd".
        width = 16
    Summary:
	no macro.
Unit  synthesized.

Synthesizing Unit .
    Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/cell_1b_adder.vhd".
    Summary:
Unit  synthesized.

Synthesizing Unit .
    Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/standard_cell_block.vhd".
        width = 16
    Summary:
	no macro.
Unit  synthesized.

Synthesizing Unit .
    Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/cell_1b.vhd".
    Summary:
	no macro.
Unit  synthesized.

Synthesizing Unit .
    Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/cell_1b_mux.vhd".
    Found 1-bit 4-to-1 multiplexer for signal  created at line 72.
    Summary:
	inferred   1 Multiplexer(s).
Unit  synthesized.

Synthesizing Unit .
    Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/register_n.vhd".
        width = 16
    Found 16-bit register for signal .
    Summary:
	inferred  16 D-type flip-flop(s).
Unit  synthesized.

Synthesizing Unit .
    Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/register_1b.vhd".
    Found 1-bit register for signal .
    Summary:
	inferred   1 D-type flip-flop(s).
Unit  synthesized.

Synthesizing Unit .
    Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/sys_first_cell_logic.vhd".
    Summary:
Unit  synthesized.

Synthesizing Unit .
    Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/sys_last_cell_logic.vhd".
INFO:Xst:3010 - "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/sys_last_cell_logic.vhd" line 86: Output port  of the instance  is unconnected or connected to loadless signal.
    Summary:
	no macro.
Unit  synthesized.

Synthesizing Unit .
    Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/operand_mem.vhd".
        n = 1536
    Summary:
	inferred   2 Multiplexer(s).
Unit  synthesized.

Synthesizing Unit .
    Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/operand_ram.vhd".
    Found 32-bit 3-to-1 multiplexer for signal  created at line 120.
    Summary:
	inferred   3 Multiplexer(s).
Unit  synthesized.

Synthesizing Unit .
    Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/modulus_ram.vhd".
    Summary:
	inferred   1 Multiplexer(s).
Unit  synthesized.

Synthesizing Unit .
    Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/fifo_primitive.vhd".
    Found 1-bit register for signal .
    Found 2-bit register for signal .
    Found 2-bit subtractor for signal > created at line 100.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred   3 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit  synthesized.

Synthesizing Unit .
    Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/mont_ctrl.vhd".
    Found 3-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 3-bit adder for signal  created at line 128.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred   5 D-type flip-flop(s).
	inferred   5 Multiplexer(s).
Unit  synthesized.

Synthesizing Unit .
    Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/autorun_cntrl.vhd".
    Found 4-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 4-bit subtractor for signal > created at line 113.
    Found 1-bit 16-to-1 multiplexer for signal  created at line 122.
    Found 1-bit 16-to-1 multiplexer for signal  created at line 123.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred   9 D-type flip-flop(s).
	inferred   7 Multiplexer(s).
Unit  synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# RAMs                                                 : 1
 4x18-bit single-port Read Only RAM                    : 1
# Adders/Subtractors                                   : 8
 1-bit adder                                           : 1
 11-bit adder                                          : 1
 2-bit subtractor                                      : 1
 3-bit adder                                           : 1
 32-bit subtractor                                     : 2
 4-bit subtractor                                      : 1
 7-bit adder                                           : 1
# Registers                                            : 695
 1-bit register                                        : 593
 11-bit register                                       : 1
 1536-bit register                                     : 1
 16-bit register                                       : 96
 2-bit register                                        : 1
 3-bit register                                        : 1
 4-bit register                                        : 1
 7-bit register                                        : 1
# Comparators                                          : 2
 32-bit comparator equal                               : 2
# Multiplexers                                         : 3207
 1-bit 16-to-1 multiplexer                             : 2
 1-bit 2-to-1 multiplexer                              : 1553
 1-bit 3-to-1 multiplexer                              : 1
 1-bit 4-to-1 multiplexer                              : 1539
 11-bit 2-to-1 multiplexer                             : 1
 16-bit 2-to-1 multiplexer                             : 96
 2-bit 2-to-1 multiplexer                              : 6
 3-bit 2-to-1 multiplexer                              : 2
 32-bit 3-to-1 multiplexer                             : 1
 4-bit 2-to-1 multiplexer                              : 4
 6-bit 2-to-1 multiplexer                              : 1
 7-bit 2-to-1 multiplexer                              : 1
# Xors                                                 : 9224
 1-bit xor2                                            : 9224

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Reading core <../../SVN/mod_sim_exp/rtl/vhdl/core/operand_dp.ngc>.
Reading core <../../SVN/mod_sim_exp/rtl/vhdl/core/operands_sp.ngc>.
Loading core  for timing and area information for instance .
Loading core  for timing and area information for instance .
Loading core  for timing and area information for instance .
Loading core  for timing and area information for instance .
Loading core  for timing and area information for instance .
Loading core  for timing and area information for instance .
WARNING:Xst:1290 - Hierarchical block  is unconnected in block .
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block  is unconnected in block .
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block  is unconnected in block .
   It will be removed from the design.

Synthesizing (advanced) Unit .
The following registers are absorbed into counter : 1 register on signal .
Unit  synthesized (advanced).

Synthesizing (advanced) Unit .
The following registers are absorbed into counter : 1 register on signal .
Unit  synthesized (advanced).

Synthesizing (advanced) Unit .
The following registers are absorbed into counter : 1 register on signal .
Unit  synthesized (advanced).

Synthesizing (advanced) Unit .
INFO:Xst:3031 - HDL ADVISOR - The RAM  will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 4-word x 18-bit                     |          |
    |     weA            | connected to signal            | high     |
    |     addrA          | connected to signal          |          |
    |     diA            | connected to signal            |          |
    |     doA            | connected to signal          |          |
    -----------------------------------------------------------------------
Unit  synthesized (advanced).

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# RAMs                                                 : 1
 4x18-bit single-port distributed Read Only RAM        : 1
# Adders/Subtractors                                   : 5
 2-bit subtractor                                      : 1
 3-bit adder                                           : 1
 32-bit subtractor                                     : 2
 4-bit subtractor                                      : 1
# Counters                                             : 3
 1-bit up counter                                      : 1
 11-bit up counter                                     : 1
 7-bit up counter                                      : 1
# Registers                                            : 3673
 Flip-Flops                                            : 3673
# Comparators                                          : 2
 32-bit comparator equal                               : 2
# Multiplexers                                         : 3202
 1-bit 16-to-1 multiplexer                             : 2
 1-bit 2-to-1 multiplexer                              : 1552
 1-bit 3-to-1 multiplexer                              : 1
 1-bit 4-to-1 multiplexer                              : 1539
 16-bit 2-to-1 multiplexer                             : 96
 2-bit 2-to-1 multiplexer                              : 4
 3-bit 2-to-1 multiplexer                              : 2
 32-bit 3-to-1 multiplexer                             : 1
 4-bit 2-to-1 multiplexer                              : 4
 6-bit 2-to-1 multiplexer                              : 1
# Xors                                                 : 9224
 1-bit xor2                                            : 9224

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit  ...

Optimizing unit  ...

Optimizing unit  ...

Optimizing unit  ...

Optimizing unit  ...

Optimizing unit  ...

Optimizing unit  ...

Optimizing unit  ...

Optimizing unit  ...

Optimizing unit  ...

Optimizing unit  ...

Optimizing unit  ...

Optimizing unit  ...
WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
WARNING:Xst:2677 - Node  of sequential type is unconnected in block .

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block mod_sim_exp_core, actual ratio is 7.

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 3689
 Flip-Flops                                            : 3689

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Design Summary                             *
=========================================================================

Top Level Output File Name         : mod_sim_exp_core.ngc

Primitive and Black Box Usage:
------------------------------
# BELS                             : 10150
#      GND                         : 7
#      INV                         : 1
#      LUT2                        : 14
#      LUT3                        : 788
#      LUT4                        : 799
#      LUT5                        : 3883
#      LUT6                        : 3864
#      MUXCY                       : 10
#      MUXF7                       : 762
#      MUXF8                       : 2
#      VCC                         : 7
#      XORCY                       : 13
# FlipFlops/Latches                : 3689
#      FD                          : 4
#      FDC                         : 1832
#      FDCE                        : 1845
#      FDP                         : 4
#      FDPE                        : 4
# RAMS                             : 97
#      FIFO18E1                    : 1
#      RAMB36E1                    : 96

Device utilization summary:
---------------------------

Selected Device : 6vlx240tff1156-1 


Slice Logic Utilization: 
 Number of Slice Registers:            3689  out of  301440     1%  
 Number of Slice LUTs:                 9349  out of  150720     6%  
    Number used as Logic:              9349  out of  150720     6%  

Slice Logic Distribution: 
 Number of LUT Flip Flop pairs used:   9490
   Number with an unused Flip Flop:    5801  out of   9490    61%  
   Number with an unused LUT:           141  out of   9490     1%  
   Number of fully used LUT-FF pairs:  3548  out of   9490    37%  
   Number of unique control sets:       108

IO Utilization: 
 Number of IOs:                         124
 Number of bonded IOBs:                   0  out of    600     0%  

Specific Feature Utilization:
 Number of Block RAM/FIFO:               97  out of    416    23%  
    Number using Block RAM only:         96
    Number using FIFO only:               1

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
Timing Report

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+----------------------------------------+-------+
Clock Signal                       | Clock buffer(FF name)                  | Load  |
-----------------------------------+----------------------------------------+-------+
clk                                | NONE(the_multiplier/delay_1_cycle/dout)| 3786  |
-----------------------------------+----------------------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:
----------------------------------------
---------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+-------+
Control Signal                                                                   | Buffer(FF name)                                                                                                          | Load  |
---------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+-------+
the_memory/m_ram/modulus_0/BU2/doutb(0)(the_memory/m_ram/modulus_0/BU2/XST_GND:G)| NONE(the_memory/m_ram/modulus_0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SP.SIMPLE_PRIM36.ram) | 32    |
the_memory/m_ram/modulus_1/BU2/doutb(0)(the_memory/m_ram/modulus_1/BU2/XST_GND:G)| NONE(the_memory/m_ram/modulus_1/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SP.SIMPLE_PRIM36.ram) | 32    |
the_memory/m_ram/modulus_2/BU2/doutb(0)(the_memory/m_ram/modulus_2/BU2/XST_GND:G)| NONE(the_memory/m_ram/modulus_2/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SP.SIMPLE_PRIM36.ram) | 32    |
the_memory/xy_ram/op_0/BU2/rdaddrecc(0)(the_memory/xy_ram/op_0/BU2/XST_GND:G)    | NONE(the_memory/xy_ram/op_0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/TRUE_DP.SIMPLE_PRIM36.ram)| 32    |
the_memory/xy_ram/op_1/BU2/rdaddrecc(0)(the_memory/xy_ram/op_1/BU2/XST_GND:G)    | NONE(the_memory/xy_ram/op_1/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/TRUE_DP.SIMPLE_PRIM36.ram)| 32    |
the_memory/xy_ram/op_2/BU2/rdaddrecc(0)(the_memory/xy_ram/op_2/BU2/XST_GND:G)    | NONE(the_memory/xy_ram/op_2/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/TRUE_DP.SIMPLE_PRIM36.ram)| 32    |
---------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+-------+

Timing Summary:
---------------
Speed Grade: -1

   Minimum period: 5.964ns (Maximum Frequency: 167.673MHz)
   Minimum input arrival time before clock: 5.340ns
   Maximum output required time after clock: 3.208ns
   Maximum combinational path delay: 1.410ns

Timing Details:
---------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 5.964ns (frequency: 167.673MHz)
  Total number of paths / destination ports: 123290 / 9692
-------------------------------------------------------------------------
Delay:               5.964ns (Levels of Logic = 10)
  Source:            the_multiplier/systolic_array/pipeline_stages[31].stage/reduction_adder/carry_reg/dout (FF)
  Destination:       the_memory/xy_ram/op_1/BU2/U0/blk_mem_generator/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/TRUE_DP.SIMPLE_PRIM36.ram (RAM)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: the_multiplier/systolic_array/pipeline_stages[31].stage/reduction_adder/carry_reg/dout to the_memory/xy_ram/op_1/BU2/U0/blk_mem_generator/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/TRUE_DP.SIMPLE_PRIM36.ram
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              3   0.375   0.431  the_multiplier/systolic_array/pipeline_stages[31].stage/reduction_adder/carry_reg/dout (the_multiplier/systolic_array/pipeline_stages[31].stage/reduction_adder/carry_reg/dout)
     LUT3:I2->O            2   0.068   0.423  the_multiplier/systolic_array/Mmux_red_cin_stage<32>11 (the_multiplier/systolic_array/red_cin_stage<32>)
     LUT5:I4->O            3   0.068   0.431  the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/adder_chain[1].adders/cout1 (the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/carry<2>)
     LUT5:I4->O            3   0.068   0.431  the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/adder_chain[3].adders/cout1 (the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/carry<4>)
     LUT5:I4->O            3   0.068   0.431  the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/adder_chain[5].adders/cout1 (the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/carry<6>)
     LUT5:I4->O            3   0.068   0.431  the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/adder_chain[7].adders/cout1 (the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/carry<8>)
     LUT5:I4->O            3   0.068   0.431  the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/adder_chain[9].adders/cout1 (the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/carry<10>)
     LUT5:I4->O            3   0.068   0.431  the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/adder_chain[11].adders/cout1 (the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/carry<12>)
     LUT5:I4->O            3   0.068   0.431  the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/adder_chain[13].adders/cout1 (the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/carry<14>)
     LUT4:I3->O            1   0.068   0.399  the_multiplier/systolic_array/pipeline_stages[32].stage/Mmux_r61 (r<526>)
     begin scope: 'the_memory/xy_ram/op_1'
     begin scope: 'BU2'
     RAMB36E1:DIBDI0           0.707          U0/blk_mem_generator/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/TRUE_DP.SIMPLE_PRIM36.ram
    ----------------------------------------
    Total                      5.964ns (1.694ns logic, 4.270ns route)
                                       (28.4% logic, 71.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
  Total number of paths / destination ports: 15286 / 8029
-------------------------------------------------------------------------
Offset:              5.340ns (Levels of Logic = 10)
  Source:            p_sel<1> (PAD)
  Destination:       the_memory/xy_ram/op_1/BU2/U0/blk_mem_generator/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/TRUE_DP.SIMPLE_PRIM36.ram (RAM)
  Destination Clock: clk rising

  Data Path: p_sel<1> to the_memory/xy_ram/op_1/BU2/U0/blk_mem_generator/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/TRUE_DP.SIMPLE_PRIM36.ram
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LUT3:I0->O            2   0.068   0.423  the_multiplier/systolic_array/Mmux_red_cin_stage<32>11 (the_multiplier/systolic_array/red_cin_stage<32>)
     LUT5:I4->O            3   0.068   0.431  the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/adder_chain[1].adders/cout1 (the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/carry<2>)
     LUT5:I4->O            3   0.068   0.431  the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/adder_chain[3].adders/cout1 (the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/carry<4>)
     LUT5:I4->O            3   0.068   0.431  the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/adder_chain[5].adders/cout1 (the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/carry<6>)
     LUT5:I4->O            3   0.068   0.431  the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/adder_chain[7].adders/cout1 (the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/carry<8>)
     LUT5:I4->O            3   0.068   0.431  the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/adder_chain[9].adders/cout1 (the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/carry<10>)
     LUT5:I4->O            3   0.068   0.431  the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/adder_chain[11].adders/cout1 (the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/carry<12>)
     LUT5:I4->O            3   0.068   0.431  the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/adder_chain[13].adders/cout1 (the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/carry<14>)
     LUT4:I3->O            1   0.068   0.399  the_multiplier/systolic_array/pipeline_stages[32].stage/Mmux_r61 (r<526>)
     begin scope: 'the_memory/xy_ram/op_1'
     begin scope: 'BU2'
     RAMB36E1:DIBDI0           0.707          U0/blk_mem_generator/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/TRUE_DP.SIMPLE_PRIM36.ram
    ----------------------------------------
    Total                      5.340ns (1.501ns logic, 3.839ns route)
                                       (28.1% logic, 71.9% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 167 / 37
-------------------------------------------------------------------------
Offset:              3.208ns (Levels of Logic = 5)
  Source:            the_exponent_fifo/FIFO18E1_inst (UNKNOWN)
  Destination:       ready (PAD)
  Source Clock:      clk rising

  Data Path: the_exponent_fifo/FIFO18E1_inst to ready
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FIFO18E1:RDCLK->DO22    1   0.742   0.638  the_exponent_fifo/FIFO18E1_inst (fifo_dout<22>)
     LUT6:I2->O            1   0.068   0.000  the_control_unit/autorun_control_logic/Mmux_e1_bit_i_51 (the_control_unit/autorun_control_logic/Mmux_e1_bit_i_51)
     MUXF7:I1->O           1   0.248   0.000  the_control_unit/autorun_control_logic/Mmux_e1_bit_i_4_f7 (the_control_unit/autorun_control_logic/Mmux_e1_bit_i_4_f7)
     MUXF8:I0->O           6   0.175   0.614  the_control_unit/autorun_control_logic/Mmux_e1_bit_i_2_f8 (the_control_unit/autorun_control_logic/e1_bit_i)
     LUT6:I3->O            2   0.068   0.587  the_control_unit/autorun_control_logic/done_i (the_control_unit/auto_done)
     LUT3:I0->O            0   0.068   0.000  the_control_unit/done1 (ready)
    ----------------------------------------
    Total                      3.208ns (1.369ns logic, 1.839ns route)
                                       (42.7% logic, 57.3% route)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 70 / 35
-------------------------------------------------------------------------
Delay:               1.410ns (Levels of Logic = 3)
  Source:            exp_m (PAD)
  Destination:       ready (PAD)

  Data Path: exp_m to ready
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LUT3:I0->O            4   0.068   0.437  the_control_unit/start_auto1 (the_control_unit/start_auto)
     LUT6:I5->O            2   0.068   0.587  the_control_unit/autorun_control_logic/done_i (the_control_unit/auto_done)
     LUT3:I0->O            0   0.068   0.000  the_control_unit/done1 (ready)
    ----------------------------------------
    Total                      1.410ns (0.386ns logic, 1.024ns route)
                                       (27.4% logic, 72.6% route)

=========================================================================

Cross Clock Domains Report:
--------------------------

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    5.964|         |         |         |
---------------+---------+---------+---------+---------+

=========================================================================


Total REAL time to Xst completion: 169.00 secs
Total CPU time to Xst completion: 169.37 secs
 
--> 

Total memory usage is 382080 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    8 (   0 filtered)
Number of infos    :    7 (   0 filtered)

Synthesis Report
di 26. feb 14:57:46 2013

Release 12.4 - xst M.81d (nt)
Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.12 secs
 
--> Parameter xsthdpdir set to xst


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.12 secs
 
--> Reading design: mod_sim_exp_core.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Parsing
  3) HDL Elaboration
  4) HDL Synthesis
       4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
       5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Partition Report
  8) Design Summary
       8.1) Primitive and Black Box Usage
       8.2) Device utilization summary
       8.3) Partition Resource Summary
       8.4) Timing Report
            8.4.1) Clock Information
            8.4.2) Asynchronous Control Signals Information
            8.4.3) Timing Summary
            8.4.4) Timing Details
            8.4.5) Cross Clock Domains Report


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "mod_sim_exp_core.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "mod_sim_exp_core"
Output Format                      : NGC
Target Device                      : xc6vlx240t-1-ff1156

---- Source Options
Top Module Name                    : mod_sim_exp_core
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : LUT
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Shift Register Extraction          : YES
ROM Style                          : Auto
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Shift Register Minimum Size        : 2
Use DSP Block                      : Auto
Automatic Register Balancing       : No

---- Target Options
LUT Combining                      : Auto
Reduce Control Sets                : Auto
Add IO Buffers                     : NO
Global Maximum Fanout              : 100000
Add Generic Clock Buffer(BUFG)     : 32
Register Duplication               : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Auto
Use Synchronous Set                : Auto
Use Synchronous Reset              : Auto
Pack IO Registers into IOBs        : Auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Area
Optimization Effort                : 2
Power Reduction                    : NO
Keep Hierarchy                     : No
Netlist Hierarchy                  : As_Optimized
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : Maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
DSP48 Utilization Ratio            : 100
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

---- Other Options
Cores Search Directories           : {"../../SVN/mod_sim_exp/rtl/vhdl/core"  }

=========================================================================


=========================================================================
*                          HDL Parsing                                  *
=========================================================================
Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/std_functions.vhd" into library mod_sim_exp
Parsing package .
Parsing package body .
Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/mod_sim_exp_pkg.vhd" into library mod_sim_exp
Parsing package .
Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/cell_1b_mux.vhd" into library mod_sim_exp
Parsing entity .
Parsing architecture  of entity .
Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/cell_1b_adder.vhd" into library mod_sim_exp
Parsing entity .
Parsing architecture  of entity .
Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/d_flip_flop.vhd" into library mod_sim_exp
Parsing entity .
Parsing architecture  of entity .
Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/cell_1b.vhd" into library mod_sim_exp
Parsing entity .
Parsing architecture  of entity .
Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/standard_cell_block.vhd" into library mod_sim_exp
Parsing entity .
Parsing architecture  of entity .
Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/register_n.vhd" into library mod_sim_exp
Parsing entity .
Parsing architecture  of entity .
Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/register_1b.vhd" into library mod_sim_exp
Parsing entity .
Parsing architecture  of entity .
Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/adder_block.vhd" into library mod_sim_exp
Parsing entity .
Parsing architecture  of entity .
Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/ram/tdpram_generic.vhd" into library mod_sim_exp
Parsing entity .
Parsing architecture  of entity .
Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/ram/dpram_generic.vhd" into library mod_sim_exp
Parsing entity .
Parsing architecture  of entity .
Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/sys_stage.vhd" into library mod_sim_exp
Parsing entity .
Parsing architecture  of entity .
Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/sys_last_cell_logic.vhd" into library mod_sim_exp
Parsing entity .
Parsing architecture  of entity .
Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/sys_first_cell_logic.vhd" into library mod_sim_exp
Parsing entity .
Parsing architecture  of entity .
Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/counter_sync.vhd" into library mod_sim_exp
Parsing entity .
Parsing architecture  of entity .
Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/x_shift_reg.vhd" into library mod_sim_exp
Parsing entity .
Parsing architecture  of entity .
Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/sys_pipeline.vhd" into library mod_sim_exp
Parsing entity .
Parsing architecture  of entity .
Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/stepping_logic.vhd" into library mod_sim_exp
Parsing entity .
Parsing architecture  of entity .
Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/operand_ram_gen.vhd" into library mod_sim_exp
Parsing entity .
Parsing architecture  of entity .
Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/modulus_ram_gen.vhd" into library mod_sim_exp
Parsing entity .
Parsing architecture  of entity .
Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/autorun_cntrl.vhd" into library mod_sim_exp
Parsing entity .
Parsing architecture  of entity .
Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/operand_mem_gen.vhd" into library mod_sim_exp
Parsing entity .
Parsing architecture  of entity .
Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/mont_multiplier.vhd" into library mod_sim_exp
Parsing entity .
Parsing architecture  of entity .
Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/mont_ctrl.vhd" into library mod_sim_exp
Parsing entity .
Parsing architecture  of entity .
Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/fifo_generic.vhd" into library mod_sim_exp
Parsing entity .
Parsing architecture  of entity .
Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/mod_sim_exp_core.vhd" into library mod_sim_exp
Parsing entity .
Parsing architecture  of entity .

=========================================================================
*                            HDL Elaboration                            *
=========================================================================

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) from library .

Elaborating entity  (architecture ) from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) from library .

Elaborating entity  (architecture ) from library .

Elaborating entity  (architecture ) from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) from library .

Elaborating entity  (architecture ) from library .

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit .
    Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/mod_sim_exp_core.vhd".
        C_NR_BITS_TOTAL = 1536
        C_NR_STAGES_TOTAL = 96
        C_NR_STAGES_LOW = 32
        C_SPLIT_PIPELINE = true
        C_NR_OP = 4
        C_NR_M = 2
        C_FIFO_DEPTH = 32
INFO:Xst:3010 - "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/mod_sim_exp_core.vhd" line 167: Output port  of the instance  is unconnected or connected to loadless signal.
    Summary:
	inferred   1 Multiplexer(s).
Unit  synthesized.

Synthesizing Unit .
    Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/mont_multiplier.vhd".
        n = 1536
        t = 96
        tl = 32
        split = true
    Found 4x18-bit Read Only RAM for signal <_n0015>
    Summary:
	inferred   1 RAM(s).
Unit  synthesized.

Synthesizing Unit .
    Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/d_flip_flop.vhd".
    Found 1-bit register for signal .
    Summary:
	inferred   1 D-type flip-flop(s).
Unit  synthesized.

Synthesizing Unit .
    Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/x_shift_reg.vhd".
        n = 1536
        t = 96
        tl = 32
    Found 1536-bit register for signal .
    Summary:
	inferred 1536 D-type flip-flop(s).
	inferred 1536 Multiplexer(s).
Unit  synthesized.

Synthesizing Unit .
    Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/stepping_logic.vhd".
        n = 1536
        t = 96
    Summary:
	no macro.
Unit  synthesized.

Synthesizing Unit .
    Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/counter_sync.vhd".
        max_value = 96
    Found 7-bit register for signal .
    Found 1-bit register for signal .
    Found 7-bit adder for signal  created at line 83.
    Found 32-bit subtractor for signal > created at line 79.
    Found 32-bit comparator equal for signal  created at line 79
    Summary:
	inferred   2 Adder/Subtractor(s).
	inferred   8 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred   2 Multiplexer(s).
Unit  synthesized.

Synthesizing Unit .
    Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/counter_sync.vhd".
        max_value = 1536
    Found 11-bit register for signal .
    Found 1-bit register for signal .
    Found 11-bit adder for signal  created at line 83.
    Found 32-bit subtractor for signal > created at line 79.
    Found 32-bit comparator equal for signal  created at line 79
    Summary:
	inferred   2 Adder/Subtractor(s).
	inferred  12 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred   2 Multiplexer(s).
Unit  synthesized.

Synthesizing Unit .
    Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/counter_sync.vhd".
        max_value = 2
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit adder for signal > created at line 83.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred   2 D-type flip-flop(s).
	inferred   2 Multiplexer(s).
Unit  synthesized.

Synthesizing Unit .
    Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/sys_pipeline.vhd".
        n = 1536
        t = 96
        tl = 32
        split = true
INFO:Xst:3010 - "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/sys_pipeline.vhd" line 133: Output port  of the instance  is unconnected or connected to loadless signal.
INFO:Xst:3010 - "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/sys_pipeline.vhd" line 133: Output port  of the instance  is unconnected or connected to loadless signal.
INFO:Xst:3010 - "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/sys_pipeline.vhd" line 133: Output port  of the instance  is unconnected or connected to loadless signal.
    Found 1-bit 3-to-1 multiplexer for signal > created at line 270.
    Found 1-bit 4-to-1 multiplexer for signal  created at line 304.
    Summary:
	inferred  11 Multiplexer(s).
Unit  synthesized.

Synthesizing Unit .
    Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/sys_stage.vhd".
        width = 16
    Summary:
	inferred   1 Multiplexer(s).
Unit  synthesized.

Synthesizing Unit .
    Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/adder_block.vhd".
        width = 16
    Summary:
	no macro.
Unit  synthesized.

Synthesizing Unit .
    Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/cell_1b_adder.vhd".
    Summary:
Unit  synthesized.

Synthesizing Unit .
    Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/standard_cell_block.vhd".
        width = 16
    Summary:
	no macro.
Unit  synthesized.

Synthesizing Unit .
    Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/cell_1b.vhd".
    Summary:
	no macro.
Unit  synthesized.

Synthesizing Unit .
    Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/cell_1b_mux.vhd".
    Found 1-bit 4-to-1 multiplexer for signal  created at line 72.
    Summary:
	inferred   1 Multiplexer(s).
Unit  synthesized.

Synthesizing Unit .
    Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/register_n.vhd".
        width = 16
    Found 16-bit register for signal .
    Summary:
	inferred  16 D-type flip-flop(s).
Unit  synthesized.

Synthesizing Unit .
    Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/register_1b.vhd".
    Found 1-bit register for signal .
    Summary:
	inferred   1 D-type flip-flop(s).
Unit  synthesized.

Synthesizing Unit .
    Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/sys_first_cell_logic.vhd".
    Summary:
Unit  synthesized.

Synthesizing Unit .
    Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/sys_last_cell_logic.vhd".
INFO:Xst:3010 - "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/sys_last_cell_logic.vhd" line 86: Output port  of the instance  is unconnected or connected to loadless signal.
    Summary:
	no macro.
Unit  synthesized.

Synthesizing Unit .
    Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/operand_mem_gen.vhd".
        width = 1536
        nr_op = 4
        nr_m = 2
    Summary:
	inferred   2 Multiplexer(s).
Unit  synthesized.

Synthesizing Unit .
    Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/operand_ram_gen.vhd".
        width = 1536
        depth = 4
    Found 32-bit 48-to-1 multiplexer for signal  created at line 174.
    Found 6-bit comparator greater for signal  created at line 174
    Summary:
	inferred   1 Comparator(s).
	inferred  51 Multiplexer(s).
Unit  synthesized.

Synthesizing Unit .
    Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/ram/tdpram_generic.vhd".
        depth = 4
    Set property "ram_style = block" for signal .
    Found 4x32-bit dual-port RAM  for signal .
    Found 32-bit register for signal .
    Found 32-bit register for signal .
    Summary:
	inferred   1 RAM(s).
	inferred  64 D-type flip-flop(s).
	inferred   2 Multiplexer(s).
Unit  synthesized.

Synthesizing Unit .
    Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/modulus_ram_gen.vhd".
        width = 1536
        depth = 2
    Summary:
	inferred  48 Multiplexer(s).
Unit  synthesized.

Synthesizing Unit .
    Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/ram/dpram_generic.vhd".
        depth = 2
    Set property "ram_style = block" for signal .
    Found 2x32-bit dual-port RAM  for signal .
    Found 32-bit register for signal .
    Summary:
	inferred   1 RAM(s).
	inferred  32 D-type flip-flop(s).
Unit  synthesized.

Synthesizing Unit .
    Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/fifo_generic.vhd".
        depth = 32
    Found 6-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 6-bit register for signal .
    Found 6-bit adder for signal  created at line 95.
    Found 6-bit adder for signal  created at line 120.
    Found 6-bit comparator equal for signal  created at line 95
    Found 6-bit comparator equal for signal  created at line 99
    Summary:
	inferred   2 Adder/Subtractor(s).
	inferred  15 D-type flip-flop(s).
	inferred   2 Comparator(s).
Unit  synthesized.

Synthesizing Unit .
    Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/ram/dpram_generic.vhd".
        depth = 33
    Set property "ram_style = block" for signal .
WARNING:Xst:3035 - Index value(s) does not match array range for signal , simulation mismatch.
    Found 33x32-bit dual-port RAM  for signal .
    Found 32-bit register for signal .
    Summary:
	inferred   1 RAM(s).
	inferred  32 D-type flip-flop(s).
Unit  synthesized.

Synthesizing Unit .
    Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/mont_ctrl.vhd".
    Found 3-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 3-bit adder for signal  created at line 128.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred   5 D-type flip-flop(s).
	inferred   5 Multiplexer(s).
Unit  synthesized.

Synthesizing Unit .
    Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/autorun_cntrl.vhd".
    Found 4-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 4-bit subtractor for signal > created at line 113.
    Found 1-bit 16-to-1 multiplexer for signal  created at line 122.
    Found 1-bit 16-to-1 multiplexer for signal  created at line 123.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred   9 D-type flip-flop(s).
	inferred   7 Multiplexer(s).
Unit  synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# RAMs                                                 : 98
 2x32-bit dual-port RAM                                : 48
 33x32-bit dual-port RAM                               : 1
 4x18-bit single-port Read Only RAM                    : 1
 4x32-bit dual-port RAM                                : 48
# Adders/Subtractors                                   : 9
 1-bit adder                                           : 1
 11-bit adder                                          : 1
 3-bit adder                                           : 1
 32-bit subtractor                                     : 2
 4-bit subtractor                                      : 1
 6-bit adder                                           : 2
 7-bit adder                                           : 1
# Registers                                            : 843
 1-bit register                                        : 595
 11-bit register                                       : 1
 1536-bit register                                     : 1
 16-bit register                                       : 96
 3-bit register                                        : 1
 32-bit register                                       : 145
 4-bit register                                        : 1
 6-bit register                                        : 2
 7-bit register                                        : 1
# Comparators                                          : 5
 32-bit comparator equal                               : 2
 6-bit comparator equal                                : 2
 6-bit comparator greater                              : 1
# Multiplexers                                         : 3397
 1-bit 16-to-1 multiplexer                             : 2
 1-bit 2-to-1 multiplexer                              : 1649
 1-bit 3-to-1 multiplexer                              : 1
 1-bit 4-to-1 multiplexer                              : 1539
 11-bit 2-to-1 multiplexer                             : 1
 16-bit 2-to-1 multiplexer                             : 96
 2-bit 2-to-1 multiplexer                              : 6
 3-bit 2-to-1 multiplexer                              : 2
 32-bit 2-to-1 multiplexer                             : 97
 32-bit 48-to-1 multiplexer                            : 1
 4-bit 2-to-1 multiplexer                              : 2
 7-bit 2-to-1 multiplexer                              : 1
# Xors                                                 : 9224
 1-bit xor2                                            : 9224

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

WARNING:Xst:1290 - Hierarchical block  is unconnected in block .
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block  is unconnected in block .
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block  is unconnected in block .
   It will be removed from the design.

Synthesizing (advanced) Unit .
The following registers are absorbed into counter : 1 register on signal .
Unit  synthesized (advanced).

Synthesizing (advanced) Unit .
The following registers are absorbed into counter : 1 register on signal .
Unit  synthesized (advanced).

Synthesizing (advanced) Unit .
The following registers are absorbed into counter : 1 register on signal .
Unit  synthesized (advanced).

Synthesizing (advanced) Unit .
INFO:Xst:3040 - The RAM  will be implemented as a BLOCK RAM, absorbing the following register(s): 
    -----------------------------------------------------------------------
    | ram_type           | Block                               |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 2-word x 32-bit                     |          |
    |     mode           | read-first                          |          |
    |     clkA           | connected to signal            | rise     |
    |     weA            | connected to signal             | high     |
    |     addrA          | connected to signal          |          |
    |     diA            | connected to signal            |          |
    -----------------------------------------------------------------------
    | optimization       | area                                |          |
    -----------------------------------------------------------------------
    | Port B                                                              |
    |     aspect ratio   | 2-word x 32-bit                     |          |
    |     mode           | write-first                         |          |
    |     clkB           | connected to signal            | rise     |
    |     addrB          | connected to signal          |          |
    |     doB            | connected to signal           |          |
    -----------------------------------------------------------------------
    | optimization       | area                                |          |
    -----------------------------------------------------------------------
Unit  synthesized (advanced).

Synthesizing (advanced) Unit .
INFO:Xst:3040 - The RAM  will be implemented as a BLOCK RAM, absorbing the following register(s): 
    -----------------------------------------------------------------------
    | ram_type           | Block                               |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 33-word x 32-bit                    |          |
    |     mode           | read-first                          |          |
    |     clkA           | connected to signal            | rise     |
    |     weA            | connected to signal             | high     |
    |     addrA          | connected to signal          |          |
    |     diA            | connected to signal            |          |
    -----------------------------------------------------------------------
    | optimization       | area                                |          |
    -----------------------------------------------------------------------
    | Port B                                                              |
    |     aspect ratio   | 33-word x 32-bit                    |          |
    |     mode           | write-first                         |          |
    |     clkB           | connected to signal            | rise     |
    |     addrB          | connected to signal          |          |
    |     doB            | connected to signal           |          |
    -----------------------------------------------------------------------
    | optimization       | area                                |          |
    -----------------------------------------------------------------------
Unit  synthesized (advanced).

Synthesizing (advanced) Unit .
The following registers are absorbed into counter : 1 register on signal .
The following registers are absorbed into counter : 1 register on signal .
Unit  synthesized (advanced).

Synthesizing (advanced) Unit .
INFO:Xst:3031 - HDL ADVISOR - The RAM  will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 4-word x 18-bit                     |          |
    |     weA            | connected to signal            | high     |
    |     addrA          | connected to signal          |          |
    |     diA            | connected to signal            |          |
    |     doA            | connected to signal          |          |
    -----------------------------------------------------------------------
Unit  synthesized (advanced).

Synthesizing (advanced) Unit .
INFO:Xst:3040 - The RAM  will be implemented as a BLOCK RAM, absorbing the following register(s):  
    -----------------------------------------------------------------------
    | ram_type           | Block                               |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 4-word x 32-bit                     |          |
    |     mode           | write-first                         |          |
    |     clkA           | connected to signal           | rise     |
    |     weA            | connected to signal            | high     |
    |     addrA          | connected to signal          |          |
    |     diA            | connected to signal           |          |
    |     doA            | connected to signal          |          |
    -----------------------------------------------------------------------
    | optimization       | area                                |          |
    -----------------------------------------------------------------------
    | Port B                                                              |
    |     aspect ratio   | 4-word x 32-bit                     |          |
    |     mode           | write-first                         |          |
    |     clkB           | connected to signal           | rise     |
    |     weB            | connected to signal            | high     |
    |     addrB          | connected to signal          |          |
    |     diB            | connected to signal           |          |
    |     doB            | connected to signal          |          |
    -----------------------------------------------------------------------
    | optimization       | area                                |          |
    -----------------------------------------------------------------------
Unit  synthesized (advanced).

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# RAMs                                                 : 98
 2x32-bit dual-port block RAM                          : 48
 33x32-bit dual-port block RAM                         : 1
 4x18-bit single-port distributed Read Only RAM        : 1
 4x32-bit dual-port block RAM                          : 48
# Adders/Subtractors                                   : 5
 3-bit adder                                           : 1
 32-bit subtractor                                     : 2
 4-bit subtractor                                      : 1
 6-bit adder                                           : 1
# Counters                                             : 5
 1-bit up counter                                      : 1
 11-bit up counter                                     : 1
 6-bit up counter                                      : 2
 7-bit up counter                                      : 1
# Registers                                            : 3673
 Flip-Flops                                            : 3673
# Comparators                                          : 5
 32-bit comparator equal                               : 2
 6-bit comparator equal                                : 2
 6-bit comparator greater                              : 1
# Multiplexers                                         : 3297
 1-bit 16-to-1 multiplexer                             : 2
 1-bit 2-to-1 multiplexer                              : 1648
 1-bit 3-to-1 multiplexer                              : 1
 1-bit 4-to-1 multiplexer                              : 1539
 16-bit 2-to-1 multiplexer                             : 96
 2-bit 2-to-1 multiplexer                              : 5
 3-bit 2-to-1 multiplexer                              : 2
 32-bit 2-to-1 multiplexer                             : 1
 32-bit 48-to-1 multiplexer                            : 1
 4-bit 2-to-1 multiplexer                              : 2
# Xors                                                 : 9224
 1-bit xor2                                            : 9224

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit  ...

Optimizing unit  ...

Optimizing unit  ...

Optimizing unit  ...

Optimizing unit  ...

Optimizing unit  ...

Optimizing unit  ...

Optimizing unit  ...

Optimizing unit  ...

Optimizing unit  ...

Optimizing unit  ...

Optimizing unit  ...

Optimizing unit  ...
WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
WARNING:Xst:2677 - Node  of sequential type is unconnected in block .

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block mod_sim_exp_core, actual ratio is 7.

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 3700
 Flip-Flops                                            : 3700

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Design Summary                             *
=========================================================================

Top Level Output File Name         : mod_sim_exp_core.ngc

Primitive and Black Box Usage:
------------------------------
# BELS                             : 10810
#      GND                         : 1
#      INV                         : 4
#      LUT2                        : 14
#      LUT3                        : 800
#      LUT4                        : 832
#      LUT5                        : 3911
#      LUT6                        : 4393
#      MUXCY                       : 10
#      MUXF7                       : 829
#      MUXF8                       : 2
#      VCC                         : 1
#      XORCY                       : 13
# FlipFlops/Latches                : 3700
#      FD                          : 5
#      FDC                         : 1832
#      FDCE                        : 1845
#      FDP                         : 1
#      FDPE                        : 4
#      FDR                         : 3
#      FDRE                        : 10
# RAMS                             : 97
#      RAMB18E1                    : 49
#      RAMB36E1                    : 48

Device utilization summary:
---------------------------

Selected Device : 6vlx240tff1156-1 


Slice Logic Utilization: 
 Number of Slice Registers:            3700  out of  301440     1%  
 Number of Slice LUTs:                 9954  out of  150720     6%  
    Number used as Logic:              9954  out of  150720     6%  

Slice Logic Distribution: 
 Number of LUT Flip Flop pairs used:  10095
   Number with an unused Flip Flop:    6395  out of  10095    63%  
   Number with an unused LUT:           141  out of  10095     1%  
   Number of fully used LUT-FF pairs:  3559  out of  10095    35%  
   Number of unique control sets:       113

IO Utilization: 
 Number of IOs:                         125
 Number of bonded IOBs:                   0  out of    600     0%  

Specific Feature Utilization:
 Number of Block RAM/FIFO:               73  out of    416    17%  
    Number using Block RAM only:         73

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
Timing Report

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+----------------------------------------+-------+
Clock Signal                       | Clock buffer(FF name)                  | Load  |
-----------------------------------+----------------------------------------+-------+
clk                                | NONE(the_multiplier/delay_1_cycle/dout)| 3797  |
-----------------------------------+----------------------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -1

   Minimum period: 7.831ns (Maximum Frequency: 127.698MHz)
   Minimum input arrival time before clock: 5.973ns
   Maximum output required time after clock: 4.539ns
   Maximum combinational path delay: 2.140ns

Timing Details:
---------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 7.831ns (frequency: 127.698MHz)
  Total number of paths / destination ports: 412126 / 9739
-------------------------------------------------------------------------
Delay:               7.831ns (Levels of Logic = 11)
  Source:            the_memory/xy_ram/ramblocks[16].ramblock/Mram_RAM (RAM)
  Destination:       the_multiplier/systolic_array/pipeline_stages[32].stage/cout_reg/dout (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: the_memory/xy_ram/ramblocks[16].ramblock/Mram_RAM to the_multiplier/systolic_array/pipeline_stages[32].stage/cout_reg/dout
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     RAMB36E1:CLKARDCLK->DOADO0    6   2.073   0.450  the_memory/xy_ram/ramblocks[16].ramblock/Mram_RAM (xy<512>)
     LUT6:I5->O           25   0.068   0.929  the_multiplier/systolic_array/Mmux_qin_stage<32>11 (the_multiplier/systolic_array/qin_stage<32>)
     LUT6:I0->O            1   0.068   0.000  the_multiplier/systolic_array/pipeline_stages[32].stage/sys_cells/cell_block[1].cells/cell_mux/Mmux_result121 (the_multiplier/systolic_array/pipeline_stages[32].stage/sys_cells/cell_block[1].cells/cell_mux/Mmux_result12)
     MUXF7:I1->O           2   0.248   0.423  the_multiplier/systolic_array/pipeline_stages[32].stage/sys_cells/cell_block[1].cells/cell_mux/Mmux_result12_f7 (the_multiplier/systolic_array/pipeline_stages[32].stage/sys_cells/cell_block[1].cells/cell_mux/Mmux_result12_f7)
     LUT5:I4->O            3   0.068   0.431  the_multiplier/systolic_array/pipeline_stages[32].stage/sys_cells/cell_block[1].cells/cell_adder/cout1 (the_multiplier/systolic_array/pipeline_stages[32].stage/sys_cells/carry<2>)
     LUT5:I4->O            3   0.068   0.431  the_multiplier/systolic_array/pipeline_stages[32].stage/sys_cells/cell_block[3].cells/cell_adder/cout1 (the_multiplier/systolic_array/pipeline_stages[32].stage/sys_cells/carry<4>)
     LUT5:I4->O            3   0.068   0.431  the_multiplier/systolic_array/pipeline_stages[32].stage/sys_cells/cell_block[5].cells/cell_adder/cout1 (the_multiplier/systolic_array/pipeline_stages[32].stage/sys_cells/carry<6>)
     LUT5:I4->O            3   0.068   0.431  the_multiplier/systolic_array/pipeline_stages[32].stage/sys_cells/cell_block[7].cells/cell_adder/cout1 (the_multiplier/systolic_array/pipeline_stages[32].stage/sys_cells/carry<8>)
     LUT5:I4->O            3   0.068   0.431  the_multiplier/systolic_array/pipeline_stages[32].stage/sys_cells/cell_block[9].cells/cell_adder/cout1 (the_multiplier/systolic_array/pipeline_stages[32].stage/sys_cells/carry<10>)
     LUT5:I4->O            3   0.068   0.431  the_multiplier/systolic_array/pipeline_stages[32].stage/sys_cells/cell_block[11].cells/cell_adder/cout1 (the_multiplier/systolic_array/pipeline_stages[32].stage/sys_cells/carry<12>)
     LUT5:I4->O            3   0.068   0.431  the_multiplier/systolic_array/pipeline_stages[32].stage/sys_cells/cell_block[13].cells/cell_adder/cout1 (the_multiplier/systolic_array/pipeline_stages[32].stage/sys_cells/carry<14>)
     LUT5:I4->O            1   0.068   0.000  the_multiplier/systolic_array/pipeline_stages[32].stage/sys_cells/cell_block[15].cells/cell_adder/Mxor_r_xo<0>1 (the_multiplier/systolic_array/pipeline_stages[32].stage/cell_result<15>)
     FDCE:D                    0.011          the_multiplier/systolic_array/pipeline_stages[32].stage/result_reg/dout_15
    ----------------------------------------
    Total                      7.831ns (3.012ns logic, 4.819ns route)
                                       (38.5% logic, 61.5% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
  Total number of paths / destination ports: 19167 / 10478
-------------------------------------------------------------------------
Offset:              5.973ns (Levels of Logic = 12)
  Source:            p_sel<0> (PAD)
  Destination:       the_multiplier/systolic_array/pipeline_stages[0].stage/cout_reg/dout (FF)
  Destination Clock: clk rising

  Data Path: p_sel<0> to the_multiplier/systolic_array/pipeline_stages[0].stage/cout_reg/dout
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LUT4:I1->O           29   0.068   0.927  the_multiplier/x_selection/Mmux_xi11 (the_multiplier/xi)
     LUT6:I1->O            1   0.068   0.000  the_multiplier/systolic_array/pipeline_stages[0].stage/sys_cells/cell_block[1].cells/cell_mux/Mmux_result111 (the_multiplier/systolic_array/pipeline_stages[0].stage/sys_cells/cell_block[1].cells/cell_mux/Mmux_result11)
     MUXF7:I1->O           1   0.248   0.417  the_multiplier/systolic_array/pipeline_stages[0].stage/sys_cells/cell_block[1].cells/cell_mux/Mmux_result11_f7 (the_multiplier/systolic_array/pipeline_stages[0].stage/sys_cells/cell_block[1].cells/cell_mux/Mmux_result1)
     LUT5:I4->O            2   0.068   0.423  the_multiplier/systolic_array/pipeline_stages[0].stage/sys_cells/cell_block[1].cells/cell_mux/Mmux_result12 (the_multiplier/systolic_array/pipeline_stages[0].stage/sys_cells/cell_block[1].cells/mux2adder)
     LUT5:I4->O            3   0.068   0.431  the_multiplier/systolic_array/pipeline_stages[0].stage/sys_cells/cell_block[1].cells/cell_adder/cout1 (the_multiplier/systolic_array/pipeline_stages[0].stage/sys_cells/carry<2>)
     LUT5:I4->O            3   0.068   0.431  the_multiplier/systolic_array/pipeline_stages[0].stage/sys_cells/cell_block[3].cells/cell_adder/cout1 (the_multiplier/systolic_array/pipeline_stages[0].stage/sys_cells/carry<4>)
     LUT5:I4->O            3   0.068   0.431  the_multiplier/systolic_array/pipeline_stages[0].stage/sys_cells/cell_block[5].cells/cell_adder/cout1 (the_multiplier/systolic_array/pipeline_stages[0].stage/sys_cells/carry<6>)
     LUT5:I4->O            3   0.068   0.431  the_multiplier/systolic_array/pipeline_stages[0].stage/sys_cells/cell_block[7].cells/cell_adder/cout1 (the_multiplier/systolic_array/pipeline_stages[0].stage/sys_cells/carry<8>)
     LUT5:I4->O            3   0.068   0.431  the_multiplier/systolic_array/pipeline_stages[0].stage/sys_cells/cell_block[9].cells/cell_adder/cout1 (the_multiplier/systolic_array/pipeline_stages[0].stage/sys_cells/carry<10>)
     LUT5:I4->O            3   0.068   0.431  the_multiplier/systolic_array/pipeline_stages[0].stage/sys_cells/cell_block[11].cells/cell_adder/cout1 (the_multiplier/systolic_array/pipeline_stages[0].stage/sys_cells/carry<12>)
     LUT5:I4->O            3   0.068   0.431  the_multiplier/systolic_array/pipeline_stages[0].stage/sys_cells/cell_block[13].cells/cell_adder/cout1 (the_multiplier/systolic_array/pipeline_stages[0].stage/sys_cells/carry<14>)
     LUT5:I4->O            1   0.068   0.000  the_multiplier/systolic_array/pipeline_stages[0].stage/sys_cells/cell_block[15].cells/cell_adder/Mxor_r_xo<0>1 (the_multiplier/systolic_array/pipeline_stages[0].stage/cell_result<15>)
     FDCE:D                    0.011          the_multiplier/systolic_array/pipeline_stages[0].stage/result_reg/dout_15
    ----------------------------------------
    Total                      5.973ns (1.189ns logic, 4.784ns route)
                                       (19.9% logic, 80.1% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 2675 / 37
-------------------------------------------------------------------------
Offset:              4.539ns (Levels of Logic = 5)
  Source:            the_exponent_fifo/ramblock/Mram_RAM (RAM)
  Destination:       ready (PAD)
  Source Clock:      clk rising

  Data Path: the_exponent_fifo/ramblock/Mram_RAM to ready
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     RAMB18E1:CLKARDCLK->DOBDO6    1   2.073   0.638  the_exponent_fifo/ramblock/Mram_RAM (fifo_dout<22>)
     LUT6:I2->O            1   0.068   0.000  the_control_unit/autorun_control_logic/Mmux_e1_bit_i_51 (the_control_unit/autorun_control_logic/Mmux_e1_bit_i_51)
     MUXF7:I1->O           1   0.248   0.000  the_control_unit/autorun_control_logic/Mmux_e1_bit_i_4_f7 (the_control_unit/autorun_control_logic/Mmux_e1_bit_i_4_f7)
     MUXF8:I0->O           6   0.175   0.614  the_control_unit/autorun_control_logic/Mmux_e1_bit_i_2_f8 (the_control_unit/autorun_control_logic/e1_bit_i)
     LUT6:I3->O            2   0.068   0.587  the_control_unit/autorun_control_logic/done_i (the_control_unit/auto_done)
     LUT3:I0->O            0   0.068   0.000  the_control_unit/done1 (ready)
    ----------------------------------------
    Total                      4.539ns (2.700ns logic, 1.839ns route)
                                       (59.5% logic, 40.5% route)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 1829 / 34
-------------------------------------------------------------------------
Delay:               2.140ns (Levels of Logic = 5)
  Source:            rw_address<1> (PAD)
  Destination:       data_out<31> (PAD)

  Data Path: rw_address<1> to data_out<31>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LUT6:I0->O            1   0.068   0.638  the_memory/xy_ram/Mmux_addrB[5]_X_27_o_wide_mux_59_OUT_111 (the_memory/xy_ram/Mmux_addrB[5]_X_27_o_wide_mux_59_OUT_111)
     LUT6:I2->O            1   0.068   0.000  the_memory/xy_ram/Mmux_addrB[5]_X_27_o_wide_mux_59_OUT_6 (the_memory/xy_ram/Mmux_addrB[5]_X_27_o_wide_mux_59_OUT_6)
     MUXF7:I1->O           2   0.248   0.423  the_memory/xy_ram/Mmux_addrB[5]_X_27_o_wide_mux_59_OUT_5_f7 (the_memory/xy_ram/Mmux_addrB[5]_X_27_o_wide_mux_59_OUT_5_f7)
     LUT6:I5->O            1   0.068   0.000  the_memory/xy_ram/Mmux_doutB110 (the_memory/xy_ram/Mmux_doutB1)
     MUXF7:I1->O           0   0.248   0.000  the_memory/xy_ram/Mmux_doutB1_f7 (data_out<0>)
    ----------------------------------------
    Total                      2.140ns (1.079ns logic, 1.061ns route)
                                       (50.4% logic, 49.6% route)

=========================================================================

Cross Clock Domains Report:
--------------------------

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    7.831|         |         |         |
---------------+---------+---------+---------+---------+

=========================================================================


Total REAL time to Xst completion: 193.00 secs
Total CPU time to Xst completion: 192.90 secs
 
--> 

Total memory usage is 374848 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    8 (   0 filtered)
Number of infos    :   10 (   0 filtered)