URL
https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk
Subversion Repositories mod_sim_exp
Compare Revisions
- This comparison shows the changes necessary to convert path
/mod_sim_exp
- from Rev 20 to Rev 21
- ↔ Reverse comparison
Rev 20 → Rev 21
/trunk/rtl/vhdl/core/x_shift_reg.vhd
67,7 → 67,7
next_x : in std_logic; -- next bit of x |
p_sel : in std_logic_vector(1 downto 0); -- pipeline selection |
-- x operand bit out (serial) |
x_i : out std_logic |
xi : out std_logic |
); |
end x_shift_reg; |
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94,7 → 94,7
end process; |
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with p_sel select -- pipeline select |
x_i <= x_reg(offset) when "10", -- use bit at offset for high part of pipeline |
x_reg(0) when others; -- use LS bit for lower part of pipeline |
xi <= x_reg(offset) when "10", -- use bit at offset for high part of pipeline |
x_reg(0) when others; -- use LS bit for lower part of pipeline |
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end Behavioral; |
/trunk/rtl/vhdl/core/mont_mult_sys_pipeline.vhd
96,7 → 96,7
signal m_inv : std_logic_vector(n-1 downto 0); |
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signal next_x_i : std_logic; |
signal x_i : std_logic; |
signal xi : std_logic; |
begin |
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-- x selection |
113,7 → 113,7
load_x => load_x, |
next_x => next_x_i, |
p_sel => p_sel, |
x_i => x_i |
xi => xi |
); |
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-- precomputation of my (m+y) |
169,7 → 169,7
my => my, |
y => xy, |
m => m, |
xi => x_i, |
xi => xi, |
start => start_multiplier, |
reset => reset_multiplier, |
p_sel => p_sel, |
/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
405,7 → 405,7
next_x : in std_logic; -- next bit of x |
p_sel : in std_logic_vector(1 downto 0); -- pipeline selection |
-- x operand bit out (serial) |
x_i : out std_logic |
xi : out std_logic |
); |
end component x_shift_reg; |
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