URL
https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk
Subversion Repositories mod_sim_exp
Compare Revisions
- This comparison shows the changes necessary to convert path
/mod_sim_exp
- from Rev 80 to Rev 81
- ↔ Reverse comparison
Rev 80 → Rev 81
/trunk/rtl/vhdl/core/operand_ram_asym.vhd
53,6 → 53,7
use ieee.std_logic_unsigned.all; |
|
library mod_sim_exp; |
use mod_sim_exp.mod_sim_exp_pkg.all; |
use mod_sim_exp.std_functions.all; |
|
-- structural description of a RAM to hold the operands, with |
118,7 → 119,7
signal addrA_single : std_logic_vector(log2(width*depth/32)-1 downto 0); |
begin |
addrA_single <= operand_in_sel & operand_addr; |
ramblock : entity mod_sim_exp.tdpramblock_asym |
ramblock : tdpramblock_asym |
generic map( |
depth => depth, |
width => width, |
151,7 → 152,7
addrA <= operand_in_sel & operand_addr(log2(RAMblock_maxwidth/32)-1 downto 0); |
|
full_ones : if (i < nrRAMblocks_full) generate |
ramblock_full : entity mod_sim_exp.tdpramblock_asym |
ramblock_full : tdpramblock_asym |
generic map( |
depth => depth, |
width => RAMblock_maxwidth, |
200,7 → 201,7
signal weA_part : std_logic; |
begin |
addrA_part <= operand_in_sel & operand_addr(log2(RAMblock_part_width/32)-1 downto 0); |
ramblock_part : entity mod_sim_exp.tdpramblock_asym |
ramblock_part : tdpramblock_asym |
generic map( |
depth => depth, |
width => RAMblock_part_width, |
/trunk/rtl/vhdl/core/modulus_ram_asym.vhd
54,6 → 54,7
|
library mod_sim_exp; |
use mod_sim_exp.std_functions.all; |
use mod_sim_exp.mod_sim_exp_pkg.all; |
|
-- structural description of a RAM to hold the modulus, with |
-- adjustable width (64, 128, 256, 512, 576, 640,..) and depth(nr of moduluses) |
127,7 → 128,7
waddr <= modulus_in_sel & modulus_addr(log2(RAMblock_maxwidth/32)-1 downto 0); |
|
full_ones : if (i < nrRAMblocks_full) generate |
ramblock_full : entity mod_sim_exp.dpramblock_asym |
ramblock_full : dpramblock_asym |
generic map( |
width => RAMblock_maxwidth, |
depth => depth, |