URL
https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk
Subversion Repositories mod_sim_exp
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- This comparison shows the changes necessary to convert path
/mod_sim_exp
- from Rev 82 to Rev 83
- ↔ Reverse comparison
Rev 82 → Rev 83
/trunk/rtl/vhdl/ram/dpramblock_asym.vhd
50,6 → 50,7
|
library mod_sim_exp; |
use mod_sim_exp.std_functions.all; |
use mod_sim_exp.mod_sim_exp_pkg.all; |
|
-- altera infers ramblocks from a depth of 9 (or 2 with any ram size recognition option on) |
-- and width 64,128,256,512,1024 |
84,7 → 85,7
-- generate (width/32) blocks of 32-bit ram with a given depth |
-- these rams outputs are concatenated to a width-bit signal |
ramblocks : for i in 0 to nrRAMs-1 generate |
ramblock: entity mod_sim_exp.dpram_asym |
ramblock: dpram_asym |
generic map( |
rddepth => depth, |
wrwidth => RAMwrwidth, |
/trunk/rtl/vhdl/ram/tdpramblock_asym.vhd
50,6 → 50,7
|
library mod_sim_exp; |
use mod_sim_exp.std_functions.all; |
use mod_sim_exp.mod_sim_exp_pkg.all; |
|
-- altera infers ramblocks from a depth of 9 (or 2 with any ram size recognition option on) |
-- and width 64,128,256,512 |
87,7 → 88,7
begin |
|
ramblocks : for i in 0 to nrRAMs-1 generate |
ramblock : entity mod_sim_exp.tdpram_asym |
ramblock : tdpram_asym |
generic map( |
widthA => RAMwidthA, |
depthB => depth, |
/trunk/rtl/vhdl/core/modulus_ram_asym.vhd
100,7 → 100,7
begin |
waddr <= modulus_in_sel & modulus_addr; |
|
ramblock: entity mod_sim_exp.dpramblock_asym |
ramblock: dpramblock_asym |
generic map( |
width => width, |
depth => depth, |
162,7 → 162,7
begin |
-- write port signal |
waddr_part <= modulus_in_sel & modulus_addr(log2(RAMblock_part_width/32)-1 downto 0); |
ramblock_part : entity mod_sim_exp.dpramblock_asym |
ramblock_part : dpramblock_asym |
generic map( |
width => RAMblock_part_width, |
depth => depth, |