URL
https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk
Subversion Repositories mod_sim_exp
Compare Revisions
- This comparison shows the changes necessary to convert path
/mod_sim_exp
- from Rev 93 to Rev 94
- ↔ Reverse comparison
Rev 93 → Rev 94
/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd
65,6 → 65,8
architecture test of mod_sim_exp_core_tb is |
constant CLK_PERIOD : time := 10 ns; |
signal clk : std_logic := '0'; |
constant CORE_CLK_PERIOD : time := 4 ns; |
signal core_clk : std_logic := '0'; |
signal reset : std_logic := '1'; |
file input : text open read_mode is "src/sim_input.txt"; |
file output : text open write_mode is "out/sim_output.txt"; |
76,7 → 78,7
constant C_NR_STAGES_TOTAL : integer := 96; |
constant C_NR_STAGES_LOW : integer := 32; |
constant C_SPLIT_PIPELINE : boolean := true; |
constant C_FIFO_DEPTH : integer := 32; -- set to (maximum exponent width)/16 |
constant C_FIFO_AW : integer := 7; -- set to log2( (maximum exponent width)/16 ) |
constant C_MEM_STYLE : string := "asym"; -- xil_prim, generic, asym are valid options |
constant C_FPGA_MAN : string := "xilinx"; -- xilinx, altera are valid options |
|
126,6 → 128,16
end loop; |
end process; |
|
core_clk_process : process |
begin |
while (true) loop |
core_clk <= '0'; |
wait for CORE_CLK_PERIOD/2; |
core_clk <= '1'; |
wait for CORE_CLK_PERIOD/2; |
end loop; |
end process; |
|
------------------------------------------ |
-- Stimulus Process |
------------------------------------------ |
677,13 → 689,14
C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL, |
C_NR_STAGES_LOW => C_NR_STAGES_LOW, |
C_SPLIT_PIPELINE => C_SPLIT_PIPELINE, |
C_FIFO_DEPTH => C_FIFO_DEPTH, |
C_FIFO_AW => C_FIFO_AW, |
C_MEM_STYLE => C_MEM_STYLE, -- xil_prim, generic, asym are valid options |
C_FPGA_MAN => C_FPGA_MAN -- xilinx, altera are valid options |
) |
port map( |
clk => clk, |
reset => reset, |
bus_clk => clk, |
core_clk => core_clk, |
reset => reset, |
-- operand memory interface (plb shared memory) |
write_enable => core_write_enable, |
data_in => core_data_in, |
/trunk/bench/vhdl/axi_tb.vhd
59,6 → 59,7
architecture arch of axi_tb is |
-- constants |
constant CLK_PERIOD : time := 10 ns; |
constant CORE_CLK_PERIOD : time := 4 ns; |
constant C_S_AXI_DATA_WIDTH : integer := 32; |
constant C_S_AXI_ADDR_WIDTH : integer := 32; |
|
71,12 → 72,14
constant C_NR_STAGES_TOTAL : integer := 96; |
constant C_NR_STAGES_LOW : integer := 32; |
constant C_SPLIT_PIPELINE : boolean := true; |
constant C_FIFO_DEPTH : integer := 32; -- set to (maximum exponent width)/16 |
constant C_FIFO_AW : integer := 7; -- set to log2( (maximum exponent width)/16 ) |
constant C_MEM_STYLE : string := "generic"; -- xil_prim, generic, asym are valid options |
constant C_FPGA_MAN : string := "xilinx"; -- xilinx, altera are valid options |
constant C_BASEADDR : std_logic_vector(0 to 31) := x"A0000000"; |
constant C_HIGHADDR : std_logic_vector(0 to 31) := x"A0007FFF"; |
|
|
signal core_clk : std_logic := '0'; |
------------------------- |
-- AXI4lite interface |
------------------------- |
120,8 → 123,18
wait for CLK_PERIOD/2; |
end loop; |
end process; |
|
core_clk_process : process |
begin |
while (true) loop |
core_clk <= '0'; |
wait for CORE_CLK_PERIOD/2; |
core_clk <= '1'; |
wait for CORE_CLK_PERIOD/2; |
end loop; |
end process; |
|
|
|
stim_proc : process |
|
variable Lw : line; |
266,7 → 279,7
C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL, |
C_NR_STAGES_LOW => C_NR_STAGES_LOW, |
C_SPLIT_PIPELINE => C_SPLIT_PIPELINE, |
C_FIFO_DEPTH => C_FIFO_DEPTH, |
C_FIFO_AW => C_FIFO_AW, |
C_MEM_STYLE => C_MEM_STYLE, -- xil_prim, generic, asym are valid options |
C_FPGA_MAN => C_FPGA_MAN, -- xilinx, altera are valid options |
C_BASEADDR => C_BASEADDR, |
274,7 → 287,7
) |
port map( |
--USER ports |
|
core_clk => core_clk, |
------------------------- |
-- AXI4lite interface |
------------------------- |
/trunk/bench/vhdl/msec_axi_tb.vhd
79,8 → 79,8
constant C_NR_STAGES_TOTAL : integer := 96; |
constant C_NR_STAGES_LOW : integer := 32; |
constant C_SPLIT_PIPELINE : boolean := true; |
constant C_FIFO_DEPTH : integer := 32; -- set to (maximum exponent width)/16 |
constant C_MEM_STYLE : string := "generic"; -- xil_prim, generic, asym are valid options |
constant C_FIFO_AW : integer := 7; -- set to log2( (maximum exponent width)/16 ) |
constant C_MEM_STYLE : string := "xil_prim"; -- xil_prim, generic, asym are valid options |
constant C_FPGA_MAN : string := "xilinx"; -- xilinx, altera are valid options |
constant C_BASEADDR : std_logic_vector(0 to 31) := x"A0000000"; |
constant C_HIGHADDR : std_logic_vector(0 to 31) := x"A0007FFF"; |
821,7 → 821,7
C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL, |
C_NR_STAGES_LOW => C_NR_STAGES_LOW, |
C_SPLIT_PIPELINE => C_SPLIT_PIPELINE, |
C_FIFO_DEPTH => C_FIFO_DEPTH, |
C_FIFO_AW => C_FIFO_AW, |
C_MEM_STYLE => C_MEM_STYLE, -- xil_prim, generic, asym are valid options |
C_FPGA_MAN => C_FPGA_MAN, -- xilinx, altera are valid options |
C_BASEADDR => C_BASEADDR, |
831,6 → 831,7
--USER ports |
calc_time => calc_time, |
IntrEvent => IntrEvent, |
core_clk => core_clk, |
------------------------- |
-- AXI4lite interface |
------------------------- |
/trunk/rtl/verilog/generic_fifo_dc.v
0,0 → 1,304
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Universal FIFO Dual Clock //// |
//// //// |
//// //// |
//// Author: Rudolf Usselmann //// |
//// rudi@asics.ws //// |
//// //// |
//// //// |
//// D/L from: http://www.opencores.org/cores/generic_fifos/ //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2000-2002 Rudolf Usselmann //// |
//// www.asics.ws //// |
//// rudi@asics.ws //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// |
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// |
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// |
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// |
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// |
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// |
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// |
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// |
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// |
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// |
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// |
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// |
//// POSSIBILITY OF SUCH DAMAGE. //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
|
//// Some minor modifactions are done by Jonas De Craene, JonasDC@opencores.org |
//// in this version. The FIFO output is now registered and push and pop |
//// only works if not full or empty. |
//// The rst signal is removed, now clr is the only reset. |
//// nopush and nopop signal are added to indicate if a push or pop operation |
//// is not executed. |
//// and the memory used in the FIFO is now the same from the mod_sim_exp |
//// opencores project |
|
// CVS Log |
// |
// $Id: generic_fifo_dc.v,v 1.1.1.1 2002-09-25 05:42:02 rudi Exp $ |
// |
// $Date: 2002-09-25 05:42:02 $ |
// $Revision: 1.1.1.1 $ |
// $Author: rudi $ |
// $Locker: $ |
// $State: Exp $ |
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// |
// |
// |
// |
// |
// |
// |
// |
// |
// |
|
//`include "timescale.v" |
|
/* |
|
Description |
=========== |
|
I/Os |
---- |
rd_clk Read Port Clock |
wr_clk Write Port Clock |
rst low active, either sync. or async. master reset (see below how to select) |
clr synchronous clear (just like reset but always synchronous), high active |
re read enable, synchronous, high active |
we read enable, synchronous, high active |
din Data Input |
dout Data Output |
|
full Indicates the FIFO is full (driven at the rising edge of wr_clk) |
empty Indicates the FIFO is empty (driven at the rising edge of rd_clk) |
|
full_n Indicates if the FIFO has space for N entries (driven of wr_clk) |
empty_n Indicates the FIFO has at least N entries (driven of rd_clk) |
|
level indicates the FIFO level: |
2'b00 0-25% full |
2'b01 25-50% full |
2'b10 50-75% full |
2'b11 %75-100% full |
|
Status Timing |
------------- |
All status outputs are registered. They are asserted immediately |
as the full/empty condition occurs, however, there is a 2 cycle |
delay before they are de-asserted once the condition is not true |
anymore. |
|
Parameters |
---------- |
The FIFO takes 3 parameters: |
dw Data bus width |
aw Address bus width (Determines the FIFO size by evaluating 2^aw) |
n N is a second status threshold constant for full_n and empty_n |
If you have no need for the second status threshold, do not |
connect the outputs and the logic should be removed by your |
synthesis tool. |
|
Synthesis Results |
----------------- |
In a Spartan 2e a 8 bit wide, 8 entries deep FIFO, takes 85 LUTs and runs |
at about 116 MHz (IO insertion disabled). The registered status outputs |
are valid after 2.1NS, the combinatorial once take out to 6.5 NS to be |
available. |
|
Misc |
---- |
This design assumes you will do appropriate status checking externally. |
|
IMPORTANT ! writing while the FIFO is full or reading while the FIFO is |
empty will place the FIFO in an undefined state. |
|
*/ |
|
module generic_fifo_dc(rd_clk, wr_clk, clr, din, we, dout, re, |
full, empty, full_n, empty_n, level, nopop, nopush ); |
|
parameter dw=32; |
parameter aw=7; |
parameter n=32; |
parameter max_size = 1<<aw; |
|
input rd_clk, wr_clk, clr; |
input [dw-1:0] din; |
input we; |
output [dw-1:0] dout; |
input re; |
output full; |
output empty; |
output full_n; |
output empty_n; |
output [1:0] level; |
output nopop; |
output nopush; |
|
//////////////////////////////////////////////////////////////////// |
// |
// Local Wires |
// |
|
reg [aw:0] wp; |
wire [aw:0] wp_pl1; |
reg [aw:0] rp; |
wire [aw:0] rp_pl1; |
reg [aw:0] wp_s, rp_s; |
wire [aw:0] diff; |
reg [aw:0] diff_r1, diff_r2; |
reg re_r, we_r; |
reg full, empty, full_n, empty_n; |
reg [1:0] level; |
wire [dw-1:0] dout_ram; |
reg [dw-1:0] dout; |
reg nopop, nopush; |
|
//////////////////////////////////////////////////////////////////// |
// |
// Memory Block |
// |
|
dpram_generic #(2**aw) u0( |
.clkA(wr_clk), |
.waddrA(wp[aw-1:0]), |
.weA(we & !full), |
.dinA(din), |
.clkB(rd_clk), |
.raddrB(rp[aw-1:0]), |
.doutB(dout_ram) |
); |
|
always @(posedge rd_clk) |
if(re & !empty) dout <= #1 dout_ram; |
|
//generic_dpram #(aw, dw)u0( |
// .rclk(rd_clk), |
// .rrst( !rst), |
// .rce(1'b1), |
// .oe(1'b1), |
// .raddr(rp[aw-1:0]), |
// .do(dout), |
// .wclk(wr_clk), |
// .wrst( !rst), |
// .wce(1'b1), |
// .we(we), |
// .waddr(wp[aw-1:0]), |
// .di(din) |
// ); |
|
//////////////////////////////////////////////////////////////////// |
// |
// Read/Write Pointers Logic |
// |
|
always @(posedge wr_clk) |
if(clr) wp <= #1 {aw+1{1'b0}}; |
else |
if(we & !full) wp <= #1 wp_pl1; |
|
assign wp_pl1 = wp + { {aw{1'b0}}, 1'b1}; |
|
always @(posedge rd_clk) |
if(clr) rp <= #1 {aw+1{1'b0}}; |
else |
if(re & !empty) rp <= #1 rp_pl1; |
|
assign rp_pl1 = rp + { {aw{1'b0}}, 1'b1}; |
|
//////////////////////////////////////////////////////////////////// |
// |
// Synchronization Logic |
// |
|
// write pointer |
always @(posedge rd_clk) wp_s <= #1 wp; |
|
// read pointer |
always @(posedge wr_clk) rp_s <= #1 rp; |
|
//////////////////////////////////////////////////////////////////// |
// |
// Registered Full & Empty Flags |
// |
|
always @(posedge rd_clk) |
empty <= #1 (wp_s == rp) | (re & (wp_s == rp_pl1)); |
|
always @(posedge wr_clk) |
full <= #1 ((wp[aw-1:0] == rp_s[aw-1:0]) & (wp[aw] != rp_s[aw])) | |
(we & (wp_pl1[aw-1:0] == rp_s[aw-1:0]) & (wp_pl1[aw] != rp_s[aw])); |
|
//////////////////////////////////////////////////////////////////// |
// |
// Registered Full_n & Empty_n Flags |
// |
|
assign diff = wp-rp; |
|
always @(posedge rd_clk) |
re_r <= #1 re; |
|
always @(posedge rd_clk) |
diff_r1 <= #1 diff; |
|
always @(posedge rd_clk) |
empty_n <= #1 (diff_r1 < n) | ((diff_r1==n) & (re | re_r)); |
|
always @(posedge wr_clk) |
we_r <= #1 we; |
|
always @(posedge wr_clk) |
diff_r2 <= #1 diff; |
|
always @(posedge wr_clk) |
full_n <= #1 (diff_r2 > max_size-n) | ((diff_r2==max_size-n) & (we | we_r)); |
|
always @(posedge wr_clk) |
level <= #1 {2{diff[aw]}} | diff[aw-1:aw-2]; |
|
//////////////////////////////////////////////////////////////////// |
// |
// nopop & nopush Flags |
// |
|
always @(posedge rd_clk) |
nopop <= #1 ((re & empty) | (re & clr)); |
|
always @(posedge wr_clk) |
nopush <= #1 ((we & full) | (we & clr)); |
|
//////////////////////////////////////////////////////////////////// |
// |
// Sanity Check |
// |
|
// synopsys translate_off |
always @(posedge wr_clk) |
if(we & full) |
$display("%m WARNING: Writing while fifo is FULL (%t)",$time); |
|
always @(posedge rd_clk) |
if(re & empty) |
$display("%m WARNING: Reading while fifo is EMPTY (%t)",$time); |
// synopsys translate_on |
|
endmodule |
|
/trunk/rtl/verilog/generic_fifo_dc_gray.v
0,0 → 1,333
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Universal FIFO Dual Clock, gray encoded //// |
//// //// |
//// //// |
//// Author: Rudolf Usselmann //// |
//// rudi@asics.ws //// |
//// //// |
//// //// |
//// D/L from: http://www.opencores.org/cores/generic_fifos/ //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2000-2002 Rudolf Usselmann //// |
//// www.asics.ws //// |
//// rudi@asics.ws //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// |
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// |
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// |
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// |
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// |
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// |
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// |
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// |
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// |
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// |
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// |
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// |
//// POSSIBILITY OF SUCH DAMAGE. //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
|
//// Some minor modifactions are done by Jonas De Craene, JonasDC@opencores.org |
//// in this version. The FIFO output is now registered and push and pop |
//// only works if not full or empty. |
//// The rst signal is removed, now clr is the only reset. |
//// nopush and nopop signal are added to indicate if a push or pop operation |
//// is not executed. |
//// and the memory used in the FIFO is now the same from the mod_sim_exp |
//// opencores project |
|
// CVS Log |
// |
// $Id: generic_fifo_dc_gray.v,v 1.2 2004-01-13 09:11:55 rudi Exp $ |
// |
// $Date: 2004-01-13 09:11:55 $ |
// $Revision: 1.2 $ |
// $Author: rudi $ |
// $Locker: $ |
// $State: Exp $ |
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.1 2003/10/14 09:34:41 rudi |
// Dual clock FIFO Gray Code encoded version. |
// |
// |
// |
// |
// |
|
|
//`include "timescale.v" |
|
/* |
|
Description |
=========== |
|
I/Os |
---- |
rd_clk Read Port Clock |
wr_clk Write Port Clock |
rst low active, either sync. or async. master reset (see below how to select) |
clr synchronous clear (just like reset but always synchronous), high active |
re read enable, synchronous, high active |
we read enable, synchronous, high active |
din Data Input |
dout Data Output |
|
full Indicates the FIFO is full (driven at the rising edge of wr_clk) |
empty Indicates the FIFO is empty (driven at the rising edge of rd_clk) |
|
wr_level indicates the FIFO level: |
2'b00 0-25% full |
2'b01 25-50% full |
2'b10 50-75% full |
2'b11 %75-100% full |
|
rd_level indicates the FIFO level: |
2'b00 0-25% empty |
2'b01 25-50% empty |
2'b10 50-75% empty |
2'b11 %75-100% empty |
|
Status Timing |
------------- |
All status outputs are registered. They are asserted immediately |
as the full/empty condition occurs, however, there is a 2 cycle |
delay before they are de-asserted once the condition is not true |
anymore. |
|
Parameters |
---------- |
The FIFO takes 2 parameters: |
dw Data bus width |
aw Address bus width (Determines the FIFO size by evaluating 2^aw) |
|
Synthesis Results |
----------------- |
In a Spartan 2e a 8 bit wide, 8 entries deep FIFO, takes 97 LUTs and runs |
at about 113 MHz (IO insertion disabled). |
|
Misc |
---- |
This design assumes you will do appropriate status checking externally. |
|
IMPORTANT ! writing while the FIFO is full or reading while the FIFO is |
empty will place the FIFO in an undefined state. |
|
*/ |
|
|
module generic_fifo_dc_gray( rd_clk, wr_clk, clr, din, we, |
dout, re, full, empty, wr_level, rd_level, nopop, nopush ); |
|
parameter dw=32; |
parameter aw=7; |
|
input rd_clk, wr_clk, clr; |
input [dw-1:0] din; |
input we; |
output [dw-1:0] dout; |
input re; |
output full; |
output empty; |
output [1:0] wr_level; |
output [1:0] rd_level; |
output nopop; |
output nopush; |
|
//////////////////////////////////////////////////////////////////// |
// |
// Local Wires |
// |
|
reg [aw:0] wp_bin, wp_gray; |
reg [aw:0] rp_bin, rp_gray; |
reg [aw:0] wp_s, rp_s; |
reg full, empty; |
|
wire [aw:0] wp_bin_next, wp_gray_next; |
wire [aw:0] rp_bin_next, rp_gray_next; |
|
wire [aw:0] wp_bin_x, rp_bin_x; |
reg [aw-1:0] d1, d2; |
|
reg rd_clr, wr_clr; |
reg rd_clr_r, wr_clr_r; |
wire [dw-1:0] dout_ram; |
reg [dw-1:0] dout; |
reg nopop, nopush; |
|
//////////////////////////////////////////////////////////////////// |
// |
// Reset Logic |
// |
|
always @(posedge rd_clk or posedge clr) |
if(clr) rd_clr <= 1'b1; |
else |
if(!rd_clr_r) rd_clr <= 1'b0; // Release Clear |
|
always @(posedge rd_clk or posedge clr) |
if(clr) rd_clr_r <= 1'b1; |
else rd_clr_r <= 1'b0; |
|
always @(posedge wr_clk or posedge clr) |
if(clr) wr_clr <= 1'b1; |
else |
if(!wr_clr_r) wr_clr <= 1'b0; // Release Clear |
|
always @(posedge wr_clk or posedge clr) |
if(clr) wr_clr_r <= 1'b1; |
else wr_clr_r <= 1'b0; |
|
//////////////////////////////////////////////////////////////////// |
// |
// Memory Block |
// |
|
|
dpram_generic #(2**aw) u0( |
.clkA(wr_clk), |
.waddrA(wp_bin[aw-1:0]), |
.weA(we & !full), |
.dinA(din), |
.clkB(rd_clk), |
.raddrB(rp_bin[aw-1:0]), |
.doutB(dout_ram) |
); |
|
//generic_dpram #(aw,dw) u0( |
// .rclk( rd_clk ), |
// .rrst( !rd_rst ), |
// .rce( 1'b1 ), |
// .oe( 1'b1 ), |
// .raddr( rp_bin[aw-1:0] ), |
// .do( dout ), |
// .wclk( wr_clk ), |
// .wrst( !wr_rst ), |
// .wce( 1'b1 ), |
// .we( we ), |
// .waddr( wp_bin[aw-1:0] ), |
// .di( din ) |
// ); |
|
always @(posedge rd_clk) |
if(re & !empty) dout <= #1 dout_ram; |
|
//////////////////////////////////////////////////////////////////// |
// |
// Read/Write Pointers Logic |
// |
|
always @(posedge wr_clk) |
if(wr_clr) wp_bin <= {aw+1{1'b0}}; |
else |
if(we & !full) wp_bin <= wp_bin_next; |
|
always @(posedge wr_clk) |
if(wr_clr) wp_gray <= {aw+1{1'b0}}; |
else |
if(we & !full) wp_gray <= wp_gray_next; |
|
assign wp_bin_next = wp_bin + {{aw{1'b0}},1'b1}; |
assign wp_gray_next = wp_bin_next ^ {1'b0, wp_bin_next[aw:1]}; |
|
always @(posedge rd_clk) |
if(rd_clr) rp_bin <= {aw+1{1'b0}}; |
else |
if(re & !empty) rp_bin <= rp_bin_next; |
|
always @(posedge rd_clk) |
if(rd_clr) rp_gray <= {aw+1{1'b0}}; |
else |
if(re & !empty) rp_gray <= rp_gray_next; |
|
assign rp_bin_next = rp_bin + {{aw{1'b0}},1'b1}; |
assign rp_gray_next = rp_bin_next ^ {1'b0, rp_bin_next[aw:1]}; |
|
//////////////////////////////////////////////////////////////////// |
// |
// Synchronization Logic |
// |
|
// write pointer |
always @(posedge rd_clk) wp_s <= wp_gray; |
|
// read pointer |
always @(posedge wr_clk) rp_s <= rp_gray; |
|
//////////////////////////////////////////////////////////////////// |
// |
// Registered Full & Empty Flags |
// |
|
assign wp_bin_x = wp_s ^ {1'b0, wp_bin_x[aw:1]}; // convert gray to binary |
assign rp_bin_x = rp_s ^ {1'b0, rp_bin_x[aw:1]}; // convert gray to binary |
|
always @(posedge rd_clk) |
empty <= (wp_s == rp_gray) | (re & (wp_s == rp_gray_next)); |
|
always @(posedge wr_clk) |
full <= ((wp_bin[aw-1:0] == rp_bin_x[aw-1:0]) & (wp_bin[aw] != rp_bin_x[aw])) | |
(we & (wp_bin_next[aw-1:0] == rp_bin_x[aw-1:0]) & (wp_bin_next[aw] != rp_bin_x[aw])); |
|
//////////////////////////////////////////////////////////////////// |
// |
// nopop & nopush Flags |
// |
|
always @(posedge rd_clk) |
nopop <= #1 ((re & empty) | (re & clr)); |
|
always @(posedge wr_clk) |
nopush <= #1 ((we & full) | (we & clr)); |
|
//////////////////////////////////////////////////////////////////// |
// |
// Registered Level Indicators |
// |
reg [1:0] wr_level; |
reg [1:0] rd_level; |
reg [aw-1:0] wp_bin_xr, rp_bin_xr; |
reg full_rc; |
reg full_wc; |
|
always @(posedge wr_clk) full_wc <= full; |
always @(posedge wr_clk) rp_bin_xr <= ~rp_bin_x[aw-1:0] + {{aw-1{1'b0}}, 1'b1}; |
always @(posedge wr_clk) d1 <= wp_bin[aw-1:0] + rp_bin_xr[aw-1:0]; |
|
always @(posedge wr_clk) wr_level <= {d1[aw-1] | full | full_wc, d1[aw-2] | full | full_wc}; |
|
always @(posedge rd_clk) wp_bin_xr <= ~wp_bin_x[aw-1:0]; |
always @(posedge rd_clk) d2 <= rp_bin[aw-1:0] + wp_bin_xr[aw-1:0]; |
|
always @(posedge rd_clk) full_rc <= full; |
always @(posedge rd_clk) rd_level <= full_rc ? 2'h0 : {d2[aw-1] | empty, d2[aw-2] | empty}; |
|
//////////////////////////////////////////////////////////////////// |
// |
// Sanity Check |
// |
|
// synopsys translate_off |
always @(posedge wr_clk) |
if(we && full) |
$display("%m WARNING: Writing while fifo is FULL (%t)",$time); |
|
always @(posedge rd_clk) |
if(re && empty) |
$display("%m WARNING: Reading while fifo is EMPTY (%t)",$time); |
// synopsys translate_on |
|
endmodule |
|
/trunk/rtl/vhdl/ram/dpram_generic.vhd
56,14 → 56,15
depth : integer := 2 |
); |
port ( |
clk : in std_logic; |
-- write port |
waddr : in std_logic_vector(log2(depth)-1 downto 0); |
we : in std_logic; |
din : in std_logic_vector(31 downto 0); |
-- read port |
raddr : in std_logic_vector(log2(depth)-1 downto 0); |
dout : out std_logic_vector(31 downto 0) |
-- write port A |
clkA : in std_logic; |
waddrA : in std_logic_vector(log2(depth)-1 downto 0); |
weA : in std_logic; |
dinA : in std_logic_vector(31 downto 0); |
-- read port B |
clkB : in std_logic; |
raddrB : in std_logic_vector(log2(depth)-1 downto 0); |
doutB : out std_logic_vector(31 downto 0) |
); |
end dpram_generic; |
|
70,11 → 71,11
architecture behavorial of dpram_generic is |
-- the memory |
type ram_type is array (depth-1 downto 0) of std_logic_vector (31 downto 0); |
signal RAM : ram_type := (others => (others => '0')); |
shared variable RAM : ram_type := (others => (others => '0')); |
|
-- xilinx constraint to use blockram resources |
attribute ram_style : string; |
attribute ram_style of ram:signal is "block"; |
attribute ram_style of ram:variable is "block"; |
-- altera constraints: |
-- for smal depths: |
-- if the synthesis option "allow any size of RAM to be inferred" is on, these lines |
81,16 → 82,23
-- may be left commented. |
-- uncomment this attribute if that option is off and you know wich primitives should be used. |
--attribute ramstyle : string; |
--attribute ramstyle of RAM : signal is "M9K, no_rw_check"; |
--attribute ramstyle of RAM : variable is "M9K, no_rw_check"; |
begin |
process (clk) |
process (clkA) |
begin |
if (clk'event and clk = '1') then |
if (we = '1') then |
RAM(conv_integer(waddr)) <= din; |
if rising_edge(clkA) then |
if (weA = '1') then |
RAM(conv_integer(waddrA)) := dinA; |
end if; |
dout <= RAM(conv_integer(raddr)); |
end if; |
end process; |
|
process (clkB) |
begin |
if rising_edge(clkB) then |
doutB <= RAM(conv_integer(raddrB)); |
end if; |
end process; |
|
end behavorial; |
|
/trunk/rtl/vhdl/ram/tdpram_asym.vhd
62,13 → 62,14
device : string := "xilinx" |
); |
port ( |
clk : in std_logic; |
-- port A (widthA)-bit |
clkA : in std_logic; |
addrA : in std_logic_vector(log2((depthB*32)/widthA)-1 downto 0); |
weA : in std_logic; |
dinA : in std_logic_vector(widthA-1 downto 0); |
doutA : out std_logic_vector(widthA-1 downto 0); |
-- port B 32-bit |
clkB : in std_logic; |
addrB : in std_logic_vector(log2(depthB)-1 downto 0); |
weB : in std_logic; |
dinB : in std_logic_vector(31 downto 0); |
91,12 → 92,9
-- - the RAM has two write ports, |
-- - the RAM has only one write port whose data width is maxWIDTH |
-- In all other cases, ram can be a signal. |
shared variable ram : ramType := (others => (others => '0')); |
signal clkA : std_logic; |
signal clkB : std_logic; |
shared variable ram : ramType := (others => (others => '0')); |
|
begin |
clkA <= clk; |
process (clkA) |
begin |
if rising_edge(clkA) then |
107,7 → 105,6
end if; |
end process; |
|
clkB <= clk; |
process (clkB) |
begin |
if rising_edge(clkB) then |
149,9 → 146,9
end generate unpack; |
|
--port B |
process(clk) |
process(clkB) |
begin |
if(rising_edge(clk)) then |
if(rising_edge(clkB)) then |
if(weB = '1') then |
ram(conv_integer(addrB)) <= wB_local; |
end if; |
160,9 → 157,9
end process; |
|
-- port A |
process(clk) |
process(clkA) |
begin |
if(rising_edge(clk)) then |
if(rising_edge(clkA)) then |
doutA <= ram(conv_integer(addrA) / R )(conv_integer(addrA) mod R); |
if(weA ='1') then |
ram(conv_integer(addrA) / R)(conv_integer(addrA) mod R) <= dinA; |
/trunk/rtl/vhdl/ram/dpramblock_asym.vhd
62,14 → 62,15
device : string := "xilinx" |
); |
port ( |
clk : in std_logic; |
-- write port |
waddr : in std_logic_vector(log2((width*depth)/32)-1 downto 0); |
we : in std_logic; |
din : in std_logic_vector(31 downto 0); |
-- read port |
raddr : in std_logic_vector(log2(depth)-1 downto 0); |
dout : out std_logic_vector(width-1 downto 0) |
-- write port A |
clkA : in std_logic; |
waddrA : in std_logic_vector(log2((width*depth)/32)-1 downto 0); |
weA : in std_logic; |
dinA : in std_logic_vector(31 downto 0); |
-- read port B |
clkB : in std_logic; |
raddrB : in std_logic_vector(log2(depth)-1 downto 0); |
doutB : out std_logic_vector(width-1 downto 0) |
); |
end dpramblock_asym; |
|
92,18 → 93,20
device => device |
) |
port map( |
clk => clk, |
|
-- write port |
waddr => waddr, |
we => we, |
din => din((i+1)*RAMwrwidth-1 downto RAMwrwidth*i), |
clkA => clkA, |
waddrA => waddrA, |
weA => weA, |
dinA => dinA((i+1)*RAMwrwidth-1 downto RAMwrwidth*i), |
-- read port |
raddr => raddr, |
dout => dout_RAM(i) |
clkB => clkB, |
raddrB => raddrB, |
doutB => dout_RAM(i) |
); |
|
map_output : for j in 0 to nrRAMs-1 generate |
dout(j*32+(i+1)*RAMwrwidth-1 downto j*32+i*RAMwrwidth) |
doutB(j*32+(i+1)*RAMwrwidth-1 downto j*32+i*RAMwrwidth) |
<= dout_RAM(i)((j+1)*RAMwrwidth-1 downto j*RAMwrwidth); |
end generate; |
end generate; |
/trunk/rtl/vhdl/ram/tdpramblock_asym.vhd
61,14 → 61,15
width : integer := 512; -- width of portB |
device : string := "xilinx" |
); |
port ( |
clk : in std_logic; |
port ( |
-- port A 32-bit |
clkA : in std_logic; |
addrA : in std_logic_vector(log2((width*depth)/32)-1 downto 0); |
weA : in std_logic; |
dinA : in std_logic_vector(31 downto 0); |
doutA : out std_logic_vector(31 downto 0); |
-- port B (width)-bit |
clkB : in std_logic; |
addrB : in std_logic_vector(log2(depth)-1 downto 0); |
weB : in std_logic; |
dinB : in std_logic_vector(width-1 downto 0); |
95,13 → 96,14
device => device |
) |
port map( |
clk => clk, |
-- port A (widthA)-bit |
clkA => clkA, |
addrA => addrA, |
weA => weA, |
dinA => dinA((i+1)*RAMwidthA-1 downto RAMwidthA*i), |
doutA => doutA((i+1)*RAMwidthA-1 downto RAMwidthA*i), |
-- port B 32-bit |
clkB => clkB, |
addrB => addrB, |
weB => weB, |
dinB => dinB_RAM(i), |
/trunk/rtl/vhdl/ram/dpram_asym.vhd
61,15 → 61,16
wrwidth : integer := 2; -- write width, must be smaller than or equal to 32 |
device : string := "xilinx" -- device template to use |
); |
port ( |
clk : in std_logic; |
port ( |
-- write port |
waddr : in std_logic_vector(log2((rddepth*32)/wrwidth)-1 downto 0); |
we : in std_logic; |
din : in std_logic_vector(wrwidth-1 downto 0); |
clkA : in std_logic; |
waddrA : in std_logic_vector(log2((rddepth*32)/wrwidth)-1 downto 0); |
weA : in std_logic; |
dinA : in std_logic_vector(wrwidth-1 downto 0); |
-- read port |
raddr : in std_logic_vector(log2(rddepth)-1 downto 0); |
dout : out std_logic_vector(31 downto 0) |
clkB : in std_logic; |
raddrB : in std_logic_vector(log2(rddepth)-1 downto 0); |
doutB : out std_logic_vector(31 downto 0) |
); |
end dpram_asym; |
|
82,21 → 83,29
xilinx_device : if device="xilinx" generate |
-- the memory |
type ram_type is array (wrdepth-1 downto 0) of std_logic_vector (wrwidth-1 downto 0); |
signal RAM : ram_type := (others => (others => '0')); |
shared variable RAM : ram_type := (others => (others => '0')); |
|
-- xilinx constraint to use blockram resources |
attribute ram_style : string; |
attribute ram_style of ram:signal is "block"; |
attribute ram_style of RAM:variable is "block"; |
begin |
process (clk) |
-- Write port A |
process (clkA) |
begin |
if (clk'event and clk = '1') then |
if (we = '1') then |
RAM(conv_integer(waddr)) <= din; |
if rising_edge(clkA) then |
if (weA = '1') then |
RAM(conv_integer(waddrA)) := dinA; |
end if; |
end if; |
end process; |
|
-- Read port B |
process (clkB) |
begin |
if rising_edge(clkB) then |
for i in 0 to R-1 loop |
dout((i+1)*wrwidth-1 downto i*wrwidth) |
<= RAM(conv_integer(raddr & conv_std_logic_vector(i,log2(R)))); |
doutB((i+1)*wrwidth-1 downto i*wrwidth) |
<= RAM(conv_integer(raddrB & conv_std_logic_vector(i,log2(R)))); |
end loop; |
end if; |
end process; |
107,7 → 116,7
type word_t is array(R-1 downto 0) of std_logic_vector(wrwidth-1 downto 0); |
type ram_t is array (0 to rddepth-1) of word_t; |
|
signal ram : ram_t; |
shared variable ram : ram_t; |
signal q_local : word_t; |
-- altera constraints: |
-- for smal depths: |
118,18 → 127,24
--attribute ramstyle of RAM : signal is "M9K, no_rw_check"; |
begin |
unpack: for i in 0 to R - 1 generate |
dout(wrwidth*(i+1) - 1 downto wrwidth*i) <= q_local(i); |
doutB(wrwidth*(i+1) - 1 downto wrwidth*i) <= q_local(i); |
end generate unpack; |
|
process(clk, we) |
process(clkA) |
begin |
if(rising_edge(clk)) then |
if(we = '1') then |
ram(conv_integer(waddr)/R)(conv_integer(waddr) mod R) <= din; |
if(rising_edge(clkA)) then |
if(weA = '1') then |
ram(conv_integer(waddrA)/R)(conv_integer(waddrA) mod R) := dinA; |
end if; |
q_local <= ram(conv_integer(raddr)); |
end if; |
end process; |
|
process(clkB) |
begin |
if(rising_edge(clkB)) then |
q_local <= ram(conv_integer(raddrB)); |
end if; |
end process; |
end generate; |
|
end behavorial; |
/trunk/rtl/vhdl/interface/axi/msec_ipcore_axilite.vhd
99,7 → 99,7
C_NR_STAGES_TOTAL : integer := 96; |
C_NR_STAGES_LOW : integer := 32; |
C_SPLIT_PIPELINE : boolean := true; |
C_FIFO_DEPTH : integer := 32; |
C_FIFO_AW : integer := 7; |
C_MEM_STYLE : string := "asym"; -- xil_prim, generic, asym are valid options |
C_FPGA_MAN : string := "xilinx"; -- xilinx, altera are valid options |
-- Bus protocol parameters |
110,6 → 110,7
); |
port( |
--USER ports |
core_clk : in std_logic; |
calc_time : out std_logic; |
IntrEvent : out std_logic; |
------------------------- |
394,13 → 395,14
C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL, |
C_NR_STAGES_LOW => C_NR_STAGES_LOW, |
C_SPLIT_PIPELINE => C_SPLIT_PIPELINE, |
C_FIFO_DEPTH => C_FIFO_DEPTH, |
C_FIFO_AW => C_FIFO_AW, |
C_MEM_STYLE => C_MEM_STYLE, |
C_FPGA_MAN => C_FPGA_MAN |
) |
port map( |
clk => S_AXI_ACLK, |
reset => reset, |
bus_clk => S_AXI_ACLK, |
core_clk => core_clk, |
reset => reset, |
-- operand memory interface (plb shared memory) |
write_enable => core_write_enable, |
data_in => S_AXI_WDATA(31 downto 0), |
/trunk/rtl/vhdl/interface/plb/mod_sim_exp_IPcore.vhd
162,7 → 162,7
C_NR_STAGES_TOTAL : integer := 96; |
C_NR_STAGES_LOW : integer := 32; |
C_SPLIT_PIPELINE : boolean := true; |
C_FIFO_DEPTH : integer := 32; |
C_FIFO_AW : integer := 7; |
C_MEM_STYLE : string := "xil_prim"; -- xil_prim, generic, asym are valid options |
C_FPGA_MAN : string := "xilinx"; -- xilinx, altera are valid options |
-- ADD USER GENERICS ABOVE THIS LINE --------------- |
200,7 → 200,8
( |
-- ADD USER PORTS BELOW THIS LINE ------------------ |
--USER ports added here |
calc_time : out std_logic; |
calc_time : out std_logic; |
core_clk : in std_logic; |
-- ADD USER PORTS ABOVE THIS LINE ------------------ |
|
-- DO NOT EDIT BELOW THIS LINE --------------------- |
580,7 → 581,7
C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL, |
C_NR_STAGES_LOW => C_NR_STAGES_LOW, |
C_SPLIT_PIPELINE => C_SPLIT_PIPELINE, |
C_FIFO_DEPTH => C_FIFO_DEPTH, |
C_FIFO_AW => C_FIFO_AW, |
C_MEM_STYLE => C_MEM_STYLE, |
C_FPGA_MAN => C_FPGA_MAN, |
-- MAP USER GENERICS ABOVE THIS LINE --------------- |
596,6 → 597,7
-- MAP USER PORTS BELOW THIS LINE ------------------ |
--USER ports mapped here |
calc_time => calc_time, |
core_clk => core_clk, |
-- MAP USER PORTS ABOVE THIS LINE ------------------ |
|
Bus2IP_Clk => ipif_Bus2IP_Clk, |
/trunk/rtl/vhdl/interface/plb/user_logic.vhd
100,7 → 100,7
C_NR_STAGES_TOTAL : integer := 96; |
C_NR_STAGES_LOW : integer := 32; |
C_SPLIT_PIPELINE : boolean := true; |
C_FIFO_DEPTH : integer := 32; |
C_FIFO_AW : integer := 7; |
C_MEM_STYLE : string := "xil_prim"; -- xil_prim, generic, asym are valid options |
C_FPGA_MAN : string := "xilinx"; -- xilinx, altera are valid options |
-- ADD USER GENERICS ABOVE THIS LINE --------------- |
118,8 → 118,8
( |
-- ADD USER PORTS BELOW THIS LINE ------------------ |
--USER ports added here |
calc_time : out std_logic; |
-- ctrl_sigs : out std_logic_vector( downto ); |
calc_time : out std_logic; |
core_clk : in std_logic; |
-- ADD USER PORTS ABOVE THIS LINE ------------------ |
|
-- DO NOT EDIT BELOW THIS LINE --------------------- |
406,13 → 406,14
C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL, |
C_NR_STAGES_LOW => C_NR_STAGES_LOW, |
C_SPLIT_PIPELINE => C_SPLIT_PIPELINE, |
C_FIFO_DEPTH => C_FIFO_DEPTH, |
C_FIFO_AW => C_FIFO_AW, |
C_MEM_STYLE => C_MEM_STYLE, |
C_FPGA_MAN => C_FPGA_MAN |
) |
port map( |
clk => Bus2IP_Clk, |
reset => Bus2IP_Reset, |
core_clk => core_clk, |
bus_clk => Bus2IP_Clk, |
reset => Bus2IP_Reset, |
-- operand memory interface (plb shared memory) |
write_enable => core_write_enable, |
data_in => core_data_in, |
/trunk/rtl/vhdl/core/fifo_generic.vhd
File deleted
/trunk/rtl/vhdl/core/pulse_cdc.vhd
0,0 → 1,97
---------------------------------------------------------------------- |
---- pulse_cdc ---- |
---- ---- |
---- This file is part of the ---- |
---- Modular Simultaneous Exponentiation Core project ---- |
---- http://www.opencores.org/cores/mod_sim_exp/ ---- |
---- ---- |
---- Description ---- |
---- transfers a pulse (1clk wide) from clock domain A to ---- |
---- clock domain B by using a toggling signal. This design ---- |
---- avoids metastable states ---- |
---- ---- |
---- Dependencies: none ---- |
---- ---- |
---- Authors: ---- |
---- - Geoffrey Ottoy, DraMCo research group ---- |
---- - Jonas De Craene, JonasDC@opencores.org ---- |
---- ---- |
---------------------------------------------------------------------- |
---- ---- |
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ---- |
---- ---- |
---- This source file may be used and distributed without ---- |
---- restriction provided that this copyright statement is not ---- |
---- removed from the file and that any derivative work contains ---- |
---- the original copyright notice and the associated disclaimer. ---- |
---- ---- |
---- This source file is free software; you can redistribute it ---- |
---- and/or modify it under the terms of the GNU Lesser General ---- |
---- Public License as published by the Free Software Foundation; ---- |
---- either version 2.1 of the License, or (at your option) any ---- |
---- later version. ---- |
---- ---- |
---- This source is distributed in the hope that it will be ---- |
---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- |
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- |
---- PURPOSE. See the GNU Lesser General Public License for more ---- |
---- details. ---- |
---- ---- |
---- You should have received a copy of the GNU Lesser General ---- |
---- Public License along with this source; if not, download it ---- |
---- from http://www.opencores.org/lgpl.shtml ---- |
---- ---- |
---------------------------------------------------------------------- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_unsigned.all; |
|
entity pulse_cdc is |
port ( |
reset : in std_logic; |
clkA : in std_logic; |
pulseA : in std_logic; |
clkB : in std_logic; |
pulseB : out std_logic |
); |
end pulse_cdc; |
|
|
architecture arch of pulse_cdc is |
signal pulseA_d : std_logic; |
signal toggle : std_logic := '0'; |
signal toggle_d, toggle_d2, toggle_d3 : std_logic; |
begin |
|
-- Convert pulse from clock domain A to a toggling signal |
PulseAtoToggle : process (clkA, reset) |
begin |
if reset='1' then |
toggle <= '0'; |
else |
if rising_edge(clkA) then |
pulseA_d <= pulseA; |
toggle <= toggle xor (pulseA and not pulseA_d); |
end if; |
end if; |
end process; |
|
-- Convert toggling signal to a pulse of 1clk wide to clock domain B |
ToggletoPulseB : process (clkB, reset) |
begin |
if reset='1' then |
toggle_d <= '0'; |
toggle_d2 <= '0'; |
toggle_d3 <= '0'; |
else |
if rising_edge(clkB) then |
toggle_d <= toggle; -- this signal may have metastability isues |
toggle_d2 <= toggle_d; -- stable now |
toggle_d3 <= toggle_d2; |
end if; |
end if; |
end process; |
|
pulseB <= toggle_d2 xor toggle_d3; |
end arch; |
/trunk/rtl/vhdl/core/fifo_primitive.vhd
54,16 → 54,17
|
entity fifo_primitive is |
port ( |
clk : in std_logic; |
din : in std_logic_vector (31 downto 0); |
dout : out std_logic_vector (31 downto 0); |
empty : out std_logic; |
full : out std_logic; |
push : in std_logic; |
pop : in std_logic; |
reset : in std_logic; |
nopop : out std_logic; |
nopush : out std_logic |
push_clk : in std_logic; |
pop_clk : in std_logic; |
din : in std_logic_vector (31 downto 0); |
dout : out std_logic_vector (31 downto 0); |
empty : out std_logic; |
full : out std_logic; |
push : in std_logic; |
pop : in std_logic; |
reset : in std_logic; |
nopop : out std_logic; |
nopush : out std_logic |
); |
end fifo_primitive; |
|
86,13 → 87,13
push_i <= push and (not reset_i); |
|
-- makes the reset at least three clk_cycles long |
RESET_PROC: process (reset, clk) |
RESET_PROC: process (reset, push_clk) |
variable clk_counter : integer range 0 to 3 := 3; |
begin |
if reset = '1' then |
reset_i <= '1'; |
clk_counter := 3; |
elsif rising_edge(clk) then |
elsif rising_edge(push_clk) then |
if clk_counter = 0 then |
clk_counter := 0; |
reset_i <= '0'; |
109,7 → 110,7
ALMOST_FULL_OFFSET => X"00080", -- Sets almost full threshold |
DATA_WIDTH => 36, -- Sets data width to 4, 9, 18, or 36 |
DO_REG => 1, -- Enable output register (0 or 1) Must be 1 if EN_SYN = "FALSE" |
EN_SYN => TRUE, -- Specifies FIFO as dual-clock ("FALSE") or Synchronous ("TRUE") |
EN_SYN => FALSE, -- Specifies FIFO as dual-clock ("FALSE") or Synchronous ("TRUE") |
FIFO_MODE => "FIFO18_36", -- Sets mode to FIFO18 or FIFO18_36 |
FIRST_WORD_FALL_THROUGH => FALSE, -- Sets the FIFO FWFT to "TRUE" or "FALSE" |
INIT => X"000000000", -- Initial values on output port |
135,8 → 136,8
RST => reset_i, -- 1-bit reset input |
RSTREG => reset_i, -- 1-bit output register set/reset |
-- WRCLK, RDCLK: 1-bit (each) Clocks |
RDCLK => clk, -- 1-bit read clock input |
WRCLK => clk, -- 1-bit write clock input |
RDCLK => pop_clk, -- 1-bit read clock input |
WRCLK => push_clk, -- 1-bit write clock input |
WREN => push_i -- 1-bit write enable input |
); |
|
/trunk/rtl/vhdl/core/operand_ram_gen.vhd
61,9 → 61,9
); |
port( |
-- global ports |
clk : in std_logic; |
collision : out std_logic; -- 1 if simultaneous write on RAM |
-- bus side connections (32-bit serial) |
bus_clk : in std_logic; |
write_operand : in std_logic; -- write_enable |
operand_in_sel : in std_logic_vector(log2(depth)-1 downto 0); -- operand to write to |
operand_addr : in std_logic_vector(log2(width/32)-1 downto 0); -- address of operand word to write |
71,6 → 71,7
result_out : out std_logic_vector(31 downto 0); -- operand out, reading is always result operand |
operand_out_sel : in std_logic_vector(log2(depth)-1 downto 0); -- operand to give to multiplier |
-- multiplier side connections (width-bit parallel) |
core_clk : in std_logic; |
result_dest_op : in std_logic_vector(log2(depth)-1 downto 0); -- operand select for result |
operand_out : out std_logic_vector(width-1 downto 0); -- operand out to multiplier |
write_result : in std_logic; -- write enable for multiplier side |
88,22 → 89,22
-- total RAM structure signals |
signal weA_RAM : std_logic_vector(nrRAMs-1 downto 0); |
type wordsplit is array (nrRAMs-1 downto 0) of std_logic_vector(31 downto 0); |
signal doutB_RAM : wordsplit; |
signal doutA_RAM : wordsplit; |
--- PORT A : 32-bit write | (width)-bit read |
signal dinA : std_logic_vector(31 downto 0); |
signal doutA : std_logic_vector(width-1 downto 0); |
signal doutA : std_logic_vector(31 downto 0); |
signal weA : std_logic; |
signal addrA : std_logic_vector(RAMselect_aw-1 downto 0); |
signal op_selA : std_logic_vector(RAMdepth_aw-1 downto 0); |
--- PORT B : 32-bit read | (width)-bit write |
signal dinB : std_logic_vector(width-1 downto 0); |
signal doutB : std_logic_vector(31 downto 0); |
signal doutB : std_logic_vector(width-1 downto 0); |
signal weB : std_logic; |
signal addrB : std_logic_vector(RAMselect_aw-1 downto 0); |
signal op_selB : std_logic_vector(RAMdepth_aw-1 downto 0); |
|
signal write_operand_i : std_logic; |
signal op_selA_i : std_logic_vector(RAMdepth_aw-1 downto 0); |
signal op_selB_i : std_logic_vector(RAMdepth_aw-1 downto 0); |
begin |
|
-- WARNING: Very Important! |
115,29 → 116,29
-- the dual port ram has a depth of 4 (each layer contains an operand) |
-- result is always stored in position 3 |
-- doutb is always result |
with write_operand_i select |
op_selA_i <= operand_in_sel when '1', |
with write_result select |
op_selB_i <= result_dest_op when '1', |
operand_out_sel when others; |
|
-- map signals to RAM |
-- PORTA |
weA <= write_operand_i; |
op_selA <= op_selA_i; |
op_selA <= operand_in_sel; |
addrA <= operand_addr; |
dinA <= operand_in; |
operand_out <= doutA; |
result_out <= doutA; |
-- PORT B |
weB <= write_result; |
op_selB <= result_dest_op; -- portB locked to result operand |
op_selB <= op_selB_i; -- portB locked to result operand |
addrB <= operand_addr; |
dinB <= result_in; |
result_out <= doutB; |
operand_out <= doutB; |
|
-- generate (width/32) blocks of 32-bit ram with a given depth |
-- these rams are tyed together to form the following structure |
-- True dual port ram: |
-- - PORT A : 32-bit write | (width)-bit read |
-- - PORT B : 32-bit read | (width)-bit write |
-- - PORT A : 32-bit write | 32-bit read |
-- - PORT B : (width)-bit read | (width)-bit write |
-- ^ ^ |
-- addres addr op_sel |
-- |
148,17 → 149,17
) |
port map( |
-- port A : 32-bit |
clkA => clk, |
clkA => bus_clk, |
addrA => op_selA, |
weA => weA_RAM(i), |
dinA => dinA, |
doutA => doutA(((i+1)*32)-1 downto i*32), |
doutA => doutA_RAM(i), |
-- port B : 32-bit |
clkB => clk, |
clkB => core_clk, |
addrB => op_selB, |
weB => weB, |
dinB => dinB(((i+1)*32)-1 downto i*32), |
doutB => doutB_RAM(i) |
doutB => doutB(((i+1)*32)-1 downto i*32) |
); |
-- demultiplexer for write enable A signal |
process (addrA, weA) |
171,7 → 172,7
end process; |
end generate; |
-- PORTB 32-bit read |
doutB <= doutB_RAM(conv_integer(addrB)) when (conv_integer(addrB)<nrRAMs) |
doutA <= doutA_RAM(conv_integer(addrA)) when (conv_integer(addrA)<nrRAMs) |
else (others=>'0'); |
|
end Behavioral; |
/trunk/rtl/vhdl/core/operand_ram_asym.vhd
68,9 → 68,9
); |
port( |
-- global ports |
clk : in std_logic; |
collision : out std_logic; -- 1 if simultaneous write on RAM |
-- bus side connections (32-bit serial) |
bus_clk : in std_logic; |
write_operand : in std_logic; -- write_enable |
operand_in_sel : in std_logic_vector(log2(depth)-1 downto 0); -- operand to write to |
operand_addr : in std_logic_vector(log2(width/32)-1 downto 0); -- address of operand word to write |
78,6 → 78,7
result_out : out std_logic_vector(31 downto 0); -- operand out, reading is always result operand |
operand_out_sel : in std_logic_vector(log2(depth)-1 downto 0); -- operand to give to multiplier |
-- multiplier side connections (width-bit parallel) |
core_clk : in std_logic; |
result_dest_op : in std_logic_vector(log2(depth)-1 downto 0); -- operand select for result |
operand_out : out std_logic_vector(width-1 downto 0); -- operand out to multiplier |
write_result : in std_logic; -- write enable for multiplier side |
126,13 → 127,14
device => device |
) |
port map( |
clk => clk, |
-- port A 32-bit |
clkA => bus_clk, |
addrA => addrA_single, |
weA => write_operand_i, |
dinA => operand_in, |
doutA => result_out, |
-- port B (width)-bit |
clkB => core_clk, |
addrB => mult_op_sel, |
weB => write_result, |
dinB => result_in, |
159,13 → 161,14
device => device |
) |
port map( |
clk => clk, |
-- port A 32-bit |
clkA => bus_clk, |
addrA => addrA, |
weA => weA_RAM(i), |
dinA => operand_in, |
doutA => doutA_RAM(i), |
-- port B (width)-bit |
clkB => core_clk, |
addrB => mult_op_sel, |
weB => write_result, |
dinB => result_in((i+1)*RAMblock_maxwidth-1 downto i*RAMblock_maxwidth), |
208,13 → 211,14
device => device |
) |
port map( |
clk => clk, |
-- port A 32-bit |
clkA => bus_clk, |
addrA => addrA_part, |
weA => weA_part, |
dinA => operand_in, |
doutA => doutA_RAM(i), |
-- port B (width)-bit |
clkB => core_clk, |
addrB => mult_op_sel, |
weB => write_result, |
dinB => result_in(width-1 downto i*RAMblock_maxwidth), |
/trunk/rtl/vhdl/core/modulus_ram_asym.vhd
64,11 → 64,11
generic( |
width : integer := 1536; -- must be a multiple of 32 |
depth : integer := 2; -- nr of moduluses |
device : string := "xilinx" |
device : string := "altera" |
); |
port( |
clk : in std_logic; |
-- bus side |
bus_clk : in std_logic; |
write_modulus : in std_logic; -- write enable |
modulus_in_sel : in std_logic_vector(log2(depth)-1 downto 0); -- modulus operand to write to |
modulus_addr : in std_logic_vector(log2((width)/32)-1 downto 0); -- modulus word(32-bit) address |
75,6 → 75,7
modulus_in : in std_logic_vector(31 downto 0); -- modulus word data in |
modulus_sel : in std_logic_vector(log2(depth)-1 downto 0); -- selects the modulus to use for multiplications |
-- multiplier side |
core_clk : in std_logic; |
modulus_out : out std_logic_vector(width-1 downto 0) |
); |
end modulus_ram_asym; |
107,14 → 108,15
device => device |
) |
port map( |
clk => clk, |
-- write port |
waddr => waddr, |
we => write_modulus, |
din => modulus_in, |
clkA => bus_clk, |
waddrA => waddr, |
weA => write_modulus, |
dinA => modulus_in, |
-- read port |
raddr => modulus_sel, |
dout => modulus_out |
clkB => core_clk, |
raddrB => modulus_sel, |
doutB => modulus_out |
); |
end generate; |
|
135,14 → 137,15
device => device |
) |
port map( |
clk => clk, |
-- write port |
waddr => waddr, |
we => we_RAM(i), |
din => modulus_in, |
clkA => bus_clk, |
waddrA => waddr, |
weA => we_RAM(i), |
dinA => modulus_in, |
-- read port |
raddr => modulus_sel, |
dout => modulus_out((i+1)*RAMblock_maxwidth-1 downto i*RAMblock_maxwidth) |
clkB => core_clk, |
raddrB => modulus_sel, |
doutB => modulus_out((i+1)*RAMblock_maxwidth-1 downto i*RAMblock_maxwidth) |
); |
-- we |
process (write_modulus, modulus_addr) |
169,14 → 172,15
device => device |
) |
port map( |
clk => clk, |
-- write port |
waddr => waddr_part, |
we => we_part, |
din => modulus_in, |
clkA => bus_clk, |
waddrA => waddr_part, |
weA => we_part, |
dinA => modulus_in, |
-- read port |
raddr => modulus_sel, |
dout => modulus_out(width-1 downto i*RAMblock_maxwidth) |
clkB => core_clk, |
raddrB => modulus_sel, |
doutB => modulus_out(width-1 downto i*RAMblock_maxwidth) |
); |
|
-- we_part |
/trunk/rtl/vhdl/core/modulus_ram_gen.vhd
61,8 → 61,8
depth : integer := 2 -- nr of moduluses |
); |
port( |
clk : in std_logic; |
-- bus side |
bus_clk : in std_logic; |
write_modulus : in std_logic; -- write enable |
modulus_in_sel : in std_logic_vector(log2(depth)-1 downto 0); -- modulus operand to write to |
modulus_addr : in std_logic_vector(log2((width)/32)-1 downto 0); -- modulus word(32-bit) address |
69,6 → 69,7
modulus_in : in std_logic_vector(31 downto 0); -- modulus word data in |
modulus_sel : in std_logic_vector(log2(depth)-1 downto 0); -- selects the modulus to use for multiplications |
-- multiplier side |
core_clk : in std_logic; |
modulus_out : out std_logic_vector(width-1 downto 0) |
); |
end modulus_ram_gen; |
96,14 → 97,15
depth => depth |
) |
port map( |
clk => clk, |
-- write port |
waddr => modulus_wraddr(total_aw-1 downto RAMselect_aw), |
we => we(i), |
din => modulus_in, |
clkA => bus_clk, |
waddrA => modulus_wraddr(total_aw-1 downto RAMselect_aw), |
weA => we(i), |
dinA => modulus_in, |
-- read port |
raddr => modulus_rdaddr, |
dout => modulus_out(((i+1)*32)-1 downto i*32) |
clkB => core_clk, |
raddrB => modulus_rdaddr, |
doutB => modulus_out(((i+1)*32)-1 downto i*32) |
); |
-- connect the w |
process (write_modulus, modulus_wraddr) |
/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
479,12 → 479,12
wea : in std_logic_vector(0 downto 0); |
addra : in std_logic_vector(5 downto 0); |
dina : in std_logic_vector(31 downto 0); |
douta : out std_logic_vector(511 downto 0); |
douta : out std_logic_vector(31 downto 0); |
clkb : in std_logic; |
web : in std_logic_vector(0 downto 0); |
addrb : in std_logic_vector(5 downto 0); |
addrb : in std_logic_vector(1 downto 0); |
dinb : in std_logic_vector(511 downto 0); |
doutb : out std_logic_vector(31 downto 0) |
doutb : out std_logic_vector(511 downto 0) |
); |
end component operand_dp; |
|
510,16 → 510,17
-- |
component fifo_primitive is |
port ( |
clk : in std_logic; |
din : in std_logic_vector (31 downto 0); |
dout : out std_logic_vector (31 downto 0); |
empty : out std_logic; |
full : out std_logic; |
push : in std_logic; |
pop : in std_logic; |
reset : in std_logic; |
nopop : out std_logic; |
nopush : out std_logic |
pop_clk : in std_logic; |
push_clk : in std_logic; |
din : in std_logic_vector (31 downto 0); |
dout : out std_logic_vector (31 downto 0); |
empty : out std_logic; |
full : out std_logic; |
push : in std_logic; |
pop : in std_logic; |
reset : in std_logic; |
nopop : out std_logic; |
nopush : out std_logic |
); |
end component fifo_primitive; |
|
532,9 → 533,9
component operand_ram is |
port( |
-- global ports |
clk : in std_logic; |
collision : out std_logic; |
-- bus side connections (32-bit serial) |
bus_clk : in std_logic; |
operand_addr : in std_logic_vector(5 downto 0); |
operand_in : in std_logic_vector(31 downto 0); |
operand_in_sel : in std_logic_vector(1 downto 0); |
541,6 → 542,7
result_out : out std_logic_vector(31 downto 0); |
write_operand : in std_logic; |
-- multiplier side connections (1536 bit parallel) |
core_clk : in std_logic; |
result_dest_op : in std_logic_vector(1 downto 0); |
operand_out : out std_logic_vector(1535 downto 0); |
operand_out_sel : in std_logic_vector(1 downto 0); -- controlled by bus side |
578,14 → 580,15
depth : integer := 2 |
); |
port ( |
clk : in std_logic; |
-- write port |
waddr : in std_logic_vector(log2(depth)-1 downto 0); |
we : in std_logic; |
din : in std_logic_vector(31 downto 0); |
-- read port |
raddr : in std_logic_vector(log2(depth)-1 downto 0); |
dout : out std_logic_vector(31 downto 0) |
-- write port A |
clkA : in std_logic; |
waddrA : in std_logic_vector(log2(depth)-1 downto 0); |
weA : in std_logic; |
dinA : in std_logic_vector(31 downto 0); |
-- read port B |
clkB : in std_logic; |
raddrB : in std_logic_vector(log2(depth)-1 downto 0); |
doutB : out std_logic_vector(31 downto 0) |
); |
end component dpram_generic; |
|
651,8 → 654,8
depth : integer := 2 -- nr of moduluses |
); |
port( |
clk : in std_logic; |
-- bus side |
bus_clk : in std_logic; |
write_modulus : in std_logic; -- write enable |
modulus_in_sel : in std_logic_vector(log2(depth)-1 downto 0); -- modulus operand to write to |
modulus_addr : in std_logic_vector(log2((width)/32)-1 downto 0); -- modulus word(32-bit) address |
659,6 → 662,7
modulus_in : in std_logic_vector(31 downto 0); -- modulus word data in |
modulus_sel : in std_logic_vector(log2(depth)-1 downto 0); -- selects the modulus to use for multiplications |
-- multiplier side |
core_clk : in std_logic; |
modulus_out : out std_logic_vector(width-1 downto 0) |
); |
end component modulus_ram_gen; |
676,9 → 680,9
); |
port( |
-- global ports |
clk : in std_logic; |
collision : out std_logic; -- 1 if simultaneous write on RAM |
-- bus side connections (32-bit serial) |
bus_clk : in std_logic; |
write_operand : in std_logic; -- write_enable |
operand_in_sel : in std_logic_vector(log2(depth)-1 downto 0); -- operand to write to |
operand_addr : in std_logic_vector(log2(width/32)-1 downto 0); -- address of operand word to write |
686,6 → 690,7
result_out : out std_logic_vector(31 downto 0); -- operand out, reading is always result operand |
operand_out_sel : in std_logic_vector(log2(depth)-1 downto 0); -- operand to give to multiplier |
-- multiplier side connections (width-bit parallel) |
core_clk : in std_logic; |
result_dest_op : in std_logic_vector(log2(depth)-1 downto 0); -- operand select for result |
operand_out : out std_logic_vector(width-1 downto 0); -- operand out to multiplier |
write_result : in std_logic; -- write enable for multiplier side |
706,20 → 711,21
-- asymmetric ram. |
-- |
component dpram_asym is |
generic( |
generic ( |
rddepth : integer := 4; -- nr of 32-bit words |
wrwidth : integer := 2; -- write width, must be smaller than or equal to 32 |
device : string := "xilinx" -- device template to use |
); |
port( |
clk : in std_logic; |
port ( |
-- write port |
waddr : in std_logic_vector(log2((rddepth*32)/wrwidth)-1 downto 0); |
we : in std_logic; |
din : in std_logic_vector(wrwidth-1 downto 0); |
clkA : in std_logic; |
waddrA : in std_logic_vector(log2((rddepth*32)/wrwidth)-1 downto 0); |
weA : in std_logic; |
dinA : in std_logic_vector(wrwidth-1 downto 0); |
-- read port |
raddr : in std_logic_vector(log2(rddepth)-1 downto 0); |
dout : out std_logic_vector(31 downto 0) |
clkB : in std_logic; |
raddrB : in std_logic_vector(log2(rddepth)-1 downto 0); |
doutB : out std_logic_vector(31 downto 0) |
); |
end component dpram_asym; |
|
731,20 → 737,21
-- port. |
-- |
component dpramblock_asym is |
generic( |
generic ( |
width : integer := 256; -- read width |
depth : integer := 2; -- nr of (width)-bit words |
device : string := "xilinx" |
); |
port( |
clk : in std_logic; |
-- write port |
waddr : in std_logic_vector(log2((width*depth)/32)-1 downto 0); |
we : in std_logic; |
din : in std_logic_vector(31 downto 0); |
-- read port |
raddr : in std_logic_vector(log2(depth)-1 downto 0); |
dout : out std_logic_vector(width-1 downto 0) |
port ( |
-- write port A |
clkA : in std_logic; |
waddrA : in std_logic_vector(log2((width*depth)/32)-1 downto 0); |
weA : in std_logic; |
dinA : in std_logic_vector(31 downto 0); |
-- read port B |
clkB : in std_logic; |
raddrB : in std_logic_vector(log2(depth)-1 downto 0); |
doutB : out std_logic_vector(width-1 downto 0) |
); |
end component dpramblock_asym; |
|
757,19 → 764,20
-- altera for asymmetric ram. |
-- |
component tdpram_asym is |
generic( |
generic ( |
depthB : integer := 4; -- nr of 32-bit words |
widthA : integer := 2; -- port A width, must be smaller than or equal to 32 |
device : string := "xilinx" |
); |
port( |
clk : in std_logic; |
port ( |
-- port A (widthA)-bit |
clkA : in std_logic; |
addrA : in std_logic_vector(log2((depthB*32)/widthA)-1 downto 0); |
weA : in std_logic; |
dinA : in std_logic_vector(widthA-1 downto 0); |
doutA : out std_logic_vector(widthA-1 downto 0); |
-- port B 32-bit |
clkB : in std_logic; |
addrB : in std_logic_vector(log2(depthB)-1 downto 0); |
weB : in std_logic; |
dinB : in std_logic_vector(31 downto 0); |
790,14 → 798,15
width : integer := 512; -- width of portB |
device : string := "xilinx" |
); |
port ( |
clk : in std_logic; |
port ( |
-- port A 32-bit |
clkA : in std_logic; |
addrA : in std_logic_vector(log2((width*depth)/32)-1 downto 0); |
weA : in std_logic; |
dinA : in std_logic_vector(31 downto 0); |
doutA : out std_logic_vector(31 downto 0); |
-- port B (width)-bit |
clkB : in std_logic; |
addrB : in std_logic_vector(log2(depth)-1 downto 0); |
weB : in std_logic; |
dinB : in std_logic_vector(width-1 downto 0); |
822,8 → 831,8
device : string := "xilinx" |
); |
port( |
clk : in std_logic; |
-- bus side |
bus_clk : in std_logic; |
write_modulus : in std_logic; -- write enable |
modulus_in_sel : in std_logic_vector(log2(depth)-1 downto 0); -- modulus operand to write to |
modulus_addr : in std_logic_vector(log2((width)/32)-1 downto 0); -- modulus word(32-bit) address |
830,6 → 839,7
modulus_in : in std_logic_vector(31 downto 0); -- modulus word data in |
modulus_sel : in std_logic_vector(log2(depth)-1 downto 0); -- selects the modulus to use for multiplications |
-- multiplier side |
core_clk : in std_logic; |
modulus_out : out std_logic_vector(width-1 downto 0) |
); |
end component modulus_ram_asym; |
852,9 → 862,9
); |
port( |
-- global ports |
clk : in std_logic; |
collision : out std_logic; -- 1 if simultaneous write on RAM |
-- bus side connections (32-bit serial) |
bus_clk : in std_logic; |
write_operand : in std_logic; -- write_enable |
operand_in_sel : in std_logic_vector(log2(depth)-1 downto 0); -- operand to write to |
operand_addr : in std_logic_vector(log2(width/32)-1 downto 0); -- address of operand word to write |
862,6 → 872,7
result_out : out std_logic_vector(31 downto 0); -- operand out, reading is always result operand |
operand_out_sel : in std_logic_vector(log2(depth)-1 downto 0); -- operand to give to multiplier |
-- multiplier side connections (width-bit parallel) |
core_clk : in std_logic; |
result_dest_op : in std_logic_vector(log2(depth)-1 downto 0); -- operand select for result |
operand_out : out std_logic_vector(width-1 downto 0); -- operand out to multiplier |
write_result : in std_logic; -- write enable for multiplier side |
893,14 → 904,14
device : string := "altera" -- xilinx, altera are valid options |
); |
port( |
-- system clock |
clk : in std_logic; |
-- data interface (plb side) |
bus_clk : in std_logic; |
data_in : in std_logic_vector(31 downto 0); |
data_out : out std_logic_vector(31 downto 0); |
rw_address : in std_logic_vector(8 downto 0); |
write_enable : in std_logic; |
-- operand interface (multiplier side) |
core_clk : in std_logic; |
op_sel : in std_logic_vector(log2(nr_op)-1 downto 0); |
xy_out : out std_logic_vector((width-1) downto 0); |
m : out std_logic_vector((width-1) downto 0); |
914,7 → 925,39
end component operand_mem; |
|
|
---------------------- CLOCK DOMAIN CROSSING ---------------------- |
|
-------------------------------------------------------------------- |
-- pulse_cdc |
-------------------------------------------------------------------- |
-- transfers a pulse (1clk wide) from clock domain A to clock domain B |
-- by using a toggling signal. This design avoids metastable states |
-- |
component pulse_cdc is |
port ( |
reset : in std_logic; |
clkA : in std_logic; |
pulseA : in std_logic; |
clkB : in std_logic; |
pulseB : out std_logic |
); |
end component pulse_cdc; |
|
-------------------------------------------------------------------- |
-- clk_sync |
-------------------------------------------------------------------- |
-- transfers a signal from clock domain A to clock domain B. |
-- This design avoids metastable states |
-- |
component clk_sync is |
port ( |
sigA : in std_logic; |
clkB : in std_logic; |
sigB : out std_logic |
); |
end component clk_sync; |
|
|
---------------------------- TOP LEVEL ----------------------------- |
|
-------------------------------------------------------------------- |
930,14 → 973,15
C_NR_STAGES_TOTAL : integer := 96; |
C_NR_STAGES_LOW : integer := 32; |
C_SPLIT_PIPELINE : boolean := true; |
C_FIFO_DEPTH : integer := 32; |
C_MEM_STYLE : string := "generic"; -- xil_prim, generic, asym are valid options |
C_FIFO_AW : integer := 7; -- Address width for FIFO pointers |
C_MEM_STYLE : string := "asym"; -- xil_prim, generic, asym are valid options |
C_FPGA_MAN : string := "xilinx" -- xilinx, altera are valid options |
); |
port( |
clk : in std_logic; |
reset : in std_logic; |
core_clk : in std_logic; |
reset : in std_logic; |
-- operand memory interface (plb shared memory) |
bus_clk : in std_logic; |
write_enable : in std_logic; -- write data to operand ram |
data_in : in std_logic_vector (31 downto 0); -- operand ram data in |
rw_address : in std_logic_vector (8 downto 0); -- operand ram address bus |
957,7 → 1001,7
dest_op_single : in std_logic_vector (1 downto 0); -- result destination operand selection |
p_sel : in std_logic_vector (1 downto 0); -- pipeline part selection |
calc_time : out std_logic; |
modulus_sel : in std_logic -- selects which modulus to use for multiplications |
modulus_sel : in std_logic -- selects which modulus to use for multiplications |
); |
end component mod_sim_exp_core; |
|
/trunk/rtl/vhdl/core/clk_sync.vhd
0,0 → 1,70
---------------------------------------------------------------------- |
---- clk_sync ---- |
---- ---- |
---- This file is part of the ---- |
---- Modular Simultaneous Exponentiation Core project ---- |
---- http://www.opencores.org/cores/mod_sim_exp/ ---- |
---- ---- |
---- Description ---- |
---- synchronises signal A to clock B, avoiding metastable ---- |
---- states. ---- |
---- ---- |
---- Dependencies: none ---- |
---- ---- |
---- Authors: ---- |
---- - Geoffrey Ottoy, DraMCo research group ---- |
---- - Jonas De Craene, JonasDC@opencores.org ---- |
---- ---- |
---------------------------------------------------------------------- |
---- ---- |
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ---- |
---- ---- |
---- This source file may be used and distributed without ---- |
---- restriction provided that this copyright statement is not ---- |
---- removed from the file and that any derivative work contains ---- |
---- the original copyright notice and the associated disclaimer. ---- |
---- ---- |
---- This source file is free software; you can redistribute it ---- |
---- and/or modify it under the terms of the GNU Lesser General ---- |
---- Public License as published by the Free Software Foundation; ---- |
---- either version 2.1 of the License, or (at your option) any ---- |
---- later version. ---- |
---- ---- |
---- This source is distributed in the hope that it will be ---- |
---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- |
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- |
---- PURPOSE. See the GNU Lesser General Public License for more ---- |
---- details. ---- |
---- ---- |
---- You should have received a copy of the GNU Lesser General ---- |
---- Public License along with this source; if not, download it ---- |
---- from http://www.opencores.org/lgpl.shtml ---- |
---- ---- |
---------------------------------------------------------------------- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_unsigned.all; |
|
entity clk_sync is |
port ( |
sigA : in std_logic; |
clkB : in std_logic; |
sigB : out std_logic |
); |
end clk_sync; |
|
|
architecture arch of clk_sync is |
signal sigMeta : std_logic; -- signal where metastable states are possible |
begin |
|
sync : process (clkB) |
begin |
if rising_edge(clkB) then |
sigMeta <= sigA; |
sigB <= sigMeta; |
end if; |
end process; |
|
end arch; |
/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
65,14 → 65,15
C_NR_STAGES_TOTAL : integer := 96; |
C_NR_STAGES_LOW : integer := 32; |
C_SPLIT_PIPELINE : boolean := true; |
C_FIFO_DEPTH : integer := 32; |
C_FIFO_AW : integer := 7; -- Address width for FIFO pointers |
C_MEM_STYLE : string := "asym"; -- xil_prim, generic, asym are valid options |
C_FPGA_MAN : string := "xilinx" -- xilinx, altera are valid options |
); |
port( |
clk : in std_logic; |
reset : in std_logic; |
core_clk : in std_logic; |
reset : in std_logic; |
-- operand memory interface (plb shared memory) |
bus_clk : in std_logic; |
write_enable : in std_logic; -- write data to operand ram |
data_in : in std_logic_vector (31 downto 0); -- operand ram data in |
rw_address : in std_logic_vector (8 downto 0); -- operand ram address bus |
115,6 → 116,10
signal load_x : std_logic; |
signal load_result : std_logic; |
signal modulus_sel_i : std_logic_vector(0 downto 0); |
signal core_ready : std_logic; |
signal core_calc_time : std_logic; |
signal core_collision : std_logic; |
signal core_start : std_logic; |
|
-- fifo signals |
signal fifo_empty : std_logic; |
127,26 → 132,6
report "C_MEM_STYLE incorrect!, it must be one of these: xil_prim, generic or asym" severity failure; |
assert (C_FPGA_MAN="xilinx" or C_FPGA_MAN="altera") |
report "C_FPGA_MAN incorrect!, it must be one of these: xilinx or altera" severity failure; |
|
-- The actual multiplier |
the_multiplier : mont_multiplier |
generic map( |
n => C_NR_BITS_TOTAL, |
t => C_NR_STAGES_TOTAL, |
tl => C_NR_STAGES_LOW, |
split => C_SPLIT_PIPELINE |
) |
port map( |
core_clk => clk, |
xy => xy, |
m => m, |
r => r, |
start => start_mult, |
reset => reset, |
p_sel => p_sel, |
load_x => load_x, |
ready => mult_ready |
); |
|
-- Block ram memory for storing the operands and the modulus |
the_memory : operand_mem |
158,6 → 143,7
device => C_FPGA_MAN |
) |
port map( |
bus_clk => bus_clk, |
data_in => data_in, |
data_out => data_out, |
rw_address => rw_address, |
165,11 → 151,11
op_sel => op_sel, |
xy_out => xy, |
m => m, |
core_clk => core_clk, |
result_in => r, |
load_result => load_result, |
result_dest_op => result_dest_op, |
collision => collision, |
clk => clk, |
collision => core_collision, |
modulus_sel => modulus_sel_i |
); |
|
180,7 → 166,8
xil_prim_fifo : if C_MEM_STYLE="xil_prim" generate |
the_exponent_fifo : fifo_primitive |
port map( |
clk => clk, |
push_clk => bus_clk, |
pop_clk => core_clk, |
din => fifo_din, |
dout => fifo_dout, |
empty => fifo_empty, |
192,31 → 179,53
nopush => fifo_nopush |
); |
end generate; |
gen_fifo : if (C_MEM_STYLE="generic") or (C_MEM_STYLE="asym") generate |
the_exponent_fifo : fifo_generic |
gen_fifo : if (C_MEM_STYLE = "generic") or (C_MEM_STYLE = "asym") generate |
the_exponent_fifo : entity mod_sim_exp.generic_fifo_dc |
generic map( |
depth => C_FIFO_DEPTH |
dw => 32, |
aw => C_FIFO_AW |
) |
port map( |
clk => clk, |
wr_clk => bus_clk, |
rd_clk => core_clk, |
din => fifo_din, |
dout => fifo_dout, |
empty => fifo_empty, |
full => fifo_full, |
push => fifo_push, |
pop => fifo_pop, |
reset => reset, |
we => fifo_push, |
re => fifo_pop, |
clr => reset, |
nopop => fifo_nopop, |
nopush => fifo_nopush |
); |
end generate; |
|
-- The actual multiplier |
the_multiplier : mont_multiplier |
generic map( |
n => C_NR_BITS_TOTAL, |
t => C_NR_STAGES_TOTAL, |
tl => C_NR_STAGES_LOW, |
split => C_SPLIT_PIPELINE |
) |
port map( |
core_clk => core_clk, |
xy => xy, |
m => m, |
r => r, |
start => start_mult, |
reset => reset, -- asynchronious reset |
p_sel => p_sel, |
load_x => load_x, |
ready => mult_ready |
); |
|
-- The control logic for the core |
the_control_unit : mont_ctrl |
port map( |
clk => clk, |
reset => reset, |
start => start, |
clk => core_clk, |
reset => reset, -- asynchronious reset |
start => core_start, |
x_sel_single => x_sel_single, |
y_sel_single => y_sel_single, |
run_auto => exp_m, |
223,8 → 232,8
op_buffer_empty => fifo_empty, |
op_sel_buffer => fifo_dout, |
read_buffer => fifo_pop, |
done => ready, |
calc_time => calc_time, |
done => core_ready, |
calc_time => core_calc_time, |
op_sel => op_sel, |
load_x => load_x, |
load_result => load_result, |
231,5 → 240,41
start_multiplier => start_mult, |
multiplier_ready => mult_ready |
); |
|
-- go from bus clock domain to core clock domain |
start_pulse : pulse_cdc |
port map( |
reset => reset, |
clkA => bus_clk, |
pulseA => start, |
clkB => core_clk, |
pulseB => core_start |
); |
|
-- go from core clock domain to bus clock domain |
ready_pulse : pulse_cdc |
port map( |
reset => reset, |
clkA => core_clk, |
pulseA => core_ready, |
clkB => bus_clk, |
pulseB => ready |
); |
|
sync_to_bus_clk : clk_sync |
port map( |
sigA => core_calc_time, |
clkB => bus_clk, |
sigB => calc_time |
); |
|
collision_pulse : pulse_cdc |
port map( |
reset => reset, |
clkA => core_clk, |
pulseA => core_collision, |
clkB => bus_clk, |
pulseB => collision |
); |
|
end Structural; |
/trunk/rtl/vhdl/core/operand_dp.vhd
1,75 → 1,50
---------------------------------------------------------------------- |
---- operand_dp ---- |
---- ---- |
---- This file is part of the ---- |
---- Modular Simultaneous Exponentiation Core project ---- |
---- http://www.opencores.org/cores/mod_sim_exp/ ---- |
---- ---- |
---- Description ---- |
---- 4 x 512 bit dual port ram for the operands ---- |
---- 32 bit read and write for bus side and 512 bit read and ---- |
---- write for multiplier side ---- |
---- ---- |
---- Dependencies: none ---- |
---- ---- |
---- Authors: ---- |
---- - Geoffrey Ottoy, DraMCo research group ---- |
---- - Jonas De Craene, JonasDC@opencores.org ---- |
---- ---- |
---------------------------------------------------------------------- |
---- ---- |
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ---- |
---- ---- |
---- This source file may be used and distributed without ---- |
---- restriction provided that this copyright statement is not ---- |
---- removed from the file and that any derivative work contains ---- |
---- the original copyright notice and the associated disclaimer. ---- |
---- ---- |
---- This source file is free software; you can redistribute it ---- |
---- and/or modify it under the terms of the GNU Lesser General ---- |
---- Public License as published by the Free Software Foundation; ---- |
---- either version 2.1 of the License, or (at your option) any ---- |
---- later version. ---- |
---- ---- |
---- This source is distributed in the hope that it will be ---- |
---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- |
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- |
---- PURPOSE. See the GNU Lesser General Public License for more ---- |
---- details. ---- |
---- ---- |
---- You should have received a copy of the GNU Lesser General ---- |
---- Public License along with this source; if not, download it ---- |
---- from http://www.opencores.org/lgpl.shtml ---- |
---- ---- |
---------------------------------------------------------------------- |
---------------------------------------------------------------------- |
-- This file is owned and controlled by Xilinx and must be used -- |
-- solely for design, simulation, implementation and creation of -- |
-- design files limited to Xilinx devices or technologies. Use -- |
-- with non-Xilinx devices or technologies is expressly prohibited -- |
-- and immediately terminates your license. -- |
-- -- |
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- |
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- |
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- |
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- |
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- |
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- |
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- |
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- |
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- |
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- |
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- |
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- |
-- FOR A PARTICULAR PURPOSE. -- |
-- -- |
-- Xilinx products are not intended for use in life support -- |
-- appliances, devices, or systems. Use in such applications are -- |
-- expressly prohibited. -- |
-- -- |
-- (c) Copyright 1995-2009 Xilinx, Inc. -- |
-- All rights reserved. -- |
---------------------------------------------------------------------- |
-------------------------------------------------------------------------------- |
-- (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. -- |
-- -- |
-- This file contains confidential and proprietary information -- |
-- of Xilinx, Inc. and is protected under U.S. and -- |
-- international copyright and other intellectual property -- |
-- laws. -- |
-- -- |
-- DISCLAIMER -- |
-- This disclaimer is not a license and does not grant any -- |
-- rights to the materials distributed herewith. Except as -- |
-- otherwise provided in a valid license issued to you by -- |
-- Xilinx, and to the maximum extent permitted by applicable -- |
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- |
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- |
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- |
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- |
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- |
-- (2) Xilinx shall not be liable (whether in contract or tort, -- |
-- including negligence, or under any other theory of -- |
-- liability) for any loss or damage of any kind or nature -- |
-- related to, arising under or in connection with these -- |
-- materials, including for any direct, or any indirect, -- |
-- special, incidental, or consequential loss or damage -- |
-- (including loss of data, profits, goodwill, or any type of -- |
-- loss or damage suffered as a result of any action brought -- |
-- by a third party) even if such damage or loss was -- |
-- reasonably foreseeable or Xilinx had been advised of the -- |
-- possibility of the same. -- |
-- -- |
-- CRITICAL APPLICATIONS -- |
-- Xilinx products are not designed or intended to be fail- -- |
-- safe, or for use in any application requiring fail-safe -- |
-- performance, such as life-support or safety devices or -- |
-- systems, Class III medical devices, nuclear facilities, -- |
-- applications related to the deployment of airbags, or any -- |
-- other applications that could lead to death, personal -- |
-- injury, or severe property or environmental damage -- |
-- (individually and collectively, "Critical -- |
-- Applications"). Customer assumes the sole risk and -- |
-- liability of any use of Xilinx products in Critical -- |
-- Applications, subject only to applicable laws and -- |
-- regulations governing limitations on product liability. -- |
-- -- |
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- |
-- PART OF THIS FILE AT ALL TIMES. -- |
-------------------------------------------------------------------------------- |
-- You must compile the wrapper file operand_dp.vhd when simulating |
-- the core, operand_dp. When compiling the wrapper file, be sure to |
-- reference the XilinxCoreLib VHDL simulation library. For detailed |
79,46 → 54,40
-- below are supported by Xilinx, Mentor Graphics and Synplicity |
-- synthesis tools. Ensure they are correct for your synthesis tool(s). |
|
|
library ieee; |
use ieee.std_logic_1164.ALL; |
LIBRARY ieee; |
USE ieee.std_logic_1164.ALL; |
-- synthesis translate_off |
library XilinxCoreLib; |
Library XilinxCoreLib; |
-- synthesis translate_on |
ENTITY operand_dp IS |
port ( |
clka: in std_logic; |
wea: in std_logic_vector(0 downto 0); |
addra: in std_logic_vector(5 downto 0); |
dina: in std_logic_vector(31 downto 0); |
douta: out std_logic_vector(31 downto 0); |
clkb: in std_logic; |
web: in std_logic_vector(0 downto 0); |
addrb: in std_logic_vector(1 downto 0); |
dinb: in std_logic_vector(511 downto 0); |
doutb: out std_logic_vector(511 downto 0)); |
END operand_dp; |
|
|
entity operand_dp is |
port ( |
clka : in std_logic; |
wea : in std_logic_vector(0 downto 0); |
addra : in std_logic_vector(5 downto 0); |
dina : in std_logic_vector(31 downto 0); |
douta : out std_logic_vector(511 downto 0); |
clkb : in std_logic; |
web : in std_logic_vector(0 downto 0); |
addrb : in std_logic_vector(5 downto 0); |
dinb : in std_logic_vector(511 downto 0); |
doutb : out std_logic_vector(31 downto 0) |
); |
end operand_dp; |
|
|
architecture operand_dp_a of operand_dp is |
ARCHITECTURE operand_dp_a OF operand_dp IS |
-- synthesis translate_off |
component wrapped_operand_dp |
port ( |
clka : in std_logic; |
wea : in std_logic_vector(0 downto 0); |
addra : in std_logic_vector(5 downto 0); |
dina : in std_logic_vector(31 downto 0); |
douta : out std_logic_vector(511 downto 0); |
clkb : in std_logic; |
web : in std_logic_vector(0 downto 0); |
addrb : in std_logic_vector(5 downto 0); |
dinb : in std_logic_vector(511 downto 0); |
doutb : out std_logic_vector(31 downto 0) |
); |
end component; |
component wrapped_operand_dp |
port ( |
clka: in std_logic; |
wea: in std_logic_vector(0 downto 0); |
addra: in std_logic_vector(5 downto 0); |
dina: in std_logic_vector(31 downto 0); |
douta: out std_logic_vector(31 downto 0); |
clkb: in std_logic; |
web: in std_logic_vector(0 downto 0); |
addrb: in std_logic_vector(1 downto 0); |
dinb: in std_logic_vector(511 downto 0); |
doutb: out std_logic_vector(511 downto 0)); |
end component; |
|
-- Configuration specification |
for all : wrapped_operand_dp use entity XilinxCoreLib.blk_mem_gen_v3_3(behavioral) |
131,10 → 100,10
c_has_injecterr => 0, |
c_rst_type => "SYNC", |
c_prim_type => 1, |
c_read_width_b => 32, |
c_read_width_b => 512, |
c_initb_val => "0", |
c_family => "virtex6", |
c_read_width_a => 512, |
c_read_width_a => 32, |
c_disable_warn_bhv_coll => 0, |
c_write_mode_b => "WRITE_FIRST", |
c_init_file_name => "no_coe_file_loaded", |
152,7 → 121,7
c_inita_val => "0", |
c_has_mux_output_regs_a => 0, |
c_addra_width => 6, |
c_addrb_width => 6, |
c_addrb_width => 2, |
c_default_data => "0", |
c_use_ecc => 0, |
c_algorithm => 1, |
159,8 → 128,8
c_disable_warn_bhv_range => 0, |
c_write_width_b => 512, |
c_write_width_a => 32, |
c_read_depth_b => 64, |
c_read_depth_a => 4, |
c_read_depth_b => 4, |
c_read_depth_a => 64, |
c_byte_size => 9, |
c_sim_collision_check => "ALL", |
c_common_clk => 0, |
172,24 → 141,23
c_use_byte_wea => 0, |
c_rst_priority_b => "CE", |
c_rst_priority_a => "CE", |
c_use_default_data => 0 |
); |
c_use_default_data => 0); |
-- synthesis translate_on |
begin |
BEGIN |
-- synthesis translate_off |
U0 : wrapped_operand_dp |
port map ( |
clka => clka, |
wea => wea, |
addra => addra, |
dina => dina, |
douta => douta, |
clkb => clkb, |
web => web, |
addrb => addrb, |
dinb => dinb, |
doutb => doutb |
); |
U0 : wrapped_operand_dp |
port map ( |
clka => clka, |
wea => wea, |
addra => addra, |
dina => dina, |
douta => douta, |
clkb => clkb, |
web => web, |
addrb => addrb, |
dinb => dinb, |
doutb => doutb); |
-- synthesis translate_on |
|
end operand_dp_a; |
END operand_dp_a; |
|
/trunk/rtl/vhdl/core/operand_mem.vhd
72,17 → 72,17
nr_op : integer := 4; -- nr of operand storages, has to be greater than nr_m |
nr_m : integer := 2; -- nr of modulus storages |
mem_style : string := "asym"; -- xil_prim, generic, asym are valid options |
device : string := "altera" -- xilinx, altera are valid options |
device : string := "xilinx" -- xilinx, altera are valid options |
); |
port( |
-- system clock |
clk : in std_logic; |
-- data interface (plb side) |
bus_clk : in std_logic; |
data_in : in std_logic_vector(31 downto 0); |
data_out : out std_logic_vector(31 downto 0); |
rw_address : in std_logic_vector(8 downto 0); |
write_enable : in std_logic; |
-- operand interface (multiplier side) |
core_clk : in std_logic; |
op_sel : in std_logic_vector(log2(nr_op)-1 downto 0); |
xy_out : out std_logic_vector((width-1) downto 0); |
m : out std_logic_vector((width-1) downto 0); |
132,7 → 132,8
-- xy operand storage |
xy_ram_xil : operand_ram |
port map( |
clk => clk, |
bus_clk => bus_clk, |
core_clk => core_clk, |
collision => collision, |
operand_addr => xy_addr_i, |
operand_in => xy_data_i, |
149,7 → 150,7
-- modulus storage |
m_ram_xil : modulus_ram |
port map( |
clk => clk, |
clk => bus_clk, |
modulus_addr => m_addr_i, |
write_modulus => load_m, |
modulus_in => m_data_i, |
165,8 → 166,8
depth => nr_op |
) |
port map( |
clk => clk, |
collision => collision, |
bus_clk => bus_clk, |
operand_addr => xy_addr_i, |
operand_in => xy_data_i, |
operand_in_sel => operand_in_sel_i, |
175,6 → 176,7
operand_out => xy_out, |
operand_out_sel => op_sel, |
result_dest_op => result_dest_op, |
core_clk => core_clk, |
write_result => load_result, |
result_in => result_in |
); |
186,11 → 188,12
depth => nr_m |
) |
port map( |
clk => clk, |
bus_clk => bus_clk, |
modulus_in_sel => modulus_in_sel_i, |
modulus_addr => m_addr_i, |
write_modulus => load_m, |
modulus_in => m_data_i, |
core_clk => core_clk, |
modulus_out => m, |
modulus_sel => modulus_sel |
); |
205,8 → 208,8
device => device |
) |
port map( |
clk => clk, |
collision => collision, |
bus_clk => bus_clk, |
operand_addr => xy_addr_i, |
operand_in => xy_data_i, |
operand_in_sel => operand_in_sel_i, |
215,6 → 218,7
operand_out => xy_out, |
operand_out_sel => op_sel, |
result_dest_op => result_dest_op, |
core_clk => core_clk, |
write_result => load_result, |
result_in => result_in |
); |
227,11 → 231,12
device => device |
) |
port map( |
clk => clk, |
bus_clk => bus_clk, |
modulus_in_sel => modulus_in_sel_i, |
modulus_addr => m_addr_i, |
write_modulus => load_m, |
modulus_in => m_data_i, |
core_clk => core_clk, |
modulus_out => m, |
modulus_sel => modulus_sel |
); |
/trunk/rtl/vhdl/core/operand_ram.vhd
55,9 → 55,9
entity operand_ram is |
port( -- write_operand_ack voorzien? |
-- global ports |
clk : in std_logic; |
collision : out std_logic; |
-- bus side connections (32-bit serial) |
bus_clk : in std_logic; |
operand_addr : in std_logic_vector(5 downto 0); |
operand_in : in std_logic_vector(31 downto 0); |
operand_in_sel : in std_logic_vector(1 downto 0); |
64,6 → 64,7
result_out : out std_logic_vector(31 downto 0); |
write_operand : in std_logic; |
-- multiplier side connections (1536 bit parallel) |
core_clk : in std_logic; |
result_dest_op : in std_logic_vector(1 downto 0); |
operand_out : out std_logic_vector(1535 downto 0); |
operand_out_sel : in std_logic_vector(1 downto 0); -- controlled by bus side |
81,11 → 82,11
signal write_operand_i : std_logic; |
|
-- port b signals |
signal addrb : std_logic_vector(5 downto 0); |
signal addrb : std_logic_vector(1 downto 0); |
signal web : std_logic_vector(0 downto 0); |
signal doutb0 : std_logic_vector(31 downto 0); |
signal doutb1 : std_logic_vector(31 downto 0); |
signal doutb2 : std_logic_vector(31 downto 0); |
signal douta0 : std_logic_vector(31 downto 0); |
signal douta1 : std_logic_vector(31 downto 0); |
signal douta2 : std_logic_vector(31 downto 0); |
|
begin |
|
99,70 → 100,70
-- the dual port ram has a depth of 4 (each layer contains an operand) |
-- result is always stored in position 3 |
-- doutb is always result |
with write_operand_i select |
addra <= operand_in_sel & operand_addr(3 downto 0) when '1', |
operand_out_sel & "0000" when others; |
with write_result select |
addrb <= result_dest_op when '1', |
operand_out_sel when others; |
|
|
|
with operand_addr(5 downto 4) select |
part_enable <= "0001" when "00", |
"0010" when "01", |
"0100" when "10", |
"1000" when others; |
|
with write_operand_i select |
wea <= part_enable when '1', |
"0000" when others; |
|
with write_operand select |
wea <= part_enable when '1', |
"0000" when others; |
|
addra <= operand_in_sel & operand_addr(3 downto 0); |
|
-- we can only read back from the result (stored in result_dest_op) |
addrb <= result_dest_op & operand_addr(3 downto 0); |
|
|
with operand_addr(5 downto 4) select |
result_out <= doutb0 when "00", |
doutb1 when "01", |
doutb2 when others; |
result_out <= douta0 when "00", |
douta1 when "01", |
douta2 when others; |
|
-- 3 instances of a dual port ram to store the parts of the operand |
op_0 : operand_dp |
port map ( |
clka => clk, |
clka => bus_clk, |
wea => wea(0 downto 0), |
addra => addra, |
dina => operand_in, |
douta => operand_out(511 downto 0), |
clkb => clk, |
douta => douta0, |
clkb => core_clk, |
web => web, |
addrb => addrb, |
dinb => result_in(511 downto 0), |
doutb => doutb0 |
doutb => operand_out(511 downto 0) |
); |
|
op_1 : operand_dp |
port map ( |
clka => clk, |
clka => bus_clk, |
wea => wea(1 downto 1), |
addra => addra, |
dina => operand_in, |
douta => operand_out(1023 downto 512), |
clkb => clk, |
douta => douta1, |
clkb => core_clk, |
web => web, |
addrb => addrb, |
dinb => result_in(1023 downto 512), |
doutb => doutb1 |
doutb => operand_out(1023 downto 512) |
); |
|
op_2 : operand_dp |
port map ( |
clka => clk, |
clka => bus_clk, |
wea => wea(2 downto 2), |
addra => addra, |
dina => operand_in, |
douta => operand_out(1535 downto 1024), |
clkb => clk, |
douta => douta2, |
clkb => core_clk, |
web => web, |
addrb => addrb, |
dinb => result_in(1535 downto 1024), |
doutb => doutb2 |
doutb => operand_out(1535 downto 1024) |
); |
|
end Behavioral; |
/trunk/sim/Makefile
1,7 → 1,9
#VCOM = /usr/local/bin/vcom |
VCOMOPS = -explicit -check_synthesis -2002 -quiet |
VLOGOPS = -vopt -nocovercells |
#MAKEFLAGS = --silent |
HDL_DIR = ../rtl/vhdl/ |
VER_DIR = ../rtl/verilog/ |
|
## |
# hdl files |
44,7 → 46,11
$(HDL_DIR)core/sys_first_cell_logic.vhd \ |
$(HDL_DIR)core/sys_pipeline.vhd \ |
$(HDL_DIR)core/mont_multiplier.vhd \ |
$(HDL_DIR)core/pulse_cdc.vhd \ |
$(HDL_DIR)core/clk_sync.vhd \ |
|
VER_SRC =$(VER_DIR)generic_fifo_dc.v \ |
$(VER_DIR)generic_fifo_dc_gray.v |
|
## |
# Testbench HDL files |
51,7 → 57,8
## |
TB_SRC_DIR = ../bench/vhdl/ |
TB_SRC = $(TB_SRC_DIR)mod_sim_exp_core_tb.vhd \ |
$(TB_SRC_DIR)msec_axi_tb.vhd |
$(TB_SRC_DIR)msec_axi_tb.vhd \ |
$(TB_SRC_DIR)axi_tb.vhd |
|
## |
# Interface HDL files |
77,6 → 84,7
#echo -- |
#echo building Modular Exponentiation Core |
#echo -- |
vlog $(VLOGOPS) -work mod_sim_exp $(VER_SRC) |
vcom $(VCOMOPS) -work mod_sim_exp $(CORE_SRC) |
#echo Done! |
|
/trunk/syn/xilinx/log/fifo/generic_fifo_dc_aw5_summary.html
0,0 → 1,112
<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD> |
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'> |
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'> |
<TD ALIGN=CENTER COLSPAN='4'><B>mod_sim_exp_core Project Status (07/03/2013 - 16:14:37)</B></TD></TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD> |
<TD>msec.xise</TD> |
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD> |
<TD> No Errors </TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD> |
<TD>generic_fifo_dc</TD> |
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD> |
<TD>Synthesized</TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD> |
<TD>xc6vlx240t-1ff1156</TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD> |
<TD> |
No Errors</TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.4</TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD> |
<TD ALIGN=LEFT>No Warnings</TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD> |
<TD>Balanced</TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD> |
<TD> |
</TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD> |
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD> |
<TD> </TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD> |
<TD> |
<A HREF_DISABLED='/home/dinghe/Thesis/mod_sim_exp/trunk/iseproj/msec/generic_fifo_dc_envsettings.html'> |
System Settings</A> |
</TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD> |
<TD> </TD> |
</TR> |
</TABLE> |
|
|
|
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Device Utilization Summary (estimated values)</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary(estimatedvalues)"><B>[-]</B></a></TD></TR> |
<TR ALIGN=CENTER BGCOLOR='#FFFF99'> |
<TD ALIGN=LEFT><B>Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD COLSPAN='2'><B>Utilization</B></TD></TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD> |
<TD ALIGN=RIGHT>46</TD> |
<TD ALIGN=RIGHT>301440</TD> |
<TD ALIGN=RIGHT COLSPAN='2'>0%</TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD> |
<TD ALIGN=RIGHT>40</TD> |
<TD ALIGN=RIGHT>150720</TD> |
<TD ALIGN=RIGHT COLSPAN='2'>0%</TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of fully used LUT-FF pairs</TD> |
<TD ALIGN=RIGHT>38</TD> |
<TD ALIGN=RIGHT>48</TD> |
<TD ALIGN=RIGHT COLSPAN='2'>79%</TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded IOBs</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>600</TD> |
<TD ALIGN=RIGHT COLSPAN='2'>0%</TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Block RAM/FIFO</TD> |
<TD ALIGN=RIGHT>1</TD> |
<TD ALIGN=RIGHT>416</TD> |
<TD ALIGN=RIGHT COLSPAN='2'>0%</TD> |
</TR> |
</TABLE> |
|
|
|
|
|
|
|
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR> |
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD> |
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/dinghe/Thesis/mod_sim_exp/trunk/iseproj/msec/generic_fifo_dc.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Wed Jul 3 16:14:37 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='/home/dinghe/Thesis/mod_sim_exp/trunk/iseproj/msec/_xmsgs/xst.xmsgs?&DataKey=Info'>2 Infos (1 new)</A></TD></TR> |
<TR ALIGN=LEFT><TD>Translation Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD>Map Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
</TABLE> |
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR> |
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR> |
</TABLE> |
|
|
<br><center><b>Date Generated:</b> 07/03/2013 - 16:14:37</center> |
</BODY></HTML> |
/trunk/syn/xilinx/log/fifo/generic_fifo_dc_aw5_syr.html
0,0 → 1,112
<title>Synthesis Report</title><PRE><FONT FACE="Courier New", monotype><p align=left><b>Synthesis Report</b></p><b><center>Wed Jul 3 16:16:06 2013</center></b><br><hr><br>Release 14.4 - xst P.49d (lin64)<br>Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.<br>--> <br>Parameter TMPDIR set to xst/projnav.tmp<br><br><br>Total REAL time to Xst completion: 0.00 secs<br>Total CPU time to Xst completion: 0.05 secs<br> <br>--> <br>Parameter xsthdpdir set to xst<br><br><br>Total REAL time to Xst completion: 0.00 secs<br>Total CPU time to Xst completion: 0.05 secs<br> <br>--> <br>Reading design: generic_fifo_dc.prj<br><br>TABLE OF CONTENTS<br> 1) Synthesis Options Summary<br> 2) HDL Parsing<br> 3) HDL Elaboration<br> 4) HDL Synthesis<br> 4.1) HDL Synthesis Report<br> 5) Advanced HDL Synthesis<br> 5.1) Advanced HDL Synthesis Report<br> 6) Low Level Synthesis<br> 7) Partition Report<br> 8) Design Summary<br> 8.1) Primitive and Black Box Usage<br> 8.2) Device utilization summary<br> 8.3) Partition Resource Summary<br> 8.4) Timing Report<br> 8.4.1) Clock Information<br> 8.4.2) Asynchronous Control Signals Information<br> 8.4.3) Timing Summary<br> 8.4.4) Timing Details<br> 8.4.5) Cross Clock Domains Report<br><br><br>=========================================================================<br>* Synthesis Options Summary *<br>=========================================================================<br>---- Source Parameters<br>Input File Name : "generic_fifo_dc.prj"<br>Ignore Synthesis Constraint File : NO<br><br>---- Target Parameters<br>Output File Name : "generic_fifo_dc"<br>Output Format : NGC<br>Target Device : xc6vlx240t-1-ff1156<br><br>---- Source Options<br>Top Module Name : generic_fifo_dc<br>Automatic FSM Extraction : YES<br>FSM Encoding Algorithm : Auto<br>Safe Implementation : No<br>FSM Style : LUT<br>RAM Extraction : Yes<br>RAM Style : Auto<br>ROM Extraction : Yes<br>Shift Register Extraction : YES<br>ROM Style : Auto<br>Resource Sharing : YES<br>Asynchronous To Synchronous : NO<br>Shift Register Minimum Size : 2<br>Use DSP Block : Auto<br>Automatic Register Balancing : No<br><br>---- Target Options<br>LUT Combining : Auto<br>Reduce Control Sets : Auto<br>Add IO Buffers : NO<br>Global Maximum Fanout : 100000<br>Add Generic Clock Buffer(BUFG) : 32<br>Register Duplication : YES<br>Optimize Instantiated Primitives : NO<br>Use Clock Enable : Auto<br>Use Synchronous Set : Auto<br>Use Synchronous Reset : Auto<br>Pack IO Registers into IOBs : Auto<br>Equivalent register Removal : YES<br><br>---- General Options<br>Optimization Goal : Area<br>Optimization Effort : 2<br>Power Reduction : NO<br>Keep Hierarchy : No<br>Netlist Hierarchy : As_Optimized<br>RTL Output : Yes<br>Global Optimization : AllClockNets<br>Read Cores : YES<br>Write Timing Constraints : NO<br>Cross Clock Analysis : NO<br>Hierarchy Separator : /<br>Bus Delimiter : <><br>Case Specifier : Maintain<br>Slice Utilization Ratio : 100<br>BRAM Utilization Ratio : 100<br>DSP48 Utilization Ratio : 100<br>Auto BRAM Packing : NO<br>Slice Utilization Ratio Delta : 5<br><br>---- Other Options<br>Cores Search Directories : {"../../syn/xilinx/src" }<br><br>=========================================================================<br><br><br>=========================================================================<br>* HDL Parsing *<br>=========================================================================<br>Analyzing Verilog file "/home/dinghe/Thesis/mod_sim_exp/trunk/rtl/verilog/generic_fifo_dc.v" into library work<br>Parsing module <generic_fifo_dc>.<br>Parsing VHDL file "/home/dinghe/Thesis/mod_sim_exp/trunk/rtl/vhdl/core/std_functions.vhd" into library mod_sim_exp<br>Parsing package <std_functions>.<br>Parsing package body <std_functions>.<br>Parsing VHDL file "/home/dinghe/Thesis/mod_sim_exp/trunk/rtl/vhdl/ram/dpram_generic.vhd" into library mod_sim_exp<br>Parsing entity <dpram_generic>.<br>Parsing architecture <behavorial> of entity <dpram_generic>.<br><br>=========================================================================<br>* HDL Elaboration *<br>=========================================================================<br><br>Elaborating module <generic_fifo_dc>.<br>Going to vhdl side to elaborate module dpram_generic<br><br>Elaborating entity <dpram_generic> (architecture <behavorial>) with generics from library <mod_sim_exp>.<br>Back to verilog to continue elaboration<br><br>=========================================================================<br>* HDL Synthesis *<br>=========================================================================<br><br>Synthesizing Unit <generic_fifo_dc>.<br> Related source file is "/home/dinghe/Thesis/mod_sim_exp/trunk/rtl/verilog/generic_fifo_dc.v".<br> dw = 32<br> aw = 5<br> n = 32<br> max_size = 32<br> Found 6-bit register for signal <wp>.<br> Found 6-bit register for signal <rp>.<br> Found 6-bit register for signal <wp_s>.<br> Found 6-bit register for signal <rp_s>.<br> Found 1-bit register for signal <empty>.<br> Found 1-bit register for signal <full>.<br> Found 1-bit register for signal <re_r>.<br> Found 6-bit register for signal <diff_r1>.<br> Found 1-bit register for signal <empty_n>.<br> Found 1-bit register for signal <we_r>.<br> Found 6-bit register for signal <diff_r2>.<br> Found 1-bit register for signal <full_n>.<br> Found 2-bit register for signal <level>.<br> Found 1-bit register for signal <nopop>.<br> Found 1-bit register for signal <nopush>.<br> Found 32-bit register for signal <dout>.<br> Found 6-bit subtractor for signal <diff> created at line 254.<br> Found 6-bit adder for signal <wp_pl1> created at line 217.<br> Found 6-bit adder for signal <rp_pl1> created at line 224.<br> Found 6-bit comparator equal for signal <wp_s[5]_rp[5]_equal_19_o> created at line 243<br> Found 6-bit comparator equal for signal <wp_s[5]_rp_pl1[5]_equal_20_o> created at line 243<br> Found 5-bit comparator equal for signal <wp[4]_rp_s[4]_equal_22_o> created at line 246<br> Found 1-bit comparator not equal for signal <n0022> created at line 246<br> Found 5-bit comparator equal for signal <wp_pl1[4]_rp_s[4]_equal_24_o> created at line 247<br> Found 1-bit comparator not equal for signal <n0027> created at line 247<br> Found 6-bit comparator greater for signal <diff_r1[5]_PWR_1_o_LessThan_31_o> created at line 263<br> Found 6-bit comparator greater for signal <GND_1_o_diff_r2[5]_LessThan_37_o> created at line 272<br> Summary:<br> inferred 3 Adder/Subtractor(s).<br> inferred 78 D-type flip-flop(s).<br> inferred 8 Comparator(s).<br>Unit <generic_fifo_dc> synthesized.<br><br>Synthesizing Unit <dpram_generic>.<br> Related source file is "/home/dinghe/Thesis/mod_sim_exp/trunk/rtl/vhdl/ram/dpram_generic.vhd".<br> depth = 32<br> Set property "ram_style = block" for signal <RAM>.<br> Found 32x32-bit dual-port RAM <Mram_RAM> for signal <RAM>.<br> Found 32-bit register for signal <doutB>.<br> Summary:<br> inferred 1 RAM(s).<br> inferred 32 D-type flip-flop(s).<br>Unit <dpram_generic> synthesized.<br><br>=========================================================================<br>HDL Synthesis Report<br><br>Macro Statistics<br># RAMs : 1<br> 32x32-bit dual-port RAM : 1<br># Adders/Subtractors : 3<br> 6-bit adder : 2<br> 6-bit subtractor : 1<br># Registers : 17<br> 1-bit register : 8<br> 2-bit register : 1<br> 32-bit register : 2<br> 6-bit register : 6<br># Comparators : 8<br> 1-bit comparator not equal : 2<br> 5-bit comparator equal : 2<br> 6-bit comparator equal : 2<br> 6-bit comparator greater : 2<br><br>=========================================================================<br><br>=========================================================================<br>* Advanced HDL Synthesis *<br>=========================================================================<br><br><br>Synthesizing (advanced) Unit <generic_fifo_dc>.<br>The following registers are absorbed into counter <rp>: 1 register on signal <rp>.<br>The following registers are absorbed into counter <wp>: 1 register on signal <wp>.<br>INFO:Xst:3226 - The RAM <u0/Mram_RAM> will be implemented as a BLOCK RAM, absorbing the following register(s): <u0/doutB> <dout><br> -----------------------------------------------------------------------<br> | ram_type | Block | |<br> -----------------------------------------------------------------------<br> | Port A |<br> | aspect ratio | 32-word x 32-bit | |<br> | mode | write-first | |<br> | clkA | connected to signal <wr_clk> | rise |<br> | weA | connected to internal node | high |<br> | addrA | connected to signal <wp<4:0>> | |<br> | diA | connected to signal <din> | |<br> -----------------------------------------------------------------------<br> | optimization | area | |<br> -----------------------------------------------------------------------<br> | Port B |<br> | aspect ratio | 32-word x 32-bit | |<br> | mode | write-first | |<br> | clkB | connected to signal <rd_clk> | rise |<br> | addrB | connected to signal <rp<4:0>> | |<br> | doB | connected to signal <dout> | |<br> -----------------------------------------------------------------------<br> | optimization | area | |<br> -----------------------------------------------------------------------<br>Unit <generic_fifo_dc> synthesized (advanced).<br><br>=========================================================================<br>Advanced HDL Synthesis Report<br><br>Macro Statistics<br># RAMs : 1<br> 32x32-bit dual-port block RAM : 1<br># Adders/Subtractors : 3<br> 6-bit adder : 2<br> 6-bit subtractor : 1<br># Counters : 2<br> 6-bit up counter : 2<br># Registers : 34<br> Flip-Flops : 34<br># Comparators : 8<br> 1-bit comparator not equal : 2<br> 5-bit comparator equal : 2<br> 6-bit comparator equal : 2<br> 6-bit comparator greater : 2<br><br>=========================================================================<br><br>=========================================================================<br>* Low Level Synthesis *<br>=========================================================================<br><br>Optimizing unit <generic_fifo_dc> ...<br><br>Mapping all equations...<br>Building and optimizing final netlist ...<br>Found area constraint ratio of 100 (+ 5) on block generic_fifo_dc, actual ratio is 0.<br><br>Final Macro Processing ...<br><br>=========================================================================<br>Final Register Report<br><br>Macro Statistics<br># Registers : 46<br> Flip-Flops : 46<br><br>=========================================================================<br><br>=========================================================================<br>* Partition Report *<br>=========================================================================<br><br>Partition Implementation Status<br>-------------------------------<br><br> No Partitions were found in this design.<br><br>-------------------------------<br><br>=========================================================================<br>* Design Summary *<br>=========================================================================<br><br>Top Level Output File Name : generic_fifo_dc.ngc<br><br>Primitive and Black Box Usage:<br>------------------------------<br># BELS : 53<br># GND : 1<br># INV : 2<br># LUT2 : 14<br># LUT3 : 6<br># LUT4 : 2<br># LUT5 : 6<br># LUT6 : 10<br># MUXCY : 5<br># VCC : 1<br># XORCY : 6<br># FlipFlops/Latches : 46<br># FD : 34<br># FDRE : 12<br># RAMS : 1<br># RAMB18E1 : 1<br><br>Device utilization summary:<br>---------------------------<br><br>Selected Device : 6vlx240tff1156-1 <br><br><br>Slice Logic Utilization: <br> Number of Slice Registers: 46 out of 301440 0% <br> Number of Slice LUTs: 40 out of 150720 0% <br> Number used as Logic: 40 out of 150720 0% <br><br>Slice Logic Distribution: <br> Number of LUT Flip Flop pairs used: 48<br> Number with an unused Flip Flop: 2 out of 48 4% <br> Number with an unused LUT: 8 out of 48 16% <br> Number of fully used LUT-FF pairs: 38 out of 48 79% <br> Number of unique control sets: 4<br><br>IO Utilization: <br> Number of IOs: 77<br> Number of bonded IOBs: 0 out of 600 0% <br><br>Specific Feature Utilization:<br> Number of Block RAM/FIFO: 1 out of 416 0% <br> Number using Block RAM only: 1<br><br>---------------------------<br>Partition Resource Summary:<br>---------------------------<br><br> No Partitions were found in this design.<br><br>---------------------------<br><br><br>=========================================================================<br>Timing Report<br><br>NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.<br> FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT<br> GENERATED AFTER PLACE-and-ROUTE.<br><br>Clock Information:<br>------------------<br>-----------------------------------+------------------------+-------+<br>Clock Signal | Clock buffer(FF name) | Load |<br>-----------------------------------+------------------------+-------+<br>rd_clk | NONE(empty) | 23 |<br>wr_clk | NONE(full) | 25 |<br>-----------------------------------+------------------------+-------+<br>INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.<br><br>Asynchronous Control Signals Information:<br>----------------------------------------<br>-----------------------------------+------------------------+-------+<br>Control Signal | Buffer(FF name) | Load |<br>-----------------------------------+------------------------+-------+<br>we_full_AND_3_o(we_full_AND_3_o1:O)| NONE(u0/Mram_RAM) | 8 |<br>-----------------------------------+------------------------+-------+<br><br>Timing Summary:<br>---------------<br>Speed Grade: -1<br><br> Minimum period: 2.312ns (Maximum Frequency: 432.526MHz)<br> Minimum input arrival time before clock: 1.104ns<br> Maximum output required time after clock: 0.742ns<br> Maximum combinational path delay: No path found<br><br>Timing Details:<br>---------------<br>All values displayed in nanoseconds (ns)<br><br>=========================================================================<br>Timing constraint: Default period analysis for Clock 'rd_clk'<br> Clock period: 2.312ns (frequency: 432.526MHz)<br> Total number of paths / destination ports: 100 / 27<br>-------------------------------------------------------------------------<br>Delay: 2.312ns (Levels of Logic = 3)<br> Source: rp_4 (FF)<br> Destination: empty (FF)<br> Source Clock: rd_clk rising<br> Destination Clock: rd_clk rising<br><br> Data Path: rp_4 to empty<br> Gate Net<br> Cell:in->out fanout Delay Delay Logical Name (Net Name)<br> ---------------------------------------- ------------<br> FDRE:C->Q 6 0.375 0.808 rp_4 (rp_4)<br> LUT5:I0->O 2 0.068 0.497 Result<4>2 (Result<4>)<br> LUT6:I4->O 1 0.068 0.417 wp_s[5]_re_OR_6_o4_SW0 (N13)<br> LUT5:I4->O 1 0.068 0.000 wp_s[5]_re_OR_6_o5 (wp_s[5]_re_OR_6_o)<br> FD:D 0.011 empty<br> ----------------------------------------<br> Total 2.312ns (0.590ns logic, 1.722ns route)<br> (25.5% logic, 74.5% route)<br><br>=========================================================================<br>Timing constraint: Default period analysis for Clock 'wr_clk'<br> Clock period: 2.312ns (frequency: 432.526MHz)<br> Total number of paths / destination ports: 152 / 28<br>-------------------------------------------------------------------------<br>Delay: 2.312ns (Levels of Logic = 3)<br> Source: wp_4 (FF)<br> Destination: full (FF)<br> Source Clock: wr_clk rising<br> Destination Clock: wr_clk rising<br><br> Data Path: wp_4 to full<br> Gate Net<br> Cell:in->out fanout Delay Delay Logical Name (Net Name)<br> ---------------------------------------- ------------<br> FDRE:C->Q 6 0.375 0.808 wp_4 (wp_4)<br> LUT5:I0->O 2 0.068 0.497 Result<4>11 (Result<4>1)<br> LUT6:I4->O 1 0.068 0.417 wp[4]_we_OR_11_o4_SW0 (N11)<br> LUT5:I4->O 1 0.068 0.000 wp[4]_we_OR_11_o5 (wp[4]_we_OR_11_o)<br> FD:D 0.011 full<br> ----------------------------------------<br> Total 2.312ns (0.590ns logic, 1.722ns route)<br> (25.5% logic, 74.5% route)<br><br>=========================================================================<br>Timing constraint: Default OFFSET IN BEFORE for Clock 'rd_clk'<br> Total number of paths / destination ports: 34 / 33<br>-------------------------------------------------------------------------<br>Offset: 1.104ns (Levels of Logic = 2)<br> Source: re (PAD)<br> Destination: empty (FF)<br> Destination Clock: rd_clk rising<br><br> Data Path: re to empty<br> Gate Net<br> Cell:in->out fanout Delay Delay Logical Name (Net Name)<br> ---------------------------------------- ------------<br> LUT5:I0->O 1 0.068 0.581 wp_s[5]_re_OR_6_o3 (wp_s[5]_re_OR_6_o3)<br> LUT5:I2->O 1 0.068 0.000 wp_s[5]_re_OR_6_o5 (wp_s[5]_re_OR_6_o)<br> FD:D 0.011 empty<br> ----------------------------------------<br> Total 1.104ns (0.523ns logic, 0.581ns route)<br> (47.4% logic, 52.6% route)<br><br>=========================================================================<br>Timing constraint: Default OFFSET IN BEFORE for Clock 'wr_clk'<br> Total number of paths / destination ports: 34 / 33<br>-------------------------------------------------------------------------<br>Offset: 1.104ns (Levels of Logic = 2)<br> Source: we (PAD)<br> Destination: full (FF)<br> Destination Clock: wr_clk rising<br><br> Data Path: we to full<br> Gate Net<br> Cell:in->out fanout Delay Delay Logical Name (Net Name)<br> ---------------------------------------- ------------<br> LUT5:I0->O 1 0.068 0.581 wp[4]_we_OR_11_o3 (wp[4]_we_OR_11_o3)<br> LUT5:I2->O 1 0.068 0.000 wp[4]_we_OR_11_o5 (wp[4]_we_OR_11_o)<br> FD:D 0.011 full<br> ----------------------------------------<br> Total 1.104ns (0.523ns logic, 0.581ns route)<br> (47.4% logic, 52.6% route)<br><br>=========================================================================<br>Timing constraint: Default OFFSET OUT AFTER for Clock 'rd_clk'<br> Total number of paths / destination ports: 35 / 35<br>-------------------------------------------------------------------------<br>Offset: 0.742ns (Levels of Logic = 0)<br> Source: u0/Mram_RAM (RAM)<br> Destination: dout<31> (PAD)<br> Source Clock: rd_clk rising<br><br> Data Path: u0/Mram_RAM to dout<31><br> Gate Net<br> Cell:in->out fanout Delay Delay Logical Name (Net Name)<br> ---------------------------------------- ------------<br> RAMB18E1:CLKARDCLK->DOBDO15 0 0.742 0.000 u0/Mram_RAM (dout<31>)<br> ----------------------------------------<br> Total 0.742ns (0.742ns logic, 0.000ns route)<br> (100.0% logic, 0.0% route)<br><br>=========================================================================<br>Timing constraint: Default OFFSET OUT AFTER for Clock 'wr_clk'<br> Total number of paths / destination ports: 5 / 5<br>-------------------------------------------------------------------------<br>Offset: 0.375ns (Levels of Logic = 0)<br> Source: level_1 (FF)<br> Destination: level<1> (PAD)<br> Source Clock: wr_clk rising<br><br> Data Path: level_1 to level<1><br> Gate Net<br> Cell:in->out fanout Delay Delay Logical Name (Net Name)<br> ---------------------------------------- ------------<br> FD:C->Q 0 0.375 0.000 level_1 (level_1)<br> ----------------------------------------<br> Total 0.375ns (0.375ns logic, 0.000ns route)<br> (100.0% logic, 0.0% route)<br><br>=========================================================================<br><br>Cross Clock Domains Report:<br>--------------------------<br><br>Clock to Setup on destination clock rd_clk<br>---------------+---------+---------+---------+---------+<br> | Src:Rise| Src:Fall| Src:Rise| Src:Fall|<br>Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|<br>---------------+---------+---------+---------+---------+<br>rd_clk | 2.312| | | |<br>wr_clk | 1.544| | | |<br>---------------+---------+---------+---------+---------+<br><br>Clock to Setup on destination clock wr_clk<br>---------------+---------+---------+---------+---------+<br> | Src:Rise| Src:Fall| Src:Rise| Src:Fall|<br>Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|<br>---------------+---------+---------+---------+---------+<br>rd_clk | 2.171| | | |<br>wr_clk | 2.312| | | |<br>---------------+---------+---------+---------+---------+<br><br>=========================================================================<br><br><br>Total REAL time to Xst completion: 10.00 secs<br>Total CPU time to Xst completion: 9.75 secs<br> <br>--> <br><br><br>Total memory usage is 416720 kilobytes<br><br>Number of errors : 0 ( 0 filtered)<br>Number of warnings : 0 ( 0 filtered)<br>Number of infos : 2 ( 0 filtered)<br><br></PRE></FONT> |
/trunk/syn/xilinx/log/fifo/generic_fifo_dc_aw7_summary.html
0,0 → 1,112
<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD> |
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'> |
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'> |
<TD ALIGN=CENTER COLSPAN='4'><B>mod_sim_exp_core Project Status (07/03/2013 - 16:22:14)</B></TD></TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD> |
<TD>msec.xise</TD> |
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD> |
<TD> No Errors </TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD> |
<TD>generic_fifo_dc</TD> |
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD> |
<TD>Synthesized</TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD> |
<TD>xc6vlx240t-1ff1156</TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD> |
<TD> |
No Errors</TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.4</TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD> |
<TD ALIGN=LEFT>No Warnings</TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD> |
<TD>Balanced</TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD> |
<TD> |
</TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD> |
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD> |
<TD> </TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD> |
<TD> |
<A HREF_DISABLED='/home/dinghe/Thesis/mod_sim_exp/trunk/iseproj/msec/generic_fifo_dc_envsettings.html'> |
System Settings</A> |
</TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD> |
<TD> </TD> |
</TR> |
</TABLE> |
|
|
|
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Device Utilization Summary (estimated values)</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary(estimatedvalues)"><B>[-]</B></a></TD></TR> |
<TR ALIGN=CENTER BGCOLOR='#FFFF99'> |
<TD ALIGN=LEFT><B>Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD COLSPAN='2'><B>Utilization</B></TD></TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD> |
<TD ALIGN=RIGHT>58</TD> |
<TD ALIGN=RIGHT>301440</TD> |
<TD ALIGN=RIGHT COLSPAN='2'>0%</TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD> |
<TD ALIGN=RIGHT>57</TD> |
<TD ALIGN=RIGHT>150720</TD> |
<TD ALIGN=RIGHT COLSPAN='2'>0%</TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of fully used LUT-FF pairs</TD> |
<TD ALIGN=RIGHT>48</TD> |
<TD ALIGN=RIGHT>67</TD> |
<TD ALIGN=RIGHT COLSPAN='2'>71%</TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded IOBs</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>600</TD> |
<TD ALIGN=RIGHT COLSPAN='2'>0%</TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Block RAM/FIFO</TD> |
<TD ALIGN=RIGHT>1</TD> |
<TD ALIGN=RIGHT>416</TD> |
<TD ALIGN=RIGHT COLSPAN='2'>0%</TD> |
</TR> |
</TABLE> |
|
|
|
|
|
|
|
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR> |
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD> |
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/dinghe/Thesis/mod_sim_exp/trunk/iseproj/msec/generic_fifo_dc.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Wed Jul 3 16:22:13 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='/home/dinghe/Thesis/mod_sim_exp/trunk/iseproj/msec/_xmsgs/xst.xmsgs?&DataKey=Info'>2 Infos (0 new)</A></TD></TR> |
<TR ALIGN=LEFT><TD>Translation Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD>Map Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
</TABLE> |
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR> |
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR> |
</TABLE> |
|
|
<br><center><b>Date Generated:</b> 07/03/2013 - 16:22:14</center> |
</BODY></HTML> |
/trunk/syn/xilinx/log/fifo/generic_fifo_dc_aw7_syr.html
0,0 → 1,112
<title>Synthesis Report</title><PRE><FONT FACE="Courier New", monotype><p align=left><b>Synthesis Report</b></p><b><center>Wed Jul 3 16:23:00 2013</center></b><br><hr><br>Release 14.4 - xst P.49d (lin64)<br>Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.<br>--> <br>Parameter TMPDIR set to xst/projnav.tmp<br><br><br>Total REAL time to Xst completion: 0.00 secs<br>Total CPU time to Xst completion: 0.05 secs<br> <br>--> <br>Parameter xsthdpdir set to xst<br><br><br>Total REAL time to Xst completion: 0.00 secs<br>Total CPU time to Xst completion: 0.05 secs<br> <br>--> <br>Reading design: generic_fifo_dc.prj<br><br>TABLE OF CONTENTS<br> 1) Synthesis Options Summary<br> 2) HDL Parsing<br> 3) HDL Elaboration<br> 4) HDL Synthesis<br> 4.1) HDL Synthesis Report<br> 5) Advanced HDL Synthesis<br> 5.1) Advanced HDL Synthesis Report<br> 6) Low Level Synthesis<br> 7) Partition Report<br> 8) Design Summary<br> 8.1) Primitive and Black Box Usage<br> 8.2) Device utilization summary<br> 8.3) Partition Resource Summary<br> 8.4) Timing Report<br> 8.4.1) Clock Information<br> 8.4.2) Asynchronous Control Signals Information<br> 8.4.3) Timing Summary<br> 8.4.4) Timing Details<br> 8.4.5) Cross Clock Domains Report<br><br><br>=========================================================================<br>* Synthesis Options Summary *<br>=========================================================================<br>---- Source Parameters<br>Input File Name : "generic_fifo_dc.prj"<br>Ignore Synthesis Constraint File : NO<br><br>---- Target Parameters<br>Output File Name : "generic_fifo_dc"<br>Output Format : NGC<br>Target Device : xc6vlx240t-1-ff1156<br><br>---- Source Options<br>Top Module Name : generic_fifo_dc<br>Automatic FSM Extraction : YES<br>FSM Encoding Algorithm : Auto<br>Safe Implementation : No<br>FSM Style : LUT<br>RAM Extraction : Yes<br>RAM Style : Auto<br>ROM Extraction : Yes<br>Shift Register Extraction : YES<br>ROM Style : Auto<br>Resource Sharing : YES<br>Asynchronous To Synchronous : NO<br>Shift Register Minimum Size : 2<br>Use DSP Block : Auto<br>Automatic Register Balancing : No<br><br>---- Target Options<br>LUT Combining : Auto<br>Reduce Control Sets : Auto<br>Add IO Buffers : NO<br>Global Maximum Fanout : 100000<br>Add Generic Clock Buffer(BUFG) : 32<br>Register Duplication : YES<br>Optimize Instantiated Primitives : NO<br>Use Clock Enable : Auto<br>Use Synchronous Set : Auto<br>Use Synchronous Reset : Auto<br>Pack IO Registers into IOBs : Auto<br>Equivalent register Removal : YES<br><br>---- General Options<br>Optimization Goal : Area<br>Optimization Effort : 2<br>Power Reduction : NO<br>Keep Hierarchy : No<br>Netlist Hierarchy : As_Optimized<br>RTL Output : Yes<br>Global Optimization : AllClockNets<br>Read Cores : YES<br>Write Timing Constraints : NO<br>Cross Clock Analysis : NO<br>Hierarchy Separator : /<br>Bus Delimiter : <><br>Case Specifier : Maintain<br>Slice Utilization Ratio : 100<br>BRAM Utilization Ratio : 100<br>DSP48 Utilization Ratio : 100<br>Auto BRAM Packing : NO<br>Slice Utilization Ratio Delta : 5<br><br>---- Other Options<br>Cores Search Directories : {"../../syn/xilinx/src" }<br><br>=========================================================================<br><br><br>=========================================================================<br>* HDL Parsing *<br>=========================================================================<br>Analyzing Verilog file "/home/dinghe/Thesis/mod_sim_exp/trunk/rtl/verilog/generic_fifo_dc.v" into library work<br>Parsing module <generic_fifo_dc>.<br>Parsing VHDL file "/home/dinghe/Thesis/mod_sim_exp/trunk/rtl/vhdl/core/std_functions.vhd" into library mod_sim_exp<br>Parsing package <std_functions>.<br>Parsing package body <std_functions>.<br>Parsing VHDL file "/home/dinghe/Thesis/mod_sim_exp/trunk/rtl/vhdl/ram/dpram_generic.vhd" into library mod_sim_exp<br>Parsing entity <dpram_generic>.<br>Parsing architecture <behavorial> of entity <dpram_generic>.<br><br>=========================================================================<br>* HDL Elaboration *<br>=========================================================================<br><br>Elaborating module <generic_fifo_dc>.<br>Going to vhdl side to elaborate module dpram_generic<br><br>Elaborating entity <dpram_generic> (architecture <behavorial>) with generics from library <mod_sim_exp>.<br>Back to verilog to continue elaboration<br><br>=========================================================================<br>* HDL Synthesis *<br>=========================================================================<br><br>Synthesizing Unit <generic_fifo_dc>.<br> Related source file is "/home/dinghe/Thesis/mod_sim_exp/trunk/rtl/verilog/generic_fifo_dc.v".<br> dw = 32<br> aw = 7<br> n = 32<br> max_size = 128<br> Found 8-bit register for signal <wp>.<br> Found 8-bit register for signal <rp>.<br> Found 8-bit register for signal <wp_s>.<br> Found 8-bit register for signal <rp_s>.<br> Found 1-bit register for signal <empty>.<br> Found 1-bit register for signal <full>.<br> Found 1-bit register for signal <re_r>.<br> Found 8-bit register for signal <diff_r1>.<br> Found 1-bit register for signal <empty_n>.<br> Found 1-bit register for signal <we_r>.<br> Found 8-bit register for signal <diff_r2>.<br> Found 1-bit register for signal <full_n>.<br> Found 2-bit register for signal <level>.<br> Found 1-bit register for signal <nopop>.<br> Found 1-bit register for signal <nopush>.<br> Found 32-bit register for signal <dout>.<br> Found 8-bit subtractor for signal <diff> created at line 254.<br> Found 8-bit adder for signal <wp_pl1> created at line 217.<br> Found 8-bit adder for signal <rp_pl1> created at line 224.<br> Found 8-bit comparator equal for signal <wp_s[7]_rp[7]_equal_19_o> created at line 243<br> Found 8-bit comparator equal for signal <wp_s[7]_rp_pl1[7]_equal_20_o> created at line 243<br> Found 7-bit comparator equal for signal <wp[6]_rp_s[6]_equal_22_o> created at line 246<br> Found 1-bit comparator not equal for signal <n0022> created at line 246<br> Found 7-bit comparator equal for signal <wp_pl1[6]_rp_s[6]_equal_24_o> created at line 247<br> Found 1-bit comparator not equal for signal <n0027> created at line 247<br> Found 8-bit comparator greater for signal <diff_r1[7]_GND_1_o_LessThan_31_o> created at line 263<br> Found 8-bit comparator greater for signal <GND_1_o_diff_r2[7]_LessThan_37_o> created at line 272<br> Summary:<br> inferred 3 Adder/Subtractor(s).<br> inferred 90 D-type flip-flop(s).<br> inferred 8 Comparator(s).<br>Unit <generic_fifo_dc> synthesized.<br><br>Synthesizing Unit <dpram_generic>.<br> Related source file is "/home/dinghe/Thesis/mod_sim_exp/trunk/rtl/vhdl/ram/dpram_generic.vhd".<br> depth = 128<br> Set property "ram_style = block" for signal <RAM>.<br> Found 128x32-bit dual-port RAM <Mram_RAM> for signal <RAM>.<br> Found 32-bit register for signal <doutB>.<br> Summary:<br> inferred 1 RAM(s).<br> inferred 32 D-type flip-flop(s).<br>Unit <dpram_generic> synthesized.<br><br>=========================================================================<br>HDL Synthesis Report<br><br>Macro Statistics<br># RAMs : 1<br> 128x32-bit dual-port RAM : 1<br># Adders/Subtractors : 3<br> 8-bit adder : 2<br> 8-bit subtractor : 1<br># Registers : 17<br> 1-bit register : 8<br> 2-bit register : 1<br> 32-bit register : 2<br> 8-bit register : 6<br># Comparators : 8<br> 1-bit comparator not equal : 2<br> 7-bit comparator equal : 2<br> 8-bit comparator equal : 2<br> 8-bit comparator greater : 2<br><br>=========================================================================<br><br>=========================================================================<br>* Advanced HDL Synthesis *<br>=========================================================================<br><br><br>Synthesizing (advanced) Unit <generic_fifo_dc>.<br>The following registers are absorbed into counter <rp>: 1 register on signal <rp>.<br>The following registers are absorbed into counter <wp>: 1 register on signal <wp>.<br>INFO:Xst:3226 - The RAM <u0/Mram_RAM> will be implemented as a BLOCK RAM, absorbing the following register(s): <u0/doutB> <dout><br> -----------------------------------------------------------------------<br> | ram_type | Block | |<br> -----------------------------------------------------------------------<br> | Port A |<br> | aspect ratio | 128-word x 32-bit | |<br> | mode | write-first | |<br> | clkA | connected to signal <wr_clk> | rise |<br> | weA | connected to internal node | high |<br> | addrA | connected to signal <wp<6:0>> | |<br> | diA | connected to signal <din> | |<br> -----------------------------------------------------------------------<br> | optimization | area | |<br> -----------------------------------------------------------------------<br> | Port B |<br> | aspect ratio | 128-word x 32-bit | |<br> | mode | write-first | |<br> | clkB | connected to signal <rd_clk> | rise |<br> | addrB | connected to signal <rp<6:0>> | |<br> | doB | connected to signal <dout> | |<br> -----------------------------------------------------------------------<br> | optimization | area | |<br> -----------------------------------------------------------------------<br>Unit <generic_fifo_dc> synthesized (advanced).<br><br>=========================================================================<br>Advanced HDL Synthesis Report<br><br>Macro Statistics<br># RAMs : 1<br> 128x32-bit dual-port block RAM : 1<br># Adders/Subtractors : 3<br> 8-bit adder : 2<br> 8-bit subtractor : 1<br># Counters : 2<br> 8-bit up counter : 2<br># Registers : 42<br> Flip-Flops : 42<br># Comparators : 8<br> 1-bit comparator not equal : 2<br> 7-bit comparator equal : 2<br> 8-bit comparator equal : 2<br> 8-bit comparator greater : 2<br><br>=========================================================================<br><br>=========================================================================<br>* Low Level Synthesis *<br>=========================================================================<br><br>Optimizing unit <generic_fifo_dc> ...<br><br>Mapping all equations...<br>Building and optimizing final netlist ...<br>Found area constraint ratio of 100 (+ 5) on block generic_fifo_dc, actual ratio is 0.<br><br>Final Macro Processing ...<br><br>=========================================================================<br>Final Register Report<br><br>Macro Statistics<br># Registers : 58<br> Flip-Flops : 58<br><br>=========================================================================<br><br>=========================================================================<br>* Partition Report *<br>=========================================================================<br><br>Partition Implementation Status<br>-------------------------------<br><br> No Partitions were found in this design.<br><br>-------------------------------<br><br>=========================================================================<br>* Design Summary *<br>=========================================================================<br><br>Top Level Output File Name : generic_fifo_dc.ngc<br><br>Primitive and Black Box Usage:<br>------------------------------<br># BELS : 105<br># GND : 1<br># INV : 2<br># LUT1 : 14<br># LUT2 : 14<br># LUT3 : 3<br># LUT4 : 1<br># LUT5 : 5<br># LUT6 : 18<br># MUXCY : 21<br># MUXF7 : 1<br># VCC : 1<br># XORCY : 24<br># FlipFlops/Latches : 58<br># FD : 42<br># FDRE : 16<br># RAMS : 1<br># RAMB18E1 : 1<br><br>Device utilization summary:<br>---------------------------<br><br>Selected Device : 6vlx240tff1156-1 <br><br><br>Slice Logic Utilization: <br> Number of Slice Registers: 58 out of 301440 0% <br> Number of Slice LUTs: 57 out of 150720 0% <br> Number used as Logic: 57 out of 150720 0% <br><br>Slice Logic Distribution: <br> Number of LUT Flip Flop pairs used: 67<br> Number with an unused Flip Flop: 9 out of 67 13% <br> Number with an unused LUT: 10 out of 67 14% <br> Number of fully used LUT-FF pairs: 48 out of 67 71% <br> Number of unique control sets: 4<br><br>IO Utilization: <br> Number of IOs: 77<br> Number of bonded IOBs: 0 out of 600 0% <br><br>Specific Feature Utilization:<br> Number of Block RAM/FIFO: 1 out of 416 0% <br> Number using Block RAM only: 1<br><br>---------------------------<br>Partition Resource Summary:<br>---------------------------<br><br> No Partitions were found in this design.<br><br>---------------------------<br><br><br>=========================================================================<br>Timing Report<br><br>NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.<br> FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT<br> GENERATED AFTER PLACE-and-ROUTE.<br><br>Clock Information:<br>------------------<br>-----------------------------------+------------------------+-------+<br>Clock Signal | Clock buffer(FF name) | Load |<br>-----------------------------------+------------------------+-------+<br>rd_clk | NONE(empty) | 29 |<br>wr_clk | NONE(full) | 31 |<br>-----------------------------------+------------------------+-------+<br>INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.<br><br>Asynchronous Control Signals Information:<br>----------------------------------------<br>-----------------------------------+------------------------+-------+<br>Control Signal | Buffer(FF name) | Load |<br>-----------------------------------+------------------------+-------+<br>we_full_AND_3_o(we_full_AND_3_o1:O)| NONE(u0/Mram_RAM) | 8 |<br>-----------------------------------+------------------------+-------+<br><br>Timing Summary:<br>---------------<br>Speed Grade: -1<br><br> Minimum period: 3.177ns (Maximum Frequency: 314.762MHz)<br> Minimum input arrival time before clock: 2.111ns<br> Maximum output required time after clock: 0.742ns<br> Maximum combinational path delay: No path found<br><br>Timing Details:<br>---------------<br>All values displayed in nanoseconds (ns)<br><br>=========================================================================<br>Timing constraint: Default period analysis for Clock 'rd_clk'<br> Clock period: 3.063ns (frequency: 326.477MHz)<br> Total number of paths / destination ports: 184 / 35<br>-------------------------------------------------------------------------<br>Delay: 3.063ns (Levels of Logic = 4)<br> Source: wp_s_7 (FF)<br> Destination: empty (FF)<br> Source Clock: rd_clk rising<br> Destination Clock: rd_clk rising<br><br> Data Path: wp_s_7 to empty<br> Gate Net<br> Cell:in->out fanout Delay Delay Logical Name (Net Name)<br> ---------------------------------------- ------------<br> FD:C->Q 2 0.375 0.784 wp_s_7 (wp_s_7)<br> LUT6:I0->O 2 0.068 0.423 wp_s[7]_re_OR_8_o81 (wp_s[7]_re_OR_8_o_bdd13)<br> LUT6:I5->O 2 0.068 0.423 wp_s[7]_re_OR_8_o51 (wp_s[7]_re_OR_8_o_bdd7)<br> LUT6:I5->O 1 0.068 0.775 wp_s[7]_re_OR_8_o28 (wp_s[7]_re_OR_8_o27)<br> LUT6:I1->O 1 0.068 0.000 wp_s[7]_re_OR_8_o210 (wp_s[7]_re_OR_8_o)<br> FD:D 0.011 empty<br> ----------------------------------------<br> Total 3.063ns (0.658ns logic, 2.405ns route)<br> (21.5% logic, 78.5% route)<br><br>=========================================================================<br>Timing constraint: Default period analysis for Clock 'wr_clk'<br> Clock period: 3.177ns (frequency: 314.762MHz)<br> Total number of paths / destination ports: 258 / 36<br>-------------------------------------------------------------------------<br>Delay: 3.177ns (Levels of Logic = 5)<br> Source: rp_s_5 (FF)<br> Destination: full (FF)<br> Source Clock: wr_clk rising<br> Destination Clock: wr_clk rising<br><br> Data Path: rp_s_5 to full<br> Gate Net<br> Cell:in->out fanout Delay Delay Logical Name (Net Name)<br> ---------------------------------------- ------------<br> FD:C->Q 2 0.375 0.784 rp_s_5 (rp_s_5)<br> LUT6:I0->O 2 0.068 0.423 wp[6]_we_OR_15_o81 (wp[6]_we_OR_15_o_bdd13)<br> LUT6:I5->O 2 0.068 0.423 wp[6]_we_OR_15_o211 (wp[6]_we_OR_15_o_bdd36)<br> LUT3:I2->O 2 0.068 0.644 wp[6]_we_OR_15_o231 (wp[6]_we_OR_15_o_bdd39)<br> LUT5:I1->O 1 0.068 0.000 wp[6]_we_OR_15_o28_F (N10)<br> MUXF7:I0->O 1 0.245 0.000 wp[6]_we_OR_15_o28 (wp[6]_we_OR_15_o)<br> FD:D 0.011 full<br> ----------------------------------------<br> Total 3.177ns (0.903ns logic, 2.274ns route)<br> (28.4% logic, 71.6% route)<br><br>=========================================================================<br>Timing constraint: Default OFFSET IN BEFORE for Clock 'rd_clk'<br> Total number of paths / destination ports: 43 / 37<br>-------------------------------------------------------------------------<br>Offset: 1.792ns (Levels of Logic = 3)<br> Source: re (PAD)<br> Destination: empty (FF)<br> Destination Clock: rd_clk rising<br><br> Data Path: re to empty<br> Gate Net<br> Cell:in->out fanout Delay Delay Logical Name (Net Name)<br> ---------------------------------------- ------------<br> LUT6:I0->O 2 0.068 0.423 wp_s[7]_re_OR_8_o51 (wp_s[7]_re_OR_8_o_bdd7)<br> LUT6:I5->O 1 0.068 0.775 wp_s[7]_re_OR_8_o28 (wp_s[7]_re_OR_8_o27)<br> LUT6:I1->O 1 0.068 0.000 wp_s[7]_re_OR_8_o210 (wp_s[7]_re_OR_8_o)<br> FD:D 0.011 empty<br> ----------------------------------------<br> Total 1.792ns (0.594ns logic, 1.198ns route)<br> (33.1% logic, 66.9% route)<br><br>=========================================================================<br>Timing constraint: Default OFFSET IN BEFORE for Clock 'wr_clk'<br> Total number of paths / destination ports: 43 / 37<br>-------------------------------------------------------------------------<br>Offset: 2.111ns (Levels of Logic = 4)<br> Source: we (PAD)<br> Destination: full (FF)<br> Destination Clock: wr_clk rising<br><br> Data Path: we to full<br> Gate Net<br> Cell:in->out fanout Delay Delay Logical Name (Net Name)<br> ---------------------------------------- ------------<br> LUT5:I0->O 1 0.068 0.491 wp[6]_we_OR_15_o51_SW0 (N6)<br> LUT4:I2->O 2 0.068 0.781 wp[6]_we_OR_15_o41 (wp[6]_we_OR_15_o_bdd5)<br> LUT6:I1->O 1 0.068 0.000 wp[6]_we_OR_15_o28_G (N11)<br> MUXF7:I1->O 1 0.248 0.000 wp[6]_we_OR_15_o28 (wp[6]_we_OR_15_o)<br> FD:D 0.011 full<br> ----------------------------------------<br> Total 2.111ns (0.839ns logic, 1.272ns route)<br> (39.7% logic, 60.3% route)<br><br>=========================================================================<br>Timing constraint: Default OFFSET OUT AFTER for Clock 'rd_clk'<br> Total number of paths / destination ports: 35 / 35<br>-------------------------------------------------------------------------<br>Offset: 0.742ns (Levels of Logic = 0)<br> Source: u0/Mram_RAM (RAM)<br> Destination: dout<31> (PAD)<br> Source Clock: rd_clk rising<br><br> Data Path: u0/Mram_RAM to dout<31><br> Gate Net<br> Cell:in->out fanout Delay Delay Logical Name (Net Name)<br> ---------------------------------------- ------------<br> RAMB18E1:CLKARDCLK->DOBDO15 0 0.742 0.000 u0/Mram_RAM (dout<31>)<br> ----------------------------------------<br> Total 0.742ns (0.742ns logic, 0.000ns route)<br> (100.0% logic, 0.0% route)<br><br>=========================================================================<br>Timing constraint: Default OFFSET OUT AFTER for Clock 'wr_clk'<br> Total number of paths / destination ports: 5 / 5<br>-------------------------------------------------------------------------<br>Offset: 0.375ns (Levels of Logic = 0)<br> Source: level_1 (FF)<br> Destination: level<1> (PAD)<br> Source Clock: wr_clk rising<br><br> Data Path: level_1 to level<1><br> Gate Net<br> Cell:in->out fanout Delay Delay Logical Name (Net Name)<br> ---------------------------------------- ------------<br> FD:C->Q 0 0.375 0.000 level_1 (level_1)<br> ----------------------------------------<br> Total 0.375ns (0.375ns logic, 0.000ns route)<br> (100.0% logic, 0.0% route)<br><br>=========================================================================<br><br>Cross Clock Domains Report:<br>--------------------------<br><br>Clock to Setup on destination clock rd_clk<br>---------------+---------+---------+---------+---------+<br> | Src:Rise| Src:Fall| Src:Rise| Src:Fall|<br>Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|<br>---------------+---------+---------+---------+---------+<br>rd_clk | 3.063| | | |<br>wr_clk | 1.631| | | |<br>---------------+---------+---------+---------+---------+<br><br>Clock to Setup on destination clock wr_clk<br>---------------+---------+---------+---------+---------+<br> | Src:Rise| Src:Fall| Src:Rise| Src:Fall|<br>Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|<br>---------------+---------+---------+---------+---------+<br>rd_clk | 2.136| | | |<br>wr_clk | 3.177| | | |<br>---------------+---------+---------+---------+---------+<br><br>=========================================================================<br><br><br>Total REAL time to Xst completion: 11.00 secs<br>Total CPU time to Xst completion: 11.57 secs<br> <br>--> <br><br><br>Total memory usage is 482304 kilobytes<br><br>Number of errors : 0 ( 0 filtered)<br>Number of warnings : 0 ( 0 filtered)<br>Number of infos : 2 ( 0 filtered)<br><br></PRE></FONT> |
/trunk/syn/xilinx/log/fifo/generic_fifo_dc_gray_aw5_summary.html
0,0 → 1,112
<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD> |
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'> |
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'> |
<TD ALIGN=CENTER COLSPAN='4'><B>mod_sim_exp_core Project Status (07/03/2013 - 16:29:30)</B></TD></TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD> |
<TD>msec.xise</TD> |
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD> |
<TD> No Errors </TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD> |
<TD>generic_fifo_dc_gray</TD> |
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD> |
<TD>Synthesized</TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD> |
<TD>xc6vlx240t-1ff1156</TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD> |
<TD> |
No Errors</TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.4</TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD> |
<TD ALIGN=LEFT><A HREF_DISABLED='/home/dinghe/Thesis/mod_sim_exp/trunk/iseproj/msec/_xmsgs/*.xmsgs?&DataKey=Warning'>12 Warnings (12 new)</A></TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD> |
<TD>Balanced</TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD> |
<TD> |
</TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD> |
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD> |
<TD> </TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD> |
<TD> |
<A HREF_DISABLED='/home/dinghe/Thesis/mod_sim_exp/trunk/iseproj/msec/generic_fifo_dc_gray_envsettings.html'> |
System Settings</A> |
</TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD> |
<TD> </TD> |
</TR> |
</TABLE> |
|
|
|
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Device Utilization Summary (estimated values)</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary(estimatedvalues)"><B>[-]</B></a></TD></TR> |
<TR ALIGN=CENTER BGCOLOR='#FFFF99'> |
<TD ALIGN=LEFT><B>Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD COLSPAN='2'><B>Utilization</B></TD></TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD> |
<TD ALIGN=RIGHT>62</TD> |
<TD ALIGN=RIGHT>301440</TD> |
<TD ALIGN=RIGHT COLSPAN='2'>0%</TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD> |
<TD ALIGN=RIGHT>66</TD> |
<TD ALIGN=RIGHT>150720</TD> |
<TD ALIGN=RIGHT COLSPAN='2'>0%</TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of fully used LUT-FF pairs</TD> |
<TD ALIGN=RIGHT>54</TD> |
<TD ALIGN=RIGHT>74</TD> |
<TD ALIGN=RIGHT COLSPAN='2'>72%</TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded IOBs</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>600</TD> |
<TD ALIGN=RIGHT COLSPAN='2'>0%</TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Block RAM/FIFO</TD> |
<TD ALIGN=RIGHT>1</TD> |
<TD ALIGN=RIGHT>416</TD> |
<TD ALIGN=RIGHT COLSPAN='2'>0%</TD> |
</TR> |
</TABLE> |
|
|
|
|
|
|
|
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR> |
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD> |
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/dinghe/Thesis/mod_sim_exp/trunk/iseproj/msec/generic_fifo_dc_gray.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Wed Jul 3 16:29:29 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='/home/dinghe/Thesis/mod_sim_exp/trunk/iseproj/msec/_xmsgs/xst.xmsgs?&DataKey=Warning'>12 Warnings (12 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='/home/dinghe/Thesis/mod_sim_exp/trunk/iseproj/msec/_xmsgs/xst.xmsgs?&DataKey=Info'>4 Infos (4 new)</A></TD></TR> |
<TR ALIGN=LEFT><TD>Translation Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD>Map Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
</TABLE> |
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR> |
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR> |
</TABLE> |
|
|
<br><center><b>Date Generated:</b> 07/03/2013 - 16:29:30</center> |
</BODY></HTML> |
/trunk/syn/xilinx/log/fifo/generic_fifo_dc_gray_aw5_syr.html
0,0 → 1,112
<title>Synthesis Report</title><PRE><FONT FACE="Courier New", monotype><p align=left><b>Synthesis Report</b></p><b><center>Wed Jul 3 16:30:18 2013</center></b><br><hr><br>Release 14.4 - xst P.49d (lin64)<br>Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.<br>--> <br>Parameter TMPDIR set to xst/projnav.tmp<br><br><br>Total REAL time to Xst completion: 0.00 secs<br>Total CPU time to Xst completion: 0.05 secs<br> <br>--> <br>Parameter xsthdpdir set to xst<br><br><br>Total REAL time to Xst completion: 0.00 secs<br>Total CPU time to Xst completion: 0.05 secs<br> <br>--> <br>Reading design: generic_fifo_dc_gray.prj<br><br>TABLE OF CONTENTS<br> 1) Synthesis Options Summary<br> 2) HDL Parsing<br> 3) HDL Elaboration<br> 4) HDL Synthesis<br> 4.1) HDL Synthesis Report<br> 5) Advanced HDL Synthesis<br> 5.1) Advanced HDL Synthesis Report<br> 6) Low Level Synthesis<br> 7) Partition Report<br> 8) Design Summary<br> 8.1) Primitive and Black Box Usage<br> 8.2) Device utilization summary<br> 8.3) Partition Resource Summary<br> 8.4) Timing Report<br> 8.4.1) Clock Information<br> 8.4.2) Asynchronous Control Signals Information<br> 8.4.3) Timing Summary<br> 8.4.4) Timing Details<br> 8.4.5) Cross Clock Domains Report<br><br><br>=========================================================================<br>* Synthesis Options Summary *<br>=========================================================================<br>---- Source Parameters<br>Input File Name : "generic_fifo_dc_gray.prj"<br>Ignore Synthesis Constraint File : NO<br><br>---- Target Parameters<br>Output File Name : "generic_fifo_dc_gray"<br>Output Format : NGC<br>Target Device : xc6vlx240t-1-ff1156<br><br>---- Source Options<br>Top Module Name : generic_fifo_dc_gray<br>Automatic FSM Extraction : YES<br>FSM Encoding Algorithm : Auto<br>Safe Implementation : No<br>FSM Style : LUT<br>RAM Extraction : Yes<br>RAM Style : Auto<br>ROM Extraction : Yes<br>Shift Register Extraction : YES<br>ROM Style : Auto<br>Resource Sharing : YES<br>Asynchronous To Synchronous : NO<br>Shift Register Minimum Size : 2<br>Use DSP Block : Auto<br>Automatic Register Balancing : No<br><br>---- Target Options<br>LUT Combining : Auto<br>Reduce Control Sets : Auto<br>Add IO Buffers : NO<br>Global Maximum Fanout : 100000<br>Add Generic Clock Buffer(BUFG) : 32<br>Register Duplication : YES<br>Optimize Instantiated Primitives : NO<br>Use Clock Enable : Auto<br>Use Synchronous Set : Auto<br>Use Synchronous Reset : Auto<br>Pack IO Registers into IOBs : Auto<br>Equivalent register Removal : YES<br><br>---- General Options<br>Optimization Goal : Area<br>Optimization Effort : 2<br>Power Reduction : NO<br>Keep Hierarchy : No<br>Netlist Hierarchy : As_Optimized<br>RTL Output : Yes<br>Global Optimization : AllClockNets<br>Read Cores : YES<br>Write Timing Constraints : NO<br>Cross Clock Analysis : NO<br>Hierarchy Separator : /<br>Bus Delimiter : <><br>Case Specifier : Maintain<br>Slice Utilization Ratio : 100<br>BRAM Utilization Ratio : 100<br>DSP48 Utilization Ratio : 100<br>Auto BRAM Packing : NO<br>Slice Utilization Ratio Delta : 5<br><br>---- Other Options<br>Cores Search Directories : {"../../syn/xilinx/src" }<br><br>=========================================================================<br><br><br>=========================================================================<br>* HDL Parsing *<br>=========================================================================<br>Analyzing Verilog file "/home/dinghe/Thesis/mod_sim_exp/trunk/rtl/verilog/generic_fifo_dc_gray.v" into library work<br>Parsing module <generic_fifo_dc_gray>.<br>Parsing VHDL file "/home/dinghe/Thesis/mod_sim_exp/trunk/rtl/vhdl/core/std_functions.vhd" into library mod_sim_exp<br>Parsing package <std_functions>.<br>Parsing package body <std_functions>.<br>Parsing VHDL file "/home/dinghe/Thesis/mod_sim_exp/trunk/rtl/vhdl/ram/dpram_generic.vhd" into library mod_sim_exp<br>Parsing entity <dpram_generic>.<br>Parsing architecture <behavorial> of entity <dpram_generic>.<br><br>=========================================================================<br>* HDL Elaboration *<br>=========================================================================<br><br>Elaborating module <generic_fifo_dc_gray>.<br>Going to vhdl side to elaborate module dpram_generic<br><br>Elaborating entity <dpram_generic> (architecture <behavorial>) with generics from library <mod_sim_exp>.<br>Back to verilog to continue elaboration<br><br>=========================================================================<br>* HDL Synthesis *<br>=========================================================================<br><br>Synthesizing Unit <generic_fifo_dc_gray>.<br> Related source file is "/home/dinghe/Thesis/mod_sim_exp/trunk/rtl/verilog/generic_fifo_dc_gray.v".<br> dw = 32<br> aw = 5<br> Found 1-bit register for signal <rd_clr_r>.<br> Found 1-bit register for signal <wr_clr>.<br> Found 1-bit register for signal <wr_clr_r>.<br> Found 1-bit register for signal <rd_clr>.<br> Found 32-bit register for signal <dout>.<br> Found 6-bit register for signal <wp_bin>.<br> Found 6-bit register for signal <wp_gray>.<br> Found 6-bit register for signal <rp_bin>.<br> Found 6-bit register for signal <rp_gray>.<br> Found 6-bit register for signal <wp_s>.<br> Found 6-bit register for signal <rp_s>.<br> Found 1-bit register for signal <empty>.<br> Found 1-bit register for signal <full>.<br> Found 1-bit register for signal <nopop>.<br> Found 1-bit register for signal <nopush>.<br> Found 1-bit register for signal <full_wc>.<br> Found 5-bit register for signal <rp_bin_xr>.<br> Found 5-bit register for signal <d1>.<br> Found 2-bit register for signal <wr_level>.<br> Found 5-bit register for signal <wp_bin_xr>.<br> Found 5-bit register for signal <d2>.<br> Found 1-bit register for signal <full_rc>.<br> Found 2-bit register for signal <rd_level>.<br> Found 6-bit adder for signal <wp_bin_next> created at line 242.<br> Found 6-bit adder for signal <rp_bin_next> created at line 255.<br> Found 5-bit adder for signal <rp_bin_x[4]_GND_1_o_add_42_OUT> created at line 306.<br> Found 5-bit adder for signal <wp_bin[4]_rp_bin_xr[4]_add_45_OUT> created at line 307.<br> Found 5-bit adder for signal <rp_bin[4]_wp_bin_xr[4]_add_53_OUT> created at line 312.<br> Found 6-bit comparator equal for signal <wp_s[5]_rp_gray[5]_equal_31_o> created at line 278<br> Found 6-bit comparator equal for signal <wp_s[5]_rp_gray_next[5]_equal_32_o> created at line 278<br> Found 5-bit comparator equal for signal <wp_bin[4]_rp_bin_x[4]_equal_34_o> created at line 281<br> Found 1-bit comparator not equal for signal <n0038> created at line 281<br> Found 5-bit comparator equal for signal <wp_bin_next[4]_rp_bin_x[4]_equal_36_o> created at line 282<br> Found 1-bit comparator not equal for signal <n0043> created at line 282<br> Summary:<br> inferred 5 Adder/Subtractor(s).<br> inferred 102 D-type flip-flop(s).<br> inferred 6 Comparator(s).<br>Unit <generic_fifo_dc_gray> synthesized.<br><br>Synthesizing Unit <dpram_generic>.<br> Related source file is "/home/dinghe/Thesis/mod_sim_exp/trunk/rtl/vhdl/ram/dpram_generic.vhd".<br> depth = 32<br> Set property "ram_style = block" for signal <RAM>.<br> Found 32x32-bit dual-port RAM <Mram_RAM> for signal <RAM>.<br> Found 32-bit register for signal <doutB>.<br> Summary:<br> inferred 1 RAM(s).<br> inferred 32 D-type flip-flop(s).<br>Unit <dpram_generic> synthesized.<br><br>=========================================================================<br>HDL Synthesis Report<br><br>Macro Statistics<br># RAMs : 1<br> 32x32-bit dual-port RAM : 1<br># Adders/Subtractors : 5<br> 5-bit adder : 3<br> 6-bit adder : 2<br># Registers : 24<br> 1-bit register : 10<br> 2-bit register : 2<br> 32-bit register : 2<br> 5-bit register : 4<br> 6-bit register : 6<br># Comparators : 6<br> 1-bit comparator not equal : 2<br> 5-bit comparator equal : 2<br> 6-bit comparator equal : 2<br># Xors : 4<br> 6-bit xor2 : 4<br><br>=========================================================================<br><br>=========================================================================<br>* Advanced HDL Synthesis *<br>=========================================================================<br><br>WARNING:Xst:2677 - Node <d2_0> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br>WARNING:Xst:2677 - Node <d2_1> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br>WARNING:Xst:2677 - Node <d2_2> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br>WARNING:Xst:2677 - Node <d1_0> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br>WARNING:Xst:2677 - Node <d1_1> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br>WARNING:Xst:2677 - Node <d1_2> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br><br>Synthesizing (advanced) Unit <generic_fifo_dc_gray>.<br>The following registers are absorbed into counter <rp_bin>: 1 register on signal <rp_bin>.<br>The following registers are absorbed into counter <wp_bin>: 1 register on signal <wp_bin>.<br>INFO:Xst:3226 - The RAM <u0/Mram_RAM> will be implemented as a BLOCK RAM, absorbing the following register(s): <u0/doutB> <dout><br> -----------------------------------------------------------------------<br> | ram_type | Block | |<br> -----------------------------------------------------------------------<br> | Port A |<br> | aspect ratio | 32-word x 32-bit | |<br> | mode | write-first | |<br> | clkA | connected to signal <wr_clk> | rise |<br> | weA | connected to internal node | high |<br> | addrA | connected to signal <wp_bin<4:0>> | |<br> | diA | connected to signal <din> | |<br> -----------------------------------------------------------------------<br> | optimization | area | |<br> -----------------------------------------------------------------------<br> | Port B |<br> | aspect ratio | 32-word x 32-bit | |<br> | mode | write-first | |<br> | clkB | connected to signal <rd_clk> | rise |<br> | addrB | connected to signal <rp_bin<4:0>> | |<br> | doB | connected to signal <dout> | |<br> -----------------------------------------------------------------------<br> | optimization | area | |<br> -----------------------------------------------------------------------<br>Unit <generic_fifo_dc_gray> synthesized (advanced).<br>WARNING:Xst:2677 - Node <d2_0> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br>WARNING:Xst:2677 - Node <d2_1> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br>WARNING:Xst:2677 - Node <d2_2> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br>WARNING:Xst:2677 - Node <d1_0> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br>WARNING:Xst:2677 - Node <d1_1> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br>WARNING:Xst:2677 - Node <d1_2> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br><br>=========================================================================<br>Advanced HDL Synthesis Report<br><br>Macro Statistics<br># RAMs : 1<br> 32x32-bit dual-port block RAM : 1<br># Adders/Subtractors : 5<br> 5-bit adder : 3<br> 6-bit adder : 2<br># Counters : 2<br> 6-bit up counter : 2<br># Registers : 52<br> Flip-Flops : 52<br># Comparators : 6<br> 1-bit comparator not equal : 2<br> 5-bit comparator equal : 2<br> 6-bit comparator equal : 2<br># Xors : 4<br> 6-bit xor2 : 4<br><br>=========================================================================<br><br>=========================================================================<br>* Low Level Synthesis *<br>=========================================================================<br>INFO:Xst:2261 - The FF/Latch <wp_gray_5> in Unit <generic_fifo_dc_gray> is equivalent to the following FF/Latch, which will be removed : <wp_bin_5> <br>INFO:Xst:2261 - The FF/Latch <rp_gray_5> in Unit <generic_fifo_dc_gray> is equivalent to the following FF/Latch, which will be removed : <rp_bin_5> <br><br>Optimizing unit <generic_fifo_dc_gray> ...<br><br>Mapping all equations...<br>Building and optimizing final netlist ...<br>Found area constraint ratio of 100 (+ 5) on block generic_fifo_dc_gray, actual ratio is 0.<br><br>Final Macro Processing ...<br><br>=========================================================================<br>Final Register Report<br><br>Macro Statistics<br># Registers : 62<br> Flip-Flops : 62<br><br>=========================================================================<br><br>=========================================================================<br>* Partition Report *<br>=========================================================================<br><br>Partition Implementation Status<br>-------------------------------<br><br> No Partitions were found in this design.<br><br>-------------------------------<br><br>=========================================================================<br>* Design Summary *<br>=========================================================================<br><br>Top Level Output File Name : generic_fifo_dc_gray.ngc<br><br>Primitive and Black Box Usage:<br>------------------------------<br># BELS : 80<br># GND : 1<br># INV : 4<br># LUT2 : 19<br># LUT3 : 9<br># LUT4 : 7<br># LUT5 : 10<br># LUT6 : 17<br># MUXCY : 8<br># VCC : 1<br># XORCY : 4<br># FlipFlops/Latches : 62<br># FD : 34<br># FDP : 4<br># FDR : 2<br># FDRE : 22<br># RAMS : 1<br># RAMB18E1 : 1<br><br>Device utilization summary:<br>---------------------------<br><br>Selected Device : 6vlx240tff1156-1 <br><br><br>Slice Logic Utilization: <br> Number of Slice Registers: 62 out of 301440 0% <br> Number of Slice LUTs: 66 out of 150720 0% <br> Number used as Logic: 66 out of 150720 0% <br><br>Slice Logic Distribution: <br> Number of LUT Flip Flop pairs used: 74<br> Number with an unused Flip Flop: 12 out of 74 16% <br> Number with an unused LUT: 8 out of 74 10% <br> Number of fully used LUT-FF pairs: 54 out of 74 72% <br> Number of unique control sets: 7<br><br>IO Utilization: <br> Number of IOs: 77<br> Number of bonded IOBs: 0 out of 600 0% <br><br>Specific Feature Utilization:<br> Number of Block RAM/FIFO: 1 out of 416 0% <br> Number using Block RAM only: 1<br><br>---------------------------<br>Partition Resource Summary:<br>---------------------------<br><br> No Partitions were found in this design.<br><br>---------------------------<br><br><br>=========================================================================<br>Timing Report<br><br>NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.<br> FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT<br> GENERATED AFTER PLACE-and-ROUTE.<br><br>Clock Information:<br>------------------<br>-----------------------------------+------------------------+-------+<br>Clock Signal | Clock buffer(FF name) | Load |<br>-----------------------------------+------------------------+-------+<br>rd_clk | NONE(empty) | 32 |<br>wr_clk | NONE(full) | 32 |<br>-----------------------------------+------------------------+-------+<br>INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.<br><br>Asynchronous Control Signals Information:<br>----------------------------------------<br>-----------------------------------+------------------------+-------+<br>Control Signal | Buffer(FF name) | Load |<br>-----------------------------------+------------------------+-------+<br>we_full_AND_3_o(we_full_AND_3_o1:O)| NONE(u0/Mram_RAM) | 8 |<br>-----------------------------------+------------------------+-------+<br><br>Timing Summary:<br>---------------<br>Speed Grade: -1<br><br> Minimum period: 2.974ns (Maximum Frequency: 336.247MHz)<br> Minimum input arrival time before clock: 1.508ns<br> Maximum output required time after clock: 0.742ns<br> Maximum combinational path delay: No path found<br><br>Timing Details:<br>---------------<br>All values displayed in nanoseconds (ns)<br><br>=========================================================================<br>Timing constraint: Default period analysis for Clock 'rd_clk'<br> Clock period: 2.459ns (frequency: 406.669MHz)<br> Total number of paths / destination ports: 164 / 53<br>-------------------------------------------------------------------------<br>Delay: 2.459ns (Levels of Logic = 3)<br> Source: rp_bin_4 (FF)<br> Destination: empty (FF)<br> Source Clock: rd_clk rising<br> Destination Clock: rd_clk rising<br><br> Data Path: rp_bin_4 to empty<br> Gate Net<br> Cell:in->out fanout Delay Delay Logical Name (Net Name)<br> ---------------------------------------- ------------<br> FDRE:C->Q 6 0.375 0.808 rp_bin_4 (rp_bin_4)<br> LUT6:I1->O 2 0.068 0.644 Result<5>2 (Result<5>)<br> LUT6:I2->O 1 0.068 0.417 wp_s[5]_re_OR_6_o5 (wp_s[5]_re_OR_6_o5)<br> LUT5:I4->O 1 0.068 0.000 wp_s[5]_re_OR_6_o6 (wp_s[5]_re_OR_6_o)<br> FD:D 0.011 empty<br> ----------------------------------------<br> Total 2.459ns (0.590ns logic, 1.869ns route)<br> (24.0% logic, 76.0% route)<br><br>=========================================================================<br>Timing constraint: Default period analysis for Clock 'wr_clk'<br> Clock period: 2.974ns (frequency: 336.247MHz)<br> Total number of paths / destination ports: 202 / 51<br>-------------------------------------------------------------------------<br>Delay: 2.974ns (Levels of Logic = 4)<br> Source: wp_bin_4 (FF)<br> Destination: full (FF)<br> Source Clock: wr_clk rising<br> Destination Clock: wr_clk rising<br><br> Data Path: wp_bin_4 to full<br> Gate Net<br> Cell:in->out fanout Delay Delay Logical Name (Net Name)<br> ---------------------------------------- ------------<br> FDRE:C->Q 7 0.375 0.815 wp_bin_4 (wp_bin_4)<br> LUT5:I0->O 2 0.068 0.587 Result<4>11 (Result<4>1)<br> LUT6:I3->O 2 0.068 0.423 wp_bin[4]_we_OR_11_o7 (wp_bin[4]_we_OR_11_o7)<br> LUT5:I4->O 1 0.068 0.491 wp_bin[4]_we_OR_11_o2 (wp_bin[4]_we_OR_11_o2)<br> LUT5:I3->O 1 0.068 0.000 wp_bin[4]_we_OR_11_o5 (wp_bin[4]_we_OR_11_o)<br> FD:D 0.011 full<br> ----------------------------------------<br> Total 2.974ns (0.658ns logic, 2.316ns route)<br> (22.1% logic, 77.9% route)<br><br>=========================================================================<br>Timing constraint: Default OFFSET IN BEFORE for Clock 'rd_clk'<br> Total number of paths / destination ports: 33 / 32<br>-------------------------------------------------------------------------<br>Offset: 1.428ns (Levels of Logic = 3)<br> Source: re (PAD)<br> Destination: empty (FF)<br> Destination Clock: rd_clk rising<br><br> Data Path: re to empty<br> Gate Net<br> Cell:in->out fanout Delay Delay Logical Name (Net Name)<br> ---------------------------------------- ------------<br> LUT6:I0->O 1 0.068 0.417 wp_s[5]_re_OR_6_o4 (wp_s[5]_re_OR_6_o4)<br> LUT6:I5->O 1 0.068 0.417 wp_s[5]_re_OR_6_o5 (wp_s[5]_re_OR_6_o5)<br> LUT5:I4->O 1 0.068 0.000 wp_s[5]_re_OR_6_o6 (wp_s[5]_re_OR_6_o)<br> FD:D 0.011 empty<br> ----------------------------------------<br> Total 1.428ns (0.594ns logic, 0.834ns route)<br> (41.6% logic, 58.4% route)<br><br>=========================================================================<br>Timing constraint: Default OFFSET IN BEFORE for Clock 'wr_clk'<br> Total number of paths / destination ports: 34 / 32<br>-------------------------------------------------------------------------<br>Offset: 1.508ns (Levels of Logic = 3)<br> Source: we (PAD)<br> Destination: full (FF)<br> Destination Clock: wr_clk rising<br><br> Data Path: we to full<br> Gate Net<br> Cell:in->out fanout Delay Delay Logical Name (Net Name)<br> ---------------------------------------- ------------<br> LUT6:I0->O 2 0.068 0.423 wp_bin[4]_we_OR_11_o7 (wp_bin[4]_we_OR_11_o7)<br> LUT5:I4->O 1 0.068 0.491 wp_bin[4]_we_OR_11_o2 (wp_bin[4]_we_OR_11_o2)<br> LUT5:I3->O 1 0.068 0.000 wp_bin[4]_we_OR_11_o5 (wp_bin[4]_we_OR_11_o)<br> FD:D 0.011 full<br> ----------------------------------------<br> Total 1.508ns (0.594ns logic, 0.914ns route)<br> (39.4% logic, 60.6% route)<br><br>=========================================================================<br>Timing constraint: Default OFFSET OUT AFTER for Clock 'rd_clk'<br> Total number of paths / destination ports: 36 / 36<br>-------------------------------------------------------------------------<br>Offset: 0.742ns (Levels of Logic = 0)<br> Source: u0/Mram_RAM (RAM)<br> Destination: dout<31> (PAD)<br> Source Clock: rd_clk rising<br><br> Data Path: u0/Mram_RAM to dout<31><br> Gate Net<br> Cell:in->out fanout Delay Delay Logical Name (Net Name)<br> ---------------------------------------- ------------<br> RAMB18E1:CLKARDCLK->DOBDO15 0 0.742 0.000 u0/Mram_RAM (dout<31>)<br> ----------------------------------------<br> Total 0.742ns (0.742ns logic, 0.000ns route)<br> (100.0% logic, 0.0% route)<br><br>=========================================================================<br>Timing constraint: Default OFFSET OUT AFTER for Clock 'wr_clk'<br> Total number of paths / destination ports: 4 / 4<br>-------------------------------------------------------------------------<br>Offset: 0.375ns (Levels of Logic = 0)<br> Source: wr_level_1 (FF)<br> Destination: wr_level<1> (PAD)<br> Source Clock: wr_clk rising<br><br> Data Path: wr_level_1 to wr_level<1><br> Gate Net<br> Cell:in->out fanout Delay Delay Logical Name (Net Name)<br> ---------------------------------------- ------------<br> FD:C->Q 0 0.375 0.000 wr_level_1 (wr_level_1)<br> ----------------------------------------<br> Total 0.375ns (0.375ns logic, 0.000ns route)<br> (100.0% logic, 0.0% route)<br><br>=========================================================================<br><br>Cross Clock Domains Report:<br>--------------------------<br><br>Clock to Setup on destination clock rd_clk<br>---------------+---------+---------+---------+---------+<br> | Src:Rise| Src:Fall| Src:Rise| Src:Fall|<br>Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|<br>---------------+---------+---------+---------+---------+<br>rd_clk | 2.459| | | |<br>wr_clk | 0.818| | | |<br>---------------+---------+---------+---------+---------+<br><br>Clock to Setup on destination clock wr_clk<br>---------------+---------+---------+---------+---------+<br> | Src:Rise| Src:Fall| Src:Rise| Src:Fall|<br>Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|<br>---------------+---------+---------+---------+---------+<br>rd_clk | 1.572| | | |<br>wr_clk | 2.974| | | |<br>---------------+---------+---------+---------+---------+<br><br>=========================================================================<br><br><br>Total REAL time to Xst completion: 15.00 secs<br>Total CPU time to Xst completion: 15.01 secs<br> <br>--> <br><br><br>Total memory usage is 416708 kilobytes<br><br>Number of errors : 0 ( 0 filtered)<br>Number of warnings : 12 ( 0 filtered)<br>Number of infos : 4 ( 0 filtered)<br><br></PRE></FONT> |
/trunk/syn/xilinx/log/fifo/generic_fifo_dc_gray_aw7_summary.html
0,0 → 1,112
<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD> |
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'> |
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'> |
<TD ALIGN=CENTER COLSPAN='4'><B>mod_sim_exp_core Project Status (07/03/2013 - 16:32:22)</B></TD></TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD> |
<TD>msec.xise</TD> |
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD> |
<TD> No Errors </TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD> |
<TD>generic_fifo_dc_gray</TD> |
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD> |
<TD>Synthesized</TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD> |
<TD>xc6vlx240t-1ff1156</TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD> |
<TD> |
No Errors</TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.4</TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD> |
<TD ALIGN=LEFT><A HREF_DISABLED='/home/dinghe/Thesis/mod_sim_exp/trunk/iseproj/msec/_xmsgs/*.xmsgs?&DataKey=Warning'>20 Warnings (8 new)</A></TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD> |
<TD>Balanced</TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD> |
<TD> |
</TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD> |
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD> |
<TD> </TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD> |
<TD> |
<A HREF_DISABLED='/home/dinghe/Thesis/mod_sim_exp/trunk/iseproj/msec/generic_fifo_dc_gray_envsettings.html'> |
System Settings</A> |
</TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD> |
<TD> </TD> |
</TR> |
</TABLE> |
|
|
|
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Device Utilization Summary (estimated values)</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary(estimatedvalues)"><B>[-]</B></a></TD></TR> |
<TR ALIGN=CENTER BGCOLOR='#FFFF99'> |
<TD ALIGN=LEFT><B>Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD COLSPAN='2'><B>Utilization</B></TD></TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD> |
<TD ALIGN=RIGHT>78</TD> |
<TD ALIGN=RIGHT>301440</TD> |
<TD ALIGN=RIGHT COLSPAN='2'>0%</TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD> |
<TD ALIGN=RIGHT>95</TD> |
<TD ALIGN=RIGHT>150720</TD> |
<TD ALIGN=RIGHT COLSPAN='2'>0%</TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of fully used LUT-FF pairs</TD> |
<TD ALIGN=RIGHT>67</TD> |
<TD ALIGN=RIGHT>106</TD> |
<TD ALIGN=RIGHT COLSPAN='2'>63%</TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded IOBs</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>600</TD> |
<TD ALIGN=RIGHT COLSPAN='2'>0%</TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Block RAM/FIFO</TD> |
<TD ALIGN=RIGHT>1</TD> |
<TD ALIGN=RIGHT>416</TD> |
<TD ALIGN=RIGHT COLSPAN='2'>0%</TD> |
</TR> |
</TABLE> |
|
|
|
|
|
|
|
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR> |
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD> |
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/dinghe/Thesis/mod_sim_exp/trunk/iseproj/msec/generic_fifo_dc_gray.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Wed Jul 3 16:32:21 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='/home/dinghe/Thesis/mod_sim_exp/trunk/iseproj/msec/_xmsgs/xst.xmsgs?&DataKey=Warning'>20 Warnings (8 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='/home/dinghe/Thesis/mod_sim_exp/trunk/iseproj/msec/_xmsgs/xst.xmsgs?&DataKey=Info'>4 Infos (2 new)</A></TD></TR> |
<TR ALIGN=LEFT><TD>Translation Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD>Map Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
</TABLE> |
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR> |
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR> |
</TABLE> |
|
|
<br><center><b>Date Generated:</b> 07/03/2013 - 16:32:22</center> |
</BODY></HTML> |
/trunk/syn/xilinx/log/fifo/generic_fifo_dc_gray_aw7_syr.html
0,0 → 1,112
<title>Synthesis Report</title><PRE><FONT FACE="Courier New", monotype><p align=left><b>Synthesis Report</b></p><b><center>Wed Jul 3 16:32:33 2013</center></b><br><hr><br>Release 14.4 - xst P.49d (lin64)<br>Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.<br>--> <br>Parameter TMPDIR set to xst/projnav.tmp<br><br><br>Total REAL time to Xst completion: 0.00 secs<br>Total CPU time to Xst completion: 0.06 secs<br> <br>--> <br>Parameter xsthdpdir set to xst<br><br><br>Total REAL time to Xst completion: 0.00 secs<br>Total CPU time to Xst completion: 0.06 secs<br> <br>--> <br>Reading design: generic_fifo_dc_gray.prj<br><br>TABLE OF CONTENTS<br> 1) Synthesis Options Summary<br> 2) HDL Parsing<br> 3) HDL Elaboration<br> 4) HDL Synthesis<br> 4.1) HDL Synthesis Report<br> 5) Advanced HDL Synthesis<br> 5.1) Advanced HDL Synthesis Report<br> 6) Low Level Synthesis<br> 7) Partition Report<br> 8) Design Summary<br> 8.1) Primitive and Black Box Usage<br> 8.2) Device utilization summary<br> 8.3) Partition Resource Summary<br> 8.4) Timing Report<br> 8.4.1) Clock Information<br> 8.4.2) Asynchronous Control Signals Information<br> 8.4.3) Timing Summary<br> 8.4.4) Timing Details<br> 8.4.5) Cross Clock Domains Report<br><br><br>=========================================================================<br>* Synthesis Options Summary *<br>=========================================================================<br>---- Source Parameters<br>Input File Name : "generic_fifo_dc_gray.prj"<br>Ignore Synthesis Constraint File : NO<br><br>---- Target Parameters<br>Output File Name : "generic_fifo_dc_gray"<br>Output Format : NGC<br>Target Device : xc6vlx240t-1-ff1156<br><br>---- Source Options<br>Top Module Name : generic_fifo_dc_gray<br>Automatic FSM Extraction : YES<br>FSM Encoding Algorithm : Auto<br>Safe Implementation : No<br>FSM Style : LUT<br>RAM Extraction : Yes<br>RAM Style : Auto<br>ROM Extraction : Yes<br>Shift Register Extraction : YES<br>ROM Style : Auto<br>Resource Sharing : YES<br>Asynchronous To Synchronous : NO<br>Shift Register Minimum Size : 2<br>Use DSP Block : Auto<br>Automatic Register Balancing : No<br><br>---- Target Options<br>LUT Combining : Auto<br>Reduce Control Sets : Auto<br>Add IO Buffers : NO<br>Global Maximum Fanout : 100000<br>Add Generic Clock Buffer(BUFG) : 32<br>Register Duplication : YES<br>Optimize Instantiated Primitives : NO<br>Use Clock Enable : Auto<br>Use Synchronous Set : Auto<br>Use Synchronous Reset : Auto<br>Pack IO Registers into IOBs : Auto<br>Equivalent register Removal : YES<br><br>---- General Options<br>Optimization Goal : Area<br>Optimization Effort : 2<br>Power Reduction : NO<br>Keep Hierarchy : No<br>Netlist Hierarchy : As_Optimized<br>RTL Output : Yes<br>Global Optimization : AllClockNets<br>Read Cores : YES<br>Write Timing Constraints : NO<br>Cross Clock Analysis : NO<br>Hierarchy Separator : /<br>Bus Delimiter : <><br>Case Specifier : Maintain<br>Slice Utilization Ratio : 100<br>BRAM Utilization Ratio : 100<br>DSP48 Utilization Ratio : 100<br>Auto BRAM Packing : NO<br>Slice Utilization Ratio Delta : 5<br><br>---- Other Options<br>Cores Search Directories : {"../../syn/xilinx/src" }<br><br>=========================================================================<br><br><br>=========================================================================<br>* HDL Parsing *<br>=========================================================================<br>Analyzing Verilog file "/home/dinghe/Thesis/mod_sim_exp/trunk/rtl/verilog/generic_fifo_dc_gray.v" into library work<br>Parsing module <generic_fifo_dc_gray>.<br>Parsing VHDL file "/home/dinghe/Thesis/mod_sim_exp/trunk/rtl/vhdl/core/std_functions.vhd" into library mod_sim_exp<br>Parsing package <std_functions>.<br>Parsing package body <std_functions>.<br>Parsing VHDL file "/home/dinghe/Thesis/mod_sim_exp/trunk/rtl/vhdl/ram/dpram_generic.vhd" into library mod_sim_exp<br>Parsing entity <dpram_generic>.<br>Parsing architecture <behavorial> of entity <dpram_generic>.<br><br>=========================================================================<br>* HDL Elaboration *<br>=========================================================================<br><br>Elaborating module <generic_fifo_dc_gray>.<br>Going to vhdl side to elaborate module dpram_generic<br><br>Elaborating entity <dpram_generic> (architecture <behavorial>) with generics from library <mod_sim_exp>.<br>Back to verilog to continue elaboration<br><br>=========================================================================<br>* HDL Synthesis *<br>=========================================================================<br><br>Synthesizing Unit <generic_fifo_dc_gray>.<br> Related source file is "/home/dinghe/Thesis/mod_sim_exp/trunk/rtl/verilog/generic_fifo_dc_gray.v".<br> dw = 32<br> aw = 7<br> Found 1-bit register for signal <rd_clr_r>.<br> Found 1-bit register for signal <wr_clr>.<br> Found 1-bit register for signal <wr_clr_r>.<br> Found 1-bit register for signal <rd_clr>.<br> Found 32-bit register for signal <dout>.<br> Found 8-bit register for signal <wp_bin>.<br> Found 8-bit register for signal <wp_gray>.<br> Found 8-bit register for signal <rp_bin>.<br> Found 8-bit register for signal <rp_gray>.<br> Found 8-bit register for signal <wp_s>.<br> Found 8-bit register for signal <rp_s>.<br> Found 1-bit register for signal <empty>.<br> Found 1-bit register for signal <full>.<br> Found 1-bit register for signal <nopop>.<br> Found 1-bit register for signal <nopush>.<br> Found 1-bit register for signal <full_wc>.<br> Found 7-bit register for signal <rp_bin_xr>.<br> Found 7-bit register for signal <d1>.<br> Found 2-bit register for signal <wr_level>.<br> Found 7-bit register for signal <wp_bin_xr>.<br> Found 7-bit register for signal <d2>.<br> Found 1-bit register for signal <full_rc>.<br> Found 2-bit register for signal <rd_level>.<br> Found 8-bit adder for signal <wp_bin_next> created at line 242.<br> Found 8-bit adder for signal <rp_bin_next> created at line 255.<br> Found 7-bit adder for signal <rp_bin_x[6]_GND_1_o_add_42_OUT> created at line 306.<br> Found 7-bit adder for signal <wp_bin[6]_rp_bin_xr[6]_add_45_OUT> created at line 307.<br> Found 7-bit adder for signal <rp_bin[6]_wp_bin_xr[6]_add_53_OUT> created at line 312.<br> Found 8-bit comparator equal for signal <wp_s[7]_rp_gray[7]_equal_31_o> created at line 278<br> Found 8-bit comparator equal for signal <wp_s[7]_rp_gray_next[7]_equal_32_o> created at line 278<br> Found 7-bit comparator equal for signal <wp_bin[6]_rp_bin_x[6]_equal_34_o> created at line 281<br> Found 1-bit comparator not equal for signal <n0038> created at line 281<br> Found 7-bit comparator equal for signal <wp_bin_next[6]_rp_bin_x[6]_equal_36_o> created at line 282<br> Found 1-bit comparator not equal for signal <n0043> created at line 282<br> Summary:<br> inferred 5 Adder/Subtractor(s).<br> inferred 122 D-type flip-flop(s).<br> inferred 6 Comparator(s).<br>Unit <generic_fifo_dc_gray> synthesized.<br><br>Synthesizing Unit <dpram_generic>.<br> Related source file is "/home/dinghe/Thesis/mod_sim_exp/trunk/rtl/vhdl/ram/dpram_generic.vhd".<br> depth = 128<br> Set property "ram_style = block" for signal <RAM>.<br> Found 128x32-bit dual-port RAM <Mram_RAM> for signal <RAM>.<br> Found 32-bit register for signal <doutB>.<br> Summary:<br> inferred 1 RAM(s).<br> inferred 32 D-type flip-flop(s).<br>Unit <dpram_generic> synthesized.<br><br>=========================================================================<br>HDL Synthesis Report<br><br>Macro Statistics<br># RAMs : 1<br> 128x32-bit dual-port RAM : 1<br># Adders/Subtractors : 5<br> 7-bit adder : 3<br> 8-bit adder : 2<br># Registers : 24<br> 1-bit register : 10<br> 2-bit register : 2<br> 32-bit register : 2<br> 7-bit register : 4<br> 8-bit register : 6<br># Comparators : 6<br> 1-bit comparator not equal : 2<br> 7-bit comparator equal : 2<br> 8-bit comparator equal : 2<br># Xors : 4<br> 8-bit xor2 : 4<br><br>=========================================================================<br><br>=========================================================================<br>* Advanced HDL Synthesis *<br>=========================================================================<br><br>WARNING:Xst:2677 - Node <d2_0> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br>WARNING:Xst:2677 - Node <d2_1> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br>WARNING:Xst:2677 - Node <d2_2> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br>WARNING:Xst:2677 - Node <d2_3> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br>WARNING:Xst:2677 - Node <d2_4> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br>WARNING:Xst:2677 - Node <d1_0> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br>WARNING:Xst:2677 - Node <d1_1> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br>WARNING:Xst:2677 - Node <d1_2> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br>WARNING:Xst:2677 - Node <d1_3> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br>WARNING:Xst:2677 - Node <d1_4> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br><br>Synthesizing (advanced) Unit <generic_fifo_dc_gray>.<br>The following registers are absorbed into counter <rp_bin>: 1 register on signal <rp_bin>.<br>The following registers are absorbed into counter <wp_bin>: 1 register on signal <wp_bin>.<br>INFO:Xst:3226 - The RAM <u0/Mram_RAM> will be implemented as a BLOCK RAM, absorbing the following register(s): <u0/doutB> <dout><br> -----------------------------------------------------------------------<br> | ram_type | Block | |<br> -----------------------------------------------------------------------<br> | Port A |<br> | aspect ratio | 128-word x 32-bit | |<br> | mode | write-first | |<br> | clkA | connected to signal <wr_clk> | rise |<br> | weA | connected to internal node | high |<br> | addrA | connected to signal <wp_bin<6:0>> | |<br> | diA | connected to signal <din> | |<br> -----------------------------------------------------------------------<br> | optimization | area | |<br> -----------------------------------------------------------------------<br> | Port B |<br> | aspect ratio | 128-word x 32-bit | |<br> | mode | write-first | |<br> | clkB | connected to signal <rd_clk> | rise |<br> | addrB | connected to signal <rp_bin<6:0>> | |<br> | doB | connected to signal <dout> | |<br> -----------------------------------------------------------------------<br> | optimization | area | |<br> -----------------------------------------------------------------------<br>Unit <generic_fifo_dc_gray> synthesized (advanced).<br>WARNING:Xst:2677 - Node <d2_0> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br>WARNING:Xst:2677 - Node <d2_1> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br>WARNING:Xst:2677 - Node <d2_2> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br>WARNING:Xst:2677 - Node <d2_3> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br>WARNING:Xst:2677 - Node <d2_4> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br>WARNING:Xst:2677 - Node <d1_0> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br>WARNING:Xst:2677 - Node <d1_1> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br>WARNING:Xst:2677 - Node <d1_2> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br>WARNING:Xst:2677 - Node <d1_3> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br>WARNING:Xst:2677 - Node <d1_4> of sequential type is unconnected in block <generic_fifo_dc_gray>.<br><br>=========================================================================<br>Advanced HDL Synthesis Report<br><br>Macro Statistics<br># RAMs : 1<br> 128x32-bit dual-port block RAM : 1<br># Adders/Subtractors : 5<br> 7-bit adder : 3<br> 8-bit adder : 2<br># Counters : 2<br> 8-bit up counter : 2<br># Registers : 64<br> Flip-Flops : 64<br># Comparators : 6<br> 1-bit comparator not equal : 2<br> 7-bit comparator equal : 2<br> 8-bit comparator equal : 2<br># Xors : 4<br> 8-bit xor2 : 4<br><br>=========================================================================<br><br>=========================================================================<br>* Low Level Synthesis *<br>=========================================================================<br><br>Optimizing unit <generic_fifo_dc_gray> ...<br>INFO:Xst:2261 - The FF/Latch <rp_gray_7> in Unit <generic_fifo_dc_gray> is equivalent to the following FF/Latch, which will be removed : <rp_bin_7> <br>INFO:Xst:2261 - The FF/Latch <wp_gray_7> in Unit <generic_fifo_dc_gray> is equivalent to the following FF/Latch, which will be removed : <wp_bin_7> <br><br>Mapping all equations...<br>Building and optimizing final netlist ...<br>Found area constraint ratio of 100 (+ 5) on block generic_fifo_dc_gray, actual ratio is 0.<br><br>Final Macro Processing ...<br><br>=========================================================================<br>Final Register Report<br><br>Macro Statistics<br># Registers : 78<br> Flip-Flops : 78<br><br>=========================================================================<br><br>=========================================================================<br>* Partition Report *<br>=========================================================================<br><br>Partition Implementation Status<br>-------------------------------<br><br> No Partitions were found in this design.<br><br>-------------------------------<br><br>=========================================================================<br>* Design Summary *<br>=========================================================================<br><br>Top Level Output File Name : generic_fifo_dc_gray.ngc<br><br>Primitive and Black Box Usage:<br>------------------------------<br># BELS : 139<br># GND : 1<br># INV : 4<br># LUT1 : 12<br># LUT2 : 22<br># LUT3 : 14<br># LUT4 : 12<br># LUT5 : 12<br># LUT6 : 19<br># MUXCY : 24<br># VCC : 1<br># XORCY : 18<br># FlipFlops/Latches : 78<br># FD : 42<br># FDP : 4<br># FDR : 2<br># FDRE : 30<br># RAMS : 1<br># RAMB18E1 : 1<br><br>Device utilization summary:<br>---------------------------<br><br>Selected Device : 6vlx240tff1156-1 <br><br><br>Slice Logic Utilization: <br> Number of Slice Registers: 78 out of 301440 0% <br> Number of Slice LUTs: 95 out of 150720 0% <br> Number used as Logic: 95 out of 150720 0% <br><br>Slice Logic Distribution: <br> Number of LUT Flip Flop pairs used: 106<br> Number with an unused Flip Flop: 28 out of 106 26% <br> Number with an unused LUT: 11 out of 106 10% <br> Number of fully used LUT-FF pairs: 67 out of 106 63% <br> Number of unique control sets: 7<br><br>IO Utilization: <br> Number of IOs: 77<br> Number of bonded IOBs: 0 out of 600 0% <br><br>Specific Feature Utilization:<br> Number of Block RAM/FIFO: 1 out of 416 0% <br> Number using Block RAM only: 1<br><br>---------------------------<br>Partition Resource Summary:<br>---------------------------<br><br> No Partitions were found in this design.<br><br>---------------------------<br><br><br>=========================================================================<br>Timing Report<br><br>NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.<br> FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT<br> GENERATED AFTER PLACE-and-ROUTE.<br><br>Clock Information:<br>------------------<br>-----------------------------------+------------------------+-------+<br>Clock Signal | Clock buffer(FF name) | Load |<br>-----------------------------------+------------------------+-------+<br>rd_clk | NONE(empty) | 40 |<br>wr_clk | NONE(full) | 40 |<br>-----------------------------------+------------------------+-------+<br>INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.<br><br>Asynchronous Control Signals Information:<br>----------------------------------------<br>-----------------------------------+------------------------+-------+<br>Control Signal | Buffer(FF name) | Load |<br>-----------------------------------+------------------------+-------+<br>we_full_AND_3_o(we_full_AND_3_o1:O)| NONE(u0/Mram_RAM) | 8 |<br>-----------------------------------+------------------------+-------+<br><br>Timing Summary:<br>---------------<br>Speed Grade: -1<br><br> Minimum period: 2.978ns (Maximum Frequency: 335.796MHz)<br> Minimum input arrival time before clock: 1.589ns<br> Maximum output required time after clock: 0.742ns<br> Maximum combinational path delay: No path found<br><br>Timing Details:<br>---------------<br>All values displayed in nanoseconds (ns)<br><br>=========================================================================<br>Timing constraint: Default period analysis for Clock 'rd_clk'<br> Clock period: 2.637ns (frequency: 379.219MHz)<br> Total number of paths / destination ports: 254 / 69<br>-------------------------------------------------------------------------<br>Delay: 2.637ns (Levels of Logic = 4)<br> Source: rp_bin_2 (FF)<br> Destination: empty (FF)<br> Source Clock: rd_clk rising<br> Destination Clock: rd_clk rising<br><br> Data Path: rp_bin_2 to empty<br> Gate Net<br> Cell:in->out fanout Delay Delay Logical Name (Net Name)<br> ---------------------------------------- ------------<br> FDRE:C->Q 9 0.375 0.634 rp_bin_2 (rp_bin_2)<br> LUT3:I0->O 3 0.068 0.431 Madd_rp_bin_next_cy<2>11 (Madd_rp_bin_next_cy<2>)<br> LUT6:I5->O 2 0.068 0.423 Madd_rp_bin_next_xor<7>11 (rp_bin_next<7>)<br> LUT6:I5->O 1 0.068 0.491 wp_s[7]_re_OR_8_o6_SW0 (N15)<br> LUT6:I4->O 1 0.068 0.000 wp_s[7]_re_OR_8_o7 (wp_s[7]_re_OR_8_o)<br> FD:D 0.011 empty<br> ----------------------------------------<br> Total 2.637ns (0.658ns logic, 1.979ns route)<br> (25.0% logic, 75.0% route)<br><br>=========================================================================<br>Timing constraint: Default period analysis for Clock 'wr_clk'<br> Clock period: 2.978ns (frequency: 335.796MHz)<br> Total number of paths / destination ports: 320 / 67<br>-------------------------------------------------------------------------<br>Delay: 2.978ns (Levels of Logic = 4)<br> Source: wp_bin_4 (FF)<br> Destination: full (FF)<br> Source Clock: wr_clk rising<br> Destination Clock: wr_clk rising<br><br> Data Path: wp_bin_4 to full<br> Gate Net<br> Cell:in->out fanout Delay Delay Logical Name (Net Name)<br> ---------------------------------------- ------------<br> FDRE:C->Q 9 0.375 0.828 wp_bin_4 (wp_bin_4)<br> LUT6:I1->O 4 0.068 0.437 Madd_wp_bin_next_cy<5>11 (Madd_wp_bin_next_cy<5>)<br> LUT2:I1->O 1 0.068 0.638 Madd_wp_bin_next_xor<6>11 (wp_bin_next<6>)<br> LUT6:I2->O 1 0.068 0.417 wp_bin[6]_we_OR_15_o7 (wp_bin[6]_we_OR_15_o7)<br> LUT6:I5->O 1 0.068 0.000 wp_bin[6]_we_OR_15_o8 (wp_bin[6]_we_OR_15_o)<br> FD:D 0.011 full<br> ----------------------------------------<br> Total 2.978ns (0.658ns logic, 2.320ns route)<br> (22.1% logic, 77.9% route)<br><br>=========================================================================<br>Timing constraint: Default OFFSET IN BEFORE for Clock 'rd_clk'<br> Total number of paths / destination ports: 37 / 36<br>-------------------------------------------------------------------------<br>Offset: 1.301ns (Levels of Logic = 2)<br> Source: re (PAD)<br> Destination: empty (FF)<br> Destination Clock: rd_clk rising<br><br> Data Path: re to empty<br> Gate Net<br> Cell:in->out fanout Delay Delay Logical Name (Net Name)<br> ---------------------------------------- ------------<br> LUT6:I0->O 1 0.068 0.775 wp_s[7]_re_OR_8_o5 (wp_s[7]_re_OR_8_o5)<br> LUT6:I1->O 1 0.068 0.000 wp_s[7]_re_OR_8_o7 (wp_s[7]_re_OR_8_o)<br> FD:D 0.011 empty<br> ----------------------------------------<br> Total 1.301ns (0.526ns logic, 0.775ns route)<br> (40.4% logic, 59.6% route)<br><br>=========================================================================<br>Timing constraint: Default OFFSET IN BEFORE for Clock 'wr_clk'<br> Total number of paths / destination ports: 37 / 36<br>-------------------------------------------------------------------------<br>Offset: 1.589ns (Levels of Logic = 3)<br> Source: we (PAD)<br> Destination: full (FF)<br> Destination Clock: wr_clk rising<br><br> Data Path: we to full<br> Gate Net<br> Cell:in->out fanout Delay Delay Logical Name (Net Name)<br> ---------------------------------------- ------------<br> LUT5:I0->O 1 0.068 0.581 wp_bin[6]_we_OR_15_o5 (wp_bin[6]_we_OR_15_o5)<br> LUT6:I3->O 1 0.068 0.417 wp_bin[6]_we_OR_15_o7 (wp_bin[6]_we_OR_15_o7)<br> LUT6:I5->O 1 0.068 0.000 wp_bin[6]_we_OR_15_o8 (wp_bin[6]_we_OR_15_o)<br> FD:D 0.011 full<br> ----------------------------------------<br> Total 1.589ns (0.591ns logic, 0.998ns route)<br> (37.2% logic, 62.8% route)<br><br>=========================================================================<br>Timing constraint: Default OFFSET OUT AFTER for Clock 'rd_clk'<br> Total number of paths / destination ports: 36 / 36<br>-------------------------------------------------------------------------<br>Offset: 0.742ns (Levels of Logic = 0)<br> Source: u0/Mram_RAM (RAM)<br> Destination: dout<31> (PAD)<br> Source Clock: rd_clk rising<br><br> Data Path: u0/Mram_RAM to dout<31><br> Gate Net<br> Cell:in->out fanout Delay Delay Logical Name (Net Name)<br> ---------------------------------------- ------------<br> RAMB18E1:CLKARDCLK->DOBDO15 0 0.742 0.000 u0/Mram_RAM (dout<31>)<br> ----------------------------------------<br> Total 0.742ns (0.742ns logic, 0.000ns route)<br> (100.0% logic, 0.0% route)<br><br>=========================================================================<br>Timing constraint: Default OFFSET OUT AFTER for Clock 'wr_clk'<br> Total number of paths / destination ports: 4 / 4<br>-------------------------------------------------------------------------<br>Offset: 0.375ns (Levels of Logic = 0)<br> Source: wr_level_1 (FF)<br> Destination: wr_level<1> (PAD)<br> Source Clock: wr_clk rising<br><br> Data Path: wr_level_1 to wr_level<1><br> Gate Net<br> Cell:in->out fanout Delay Delay Logical Name (Net Name)<br> ---------------------------------------- ------------<br> FD:C->Q 0 0.375 0.000 wr_level_1 (wr_level_1)<br> ----------------------------------------<br> Total 0.375ns (0.375ns logic, 0.000ns route)<br> (100.0% logic, 0.0% route)<br><br>=========================================================================<br><br>Cross Clock Domains Report:<br>--------------------------<br><br>Clock to Setup on destination clock rd_clk<br>---------------+---------+---------+---------+---------+<br> | Src:Rise| Src:Fall| Src:Rise| Src:Fall|<br>Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|<br>---------------+---------+---------+---------+---------+<br>rd_clk | 2.637| | | |<br>wr_clk | 0.818| | | |<br>---------------+---------+---------+---------+---------+<br><br>Clock to Setup on destination clock wr_clk<br>---------------+---------+---------+---------+---------+<br> | Src:Rise| Src:Fall| Src:Rise| Src:Fall|<br>Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|<br>---------------+---------+---------+---------+---------+<br>rd_clk | 1.598| | | |<br>wr_clk | 2.978| | | |<br>---------------+---------+---------+---------+---------+<br><br>=========================================================================<br><br><br>Total REAL time to Xst completion: 9.00 secs<br>Total CPU time to Xst completion: 9.49 secs<br> <br>--> <br><br><br>Total memory usage is 481856 kilobytes<br><br>Number of errors : 0 ( 0 filtered)<br>Number of warnings : 20 ( 0 filtered)<br>Number of infos : 4 ( 0 filtered)<br><br></PRE></FONT> |
/trunk/syn/xilinx/src/operand_dp.xco
1,89 → 1,108
############################################################## |
# |
# Xilinx Core Generator version 11.4 |
# Date: Fri Mar 16 09:49:36 2012 |
# |
############################################################## |
# |
# This file contains the customisation parameters for a |
# Xilinx CORE Generator IP GUI. It is strongly recommended |
# that you do not manually alter this file as it may cause |
# unexpected and unsupported behavior. |
# |
############################################################## |
# |
# BEGIN Project Options |
SET addpads = False |
SET asysymbol = True |
SET busformat = BusFormatAngleBracketNotRipped |
SET createndf = False |
SET designentry = VHDL |
SET device = xc6vlx240t |
SET devicefamily = virtex6 |
SET flowvendor = Foundation_ISE |
SET formalverification = False |
SET foundationsym = False |
SET implementationfiletype = Ngc |
SET package = ff1156 |
SET removerpms = False |
SET simulationfiles = Behavioral |
SET speedgrade = -1 |
SET verilogsim = True |
SET vhdlsim = True |
# END Project Options |
# BEGIN Select |
SELECT Block_Memory_Generator family Xilinx,_Inc. 3.3 |
# END Select |
# BEGIN Parameters |
CSET additional_inputs_for_power_estimation=false |
CSET algorithm=Minimum_Area |
CSET assume_synchronous_clk=false |
CSET byte_size=9 |
CSET coe_file=no_coe_file_loaded |
CSET collision_warnings=ALL |
CSET component_name=operand_dp |
CSET disable_collision_warnings=false |
CSET disable_out_of_range_warnings=false |
CSET ecc=false |
CSET enable_a=Always_Enabled |
CSET enable_b=Always_Enabled |
CSET error_injection_type=Single_Bit_Error_Injection |
CSET fill_remaining_memory_locations=false |
CSET load_init_file=false |
CSET memory_type=True_Dual_Port_RAM |
CSET operating_mode_a=WRITE_FIRST |
CSET operating_mode_b=WRITE_FIRST |
CSET output_reset_value_a=0 |
CSET output_reset_value_b=0 |
CSET pipeline_stages=0 |
CSET port_a_clock=100 |
CSET port_a_enable_rate=100 |
CSET port_a_write_rate=50 |
CSET port_b_clock=100 |
CSET port_b_enable_rate=100 |
CSET port_b_write_rate=50 |
CSET primitive=8kx2 |
CSET read_width_a=512 |
CSET read_width_b=32 |
CSET register_porta_output_of_memory_core=false |
CSET register_porta_output_of_memory_primitives=false |
CSET register_portb_output_of_memory_core=false |
CSET register_portb_output_of_memory_primitives=false |
CSET remaining_memory_locations=0 |
CSET reset_memory_latch_a=false |
CSET reset_memory_latch_b=false |
CSET reset_priority_a=CE |
CSET reset_priority_b=CE |
CSET reset_type=SYNC |
CSET use_byte_write_enable=false |
CSET use_error_injection_pins=false |
CSET use_regcea_pin=false |
CSET use_regceb_pin=false |
CSET use_rsta_pin=false |
CSET use_rstb_pin=false |
CSET write_depth_a=64 |
CSET write_width_a=32 |
CSET write_width_b=512 |
# END Parameters |
GENERATE |
# CRC: 7cfa6b8b |
############################################################## |
# |
# Xilinx Core Generator version 14.4 |
# Date: Tue Jul 2 16:24:41 2013 |
# |
############################################################## |
# |
# This file contains the customisation parameters for a |
# Xilinx CORE Generator IP GUI. It is strongly recommended |
# that you do not manually alter this file as it may cause |
# unexpected and unsupported behavior. |
# |
############################################################## |
# |
# Generated from component: xilinx.com:ip:blk_mem_gen:7.3 |
# |
############################################################## |
# |
# BEGIN Project Options |
SET addpads = false |
SET asysymbol = true |
SET busformat = BusFormatAngleBracketNotRipped |
SET createndf = false |
SET designentry = VHDL |
SET device = xc7z020 |
SET devicefamily = zynq |
SET flowvendor = Foundation_ISE |
SET formalverification = false |
SET foundationsym = false |
SET implementationfiletype = Ngc |
SET package = clg484 |
SET removerpms = false |
SET simulationfiles = Behavioral |
SET speedgrade = -1 |
SET verilogsim = false |
SET vhdlsim = true |
# END Project Options |
# BEGIN Select |
SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:7.3 |
# END Select |
# BEGIN Parameters |
CSET additional_inputs_for_power_estimation=false |
CSET algorithm=Minimum_Area |
CSET assume_synchronous_clk=false |
CSET axi_id_width=4 |
CSET axi_slave_type=Memory_Slave |
CSET axi_type=AXI4_Full |
CSET byte_size=9 |
CSET coe_file=no_coe_file_loaded |
CSET collision_warnings=ALL |
CSET component_name=operand_dp |
CSET disable_collision_warnings=false |
CSET disable_out_of_range_warnings=false |
CSET ecc=false |
CSET ecctype=No_ECC |
CSET enable_32bit_address=false |
CSET enable_a=Always_Enabled |
CSET enable_b=Always_Enabled |
CSET error_injection_type=Single_Bit_Error_Injection |
CSET fill_remaining_memory_locations=false |
CSET interface_type=Native |
CSET load_init_file=false |
CSET mem_file=no_Mem_file_loaded |
CSET memory_type=True_Dual_Port_RAM |
CSET operating_mode_a=WRITE_FIRST |
CSET operating_mode_b=WRITE_FIRST |
CSET output_reset_value_a=0 |
CSET output_reset_value_b=0 |
CSET pipeline_stages=0 |
CSET port_a_clock=100 |
CSET port_a_enable_rate=100 |
CSET port_a_write_rate=50 |
CSET port_b_clock=100 |
CSET port_b_enable_rate=100 |
CSET port_b_write_rate=50 |
CSET primitive=8kx2 |
CSET read_width_a=32 |
CSET read_width_b=512 |
CSET register_porta_input_of_softecc=false |
CSET register_porta_output_of_memory_core=false |
CSET register_porta_output_of_memory_primitives=false |
CSET register_portb_output_of_memory_core=false |
CSET register_portb_output_of_memory_primitives=false |
CSET register_portb_output_of_softecc=false |
CSET remaining_memory_locations=0 |
CSET reset_memory_latch_a=false |
CSET reset_memory_latch_b=false |
CSET reset_priority_a=CE |
CSET reset_priority_b=CE |
CSET reset_type=SYNC |
CSET softecc=false |
CSET use_axi_id=false |
CSET use_bram_block=Stand_Alone |
CSET use_byte_write_enable=false |
CSET use_error_injection_pins=false |
CSET use_regcea_pin=false |
CSET use_regceb_pin=false |
CSET use_rsta_pin=false |
CSET use_rstb_pin=false |
CSET write_depth_a=64 |
CSET write_width_a=32 |
CSET write_width_b=512 |
# END Parameters |
# BEGIN Extra information |
MISC pkg_timestamp=2012-11-19T16:22:25Z |
# END Extra information |
GENERATE |
# CRC: ab5faf88 |
/trunk/syn/xilinx/src/operands_sp.xco
1,89 → 1,108
############################################################## |
# |
# Xilinx Core Generator version 11.4 |
# Date: Fri Mar 16 09:50:19 2012 |
# |
############################################################## |
# |
# This file contains the customisation parameters for a |
# Xilinx CORE Generator IP GUI. It is strongly recommended |
# that you do not manually alter this file as it may cause |
# unexpected and unsupported behavior. |
# |
############################################################## |
# |
# BEGIN Project Options |
SET addpads = False |
SET asysymbol = True |
SET busformat = BusFormatAngleBracketNotRipped |
SET createndf = False |
SET designentry = VHDL |
SET device = xc6vlx240t |
SET devicefamily = virtex6 |
SET flowvendor = Foundation_ISE |
SET formalverification = False |
SET foundationsym = False |
SET implementationfiletype = Ngc |
SET package = ff1156 |
SET removerpms = False |
SET simulationfiles = Behavioral |
SET speedgrade = -1 |
SET verilogsim = True |
SET vhdlsim = True |
# END Project Options |
# BEGIN Select |
SELECT Block_Memory_Generator family Xilinx,_Inc. 3.3 |
# END Select |
# BEGIN Parameters |
CSET additional_inputs_for_power_estimation=false |
CSET algorithm=Minimum_Area |
CSET assume_synchronous_clk=false |
CSET byte_size=9 |
CSET coe_file=no_coe_file_loaded |
CSET collision_warnings=ALL |
CSET component_name=operands_sp |
CSET disable_collision_warnings=false |
CSET disable_out_of_range_warnings=false |
CSET ecc=false |
CSET enable_a=Always_Enabled |
CSET enable_b=Always_Enabled |
CSET error_injection_type=Single_Bit_Error_Injection |
CSET fill_remaining_memory_locations=false |
CSET load_init_file=false |
CSET memory_type=Single_Port_RAM |
CSET operating_mode_a=WRITE_FIRST |
CSET operating_mode_b=WRITE_FIRST |
CSET output_reset_value_a=0 |
CSET output_reset_value_b=0 |
CSET pipeline_stages=0 |
CSET port_a_clock=100 |
CSET port_a_enable_rate=100 |
CSET port_a_write_rate=50 |
CSET port_b_clock=100 |
CSET port_b_enable_rate=100 |
CSET port_b_write_rate=50 |
CSET primitive=8kx2 |
CSET read_width_a=512 |
CSET read_width_b=32 |
CSET register_porta_output_of_memory_core=false |
CSET register_porta_output_of_memory_primitives=false |
CSET register_portb_output_of_memory_core=false |
CSET register_portb_output_of_memory_primitives=false |
CSET remaining_memory_locations=0 |
CSET reset_memory_latch_a=false |
CSET reset_memory_latch_b=false |
CSET reset_priority_a=CE |
CSET reset_priority_b=CE |
CSET reset_type=SYNC |
CSET use_byte_write_enable=false |
CSET use_error_injection_pins=false |
CSET use_regcea_pin=false |
CSET use_regceb_pin=false |
CSET use_rsta_pin=false |
CSET use_rstb_pin=false |
CSET write_depth_a=32 |
CSET write_width_a=32 |
CSET write_width_b=32 |
# END Parameters |
GENERATE |
# CRC: 13eb5650 |
############################################################## |
# |
# Xilinx Core Generator version 14.4 |
# Date: Tue Jul 2 16:44:14 2013 |
# |
############################################################## |
# |
# This file contains the customisation parameters for a |
# Xilinx CORE Generator IP GUI. It is strongly recommended |
# that you do not manually alter this file as it may cause |
# unexpected and unsupported behavior. |
# |
############################################################## |
# |
# Generated from component: xilinx.com:ip:blk_mem_gen:7.3 |
# |
############################################################## |
# |
# BEGIN Project Options |
SET addpads = false |
SET asysymbol = true |
SET busformat = BusFormatAngleBracketNotRipped |
SET createndf = false |
SET designentry = VHDL |
SET device = xc7z020 |
SET devicefamily = zynq |
SET flowvendor = Foundation_ISE |
SET formalverification = false |
SET foundationsym = false |
SET implementationfiletype = Ngc |
SET package = clg484 |
SET removerpms = false |
SET simulationfiles = Behavioral |
SET speedgrade = -1 |
SET verilogsim = false |
SET vhdlsim = true |
# END Project Options |
# BEGIN Select |
SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:7.3 |
# END Select |
# BEGIN Parameters |
CSET additional_inputs_for_power_estimation=false |
CSET algorithm=Minimum_Area |
CSET assume_synchronous_clk=false |
CSET axi_id_width=4 |
CSET axi_slave_type=Memory_Slave |
CSET axi_type=AXI4_Full |
CSET byte_size=9 |
CSET coe_file=no_coe_file_loaded |
CSET collision_warnings=ALL |
CSET component_name=operands_sp |
CSET disable_collision_warnings=false |
CSET disable_out_of_range_warnings=false |
CSET ecc=false |
CSET ecctype=No_ECC |
CSET enable_32bit_address=false |
CSET enable_a=Always_Enabled |
CSET enable_b=Always_Enabled |
CSET error_injection_type=Single_Bit_Error_Injection |
CSET fill_remaining_memory_locations=false |
CSET interface_type=Native |
CSET load_init_file=false |
CSET mem_file=no_Mem_file_loaded |
CSET memory_type=Single_Port_RAM |
CSET operating_mode_a=WRITE_FIRST |
CSET operating_mode_b=WRITE_FIRST |
CSET output_reset_value_a=0 |
CSET output_reset_value_b=0 |
CSET pipeline_stages=0 |
CSET port_a_clock=100 |
CSET port_a_enable_rate=100 |
CSET port_a_write_rate=50 |
CSET port_b_clock=100 |
CSET port_b_enable_rate=100 |
CSET port_b_write_rate=50 |
CSET primitive=8kx2 |
CSET read_width_a=512 |
CSET read_width_b=32 |
CSET register_porta_input_of_softecc=false |
CSET register_porta_output_of_memory_core=false |
CSET register_porta_output_of_memory_primitives=false |
CSET register_portb_output_of_memory_core=false |
CSET register_portb_output_of_memory_primitives=false |
CSET register_portb_output_of_softecc=false |
CSET remaining_memory_locations=0 |
CSET reset_memory_latch_a=false |
CSET reset_memory_latch_b=false |
CSET reset_priority_a=CE |
CSET reset_priority_b=CE |
CSET reset_type=SYNC |
CSET softecc=false |
CSET use_axi_id=false |
CSET use_bram_block=Stand_Alone |
CSET use_byte_write_enable=false |
CSET use_error_injection_pins=false |
CSET use_regcea_pin=false |
CSET use_regceb_pin=false |
CSET use_rsta_pin=false |
CSET use_rstb_pin=false |
CSET write_depth_a=32 |
CSET write_width_a=32 |
CSET write_width_b=32 |
# END Parameters |
# BEGIN Extra information |
MISC pkg_timestamp=2012-11-19T16:22:25Z |
# END Extra information |
GENERATE |
# CRC: 1a5b155a |