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/trunk/src/DF_mem_ctrl.v
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//----------------------------------------------------------------------- |
// Design : nova |
// Author(s) : Ke Xu |
// Email : eexuke@yahoo.com |
// File : DF_mem_ctrl.v |
// Generated : Nov 27,2005 |
// Copyright (C) 2008 Ke Xu |
//------------------------------------------------------------------------------------------------- |
// Description |
// controller for DF_mbAddrA_RAM & DF_mbAddrB_RAM & dis_frame_RAM |
//------------------------------------------------------------------------------------------------- |
|
// synopsys translate_off |
`include "timescale.v" |
// synopsys translate_on |
`include "nova_defines.v" |
|
module DF_mem_ctrl (clk,reset_n,gclk_end_of_MB_DEC,disable_DF,mb_num_h,mb_num_v, |
bs_curr_MR,bs_curr_MW,blk4x4_sum_counter,blk4x4_rec_counter_2_raster_order, |
DF_edge_counter_MR,DF_edge_counter_MW,one_edge_counter_MR,one_edge_counter_MW, |
blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out, |
p3_MW,p2_MW,p1_MW,p0_MW,q3_MW,q2_MW,q1_MW,q0_MW, |
buf0_0,buf0_1,buf0_2,buf0_3, |
buf2_0,buf2_1,buf2_2,buf2_3,buf3_0,buf3_1,buf3_2,buf3_3, |
t0_0,t0_1,t0_2,t0_3,t1_0,t1_1,t1_2,t1_3,t2_0,t2_1,t2_2,t2_3, |
|
mb_num_h_DF,mb_num_v_DF,end_of_MB_DF,end_of_lastMB_DF, |
DF_mbAddrA_RF_rd,DF_mbAddrA_RF_wr,DF_mbAddrA_RF_rd_addr,DF_mbAddrA_RF_wr_addr,DF_mbAddrA_RF_din, |
DF_mbAddrB_RAM_rd,DF_mbAddrB_RAM_wr,DF_mbAddrB_RAM_addr,DF_mbAddrB_RAM_din, |
dis_frame_RAM_wr,dis_frame_RAM_wr_addr,dis_frame_RAM_din); |
input clk,reset_n; |
input disable_DF; |
input gclk_end_of_MB_DEC; |
input [3:0] mb_num_h; |
input [3:0] mb_num_v; |
input [2:0] bs_curr_MR,bs_curr_MW; |
input [2:0] blk4x4_sum_counter; |
input [4:0] blk4x4_rec_counter_2_raster_order; |
input [5:0] DF_edge_counter_MR,DF_edge_counter_MW; |
input [1:0] one_edge_counter_MR,one_edge_counter_MW; |
input [7:0] blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out; |
input [7:0] p3_MW,p2_MW,p1_MW,p0_MW; |
input [7:0] q3_MW,q2_MW,q1_MW,q0_MW; |
input [31:0] buf0_0,buf0_1,buf0_2,buf0_3; |
input [31:0] buf2_0,buf2_1,buf2_2,buf2_3; |
input [31:0] buf3_0,buf3_1,buf3_2,buf3_3; |
input [31:0] t0_0,t0_1,t0_2,t0_3; |
input [31:0] t1_0,t1_1,t1_2,t1_3; |
input [31:0] t2_0,t2_1,t2_2,t2_3; |
|
output [3:0] mb_num_h_DF; |
output [3:0] mb_num_v_DF; |
output end_of_MB_DF; |
output end_of_lastMB_DF; |
output DF_mbAddrA_RF_rd; |
output DF_mbAddrA_RF_wr; |
output [4:0] DF_mbAddrA_RF_rd_addr; |
output [4:0] DF_mbAddrA_RF_wr_addr; |
output [31:0] DF_mbAddrA_RF_din; |
|
output DF_mbAddrB_RAM_rd; |
output DF_mbAddrB_RAM_wr; |
output [8:0] DF_mbAddrB_RAM_addr; |
output [31:0] DF_mbAddrB_RAM_din; |
|
output dis_frame_RAM_wr; |
output [13:0] dis_frame_RAM_wr_addr; |
output [31:0] dis_frame_RAM_din; |
|
wire Is_mbAddrA_wr; |
wire Is_mbAddrA_real_wr; |
wire Is_mbAddrA_virtual_wr; |
wire Is_mbAddrB_wr; |
wire Is_currMB_wr; |
wire Is_12cycles_wr; |
wire dis_frame_RAM_wr_tmp; |
|
reg [3:0] mb_num_h_DF; |
reg [3:0] mb_num_v_DF; |
always @ (posedge gclk_end_of_MB_DEC or negedge reset_n) |
if (reset_n == 1'b0) |
begin mb_num_h_DF <= 0; mb_num_v_DF <= 0; end |
else if (!disable_DF) |
begin mb_num_h_DF <= mb_num_h; mb_num_v_DF <= mb_num_v; end |
|
|
reg [3:0] DF_12_cycles; |
always @ (posedge clk) |
if (reset_n == 1'b0) |
DF_12_cycles <= 4'd12; |
else if (!disable_DF && DF_edge_counter_MW == 6'd47 && one_edge_counter_MW == 2'd3) |
DF_12_cycles <= 0; |
else if (DF_12_cycles != 4'd12) |
DF_12_cycles <= DF_12_cycles + 1; |
|
reg end_of_MB_DF; |
reg end_of_lastMB_DF;//end of MB_DF of 98th MB of one frame.Does not need to rise MB_rec_DF_align since there is only |
//DF and no reconstruction.So dispart end_of_lastMB_DF from end_of_MB_DF |
|
always @ (posedge clk) |
if (reset_n == 1'b0) |
begin |
end_of_MB_DF <= 1'b0; |
end_of_lastMB_DF <= 1'b0; |
end |
else if (DF_12_cycles == 4'd11) |
begin |
end_of_MB_DF <= (!(mb_num_h_DF == 10 && mb_num_v_DF == 8))? 1'b1:1'b0; |
end_of_lastMB_DF <= (mb_num_h_DF == 10 && mb_num_v_DF == 8)? 1'b1:1'b0; |
end |
else |
begin |
end_of_MB_DF <= 1'b0; |
end_of_lastMB_DF <= 1'b0; |
end |
|
wire [1:0] write_0to3_cycle; |
assign write_0to3_cycle = (DF_12_cycles == 4'd12)? one_edge_counter_MW:DF_12_cycles[1:0]; |
//------------------------------------------------------------------- |
//DF_mbAddrA_RF control |
//------------------------------------------------------------------- |
|
//For edge 18,34,42,it will update mbAddrB of left MB.So no matter bs_curr_MR is equal to 0 or not, |
//mbAddrA should be read out for writing to mbAddrB of left MB.Otherwise,the value written to left |
//mbAddrB will be a wrong value. |
assign DF_mbAddrA_RF_rd = (mb_num_h_DF != 0 && ((( |
DF_edge_counter_MR == 6'd0 || DF_edge_counter_MR == 6'd2 || DF_edge_counter_MR == 6'd16 || |
DF_edge_counter_MR == 6'd32 || DF_edge_counter_MR == 6'd40) && bs_curr_MR != 0) || ( |
DF_edge_counter_MR == 6'd18 || DF_edge_counter_MR == 6'd34 || DF_edge_counter_MR == 6'd42))); |
|
assign DF_mbAddrA_RF_wr = (DF_edge_counter_MW == 6'd16 || DF_edge_counter_MW == 6'd30 || |
DF_edge_counter_MW == 6'd32 || DF_edge_counter_MW == 6'd33 || DF_edge_counter_MW == 6'd40 || |
DF_edge_counter_MW == 6'd41 || DF_12_cycles[3:2] == 2'b01 || DF_12_cycles[3:2] == 2'b10); |
//DF_mbAddrA_RF_rd_addr |
reg [2:0] DF_mbAddrA_RF_rd_addr_blk4x4; |
always @ (DF_mbAddrA_RF_rd or DF_edge_counter_MR) |
if (DF_mbAddrA_RF_rd) |
case (DF_edge_counter_MR) |
6'd0 :DF_mbAddrA_RF_rd_addr_blk4x4 <= 3'd0; //mbAddrA0 |
6'd2 :DF_mbAddrA_RF_rd_addr_blk4x4 <= 3'd1; //mbAddrA1 |
6'd16:DF_mbAddrA_RF_rd_addr_blk4x4 <= 3'd2; //mbAddrA2 |
6'd18:DF_mbAddrA_RF_rd_addr_blk4x4 <= 3'd3; //mbAddrA3 |
6'd32:DF_mbAddrA_RF_rd_addr_blk4x4 <= 3'd4; //mbAddrA4 |
6'd34:DF_mbAddrA_RF_rd_addr_blk4x4 <= 3'd5; //mbAddrA5 |
6'd40:DF_mbAddrA_RF_rd_addr_blk4x4 <= 3'd6; //mbAddrA6 |
6'd42:DF_mbAddrA_RF_rd_addr_blk4x4 <= 3'd7; //mbAddrA7 |
default:DF_mbAddrA_RF_rd_addr_blk4x4 <= 0; |
endcase |
else |
DF_mbAddrA_RF_rd_addr_blk4x4 <= 0; |
assign DF_mbAddrA_RF_rd_addr = {5{DF_mbAddrA_RF_rd}} & |
({DF_mbAddrA_RF_rd_addr_blk4x4,2'b0} + one_edge_counter_MR); |
//DF_mbAddrA_RF_wr_addr |
reg [2:0] DF_mbAddrA_RF_wr_addr_blk4x4; |
always @ (DF_mbAddrA_RF_wr or DF_edge_counter_MW or DF_12_cycles[3:2]) |
if (DF_mbAddrA_RF_wr) |
begin |
if (DF_edge_counter_MW != 6'd48) |
case (DF_edge_counter_MW) |
6'd16:DF_mbAddrA_RF_wr_addr_blk4x4 <= 3'd0; //mbAddrA0 |
6'd30:DF_mbAddrA_RF_wr_addr_blk4x4 <= 3'd1; //mbAddrA1 |
6'd32:DF_mbAddrA_RF_wr_addr_blk4x4 <= 3'd2; //mbAddrA2 |
6'd33:DF_mbAddrA_RF_wr_addr_blk4x4 <= 3'd3; //mbAddrA3 |
6'd40:DF_mbAddrA_RF_wr_addr_blk4x4 <= 3'd4; //mbAddrA4 |
6'd41:DF_mbAddrA_RF_wr_addr_blk4x4 <= 3'd5; //mbAddrA5 |
default:DF_mbAddrA_RF_wr_addr_blk4x4 <= 0; |
endcase |
else if (DF_12_cycles[3:2] == 2'b01) |
DF_mbAddrA_RF_wr_addr_blk4x4 <= 3'd6; |
else |
DF_mbAddrA_RF_wr_addr_blk4x4 <= 3'd7; |
end |
else |
DF_mbAddrA_RF_wr_addr_blk4x4 <= 0; |
|
assign DF_mbAddrA_RF_wr_addr = {5{DF_mbAddrA_RF_wr}} & |
({DF_mbAddrA_RF_wr_addr_blk4x4,2'b0} + write_0to3_cycle); |
|
//DF_mbAddrA_RF_din |
wire Is_mbAddrA_t1; |
assign Is_mbAddrA_t1 = (DF_edge_counter_MW == 6'd30 || DF_edge_counter_MW == 6'd33 || |
DF_edge_counter_MW == 6'd41 || DF_12_cycles[3:2] == 2'b10); |
|
reg [31:0] DF_mbAddrA_RF_din; |
always @ (DF_mbAddrA_RF_wr or Is_mbAddrA_t1 or write_0to3_cycle or |
t0_0 or t0_1 or t0_2 or t0_3 or t1_0 or t1_1 or t1_2 or t1_3) |
if (DF_mbAddrA_RF_wr) |
begin |
if (Is_mbAddrA_t1) |
case (write_0to3_cycle) |
2'd0:DF_mbAddrA_RF_din <= t1_0; |
2'd1:DF_mbAddrA_RF_din <= t1_1; |
2'd2:DF_mbAddrA_RF_din <= t1_2; |
2'd3:DF_mbAddrA_RF_din <= t1_3; |
endcase |
else |
case (write_0to3_cycle) |
2'd0:DF_mbAddrA_RF_din <= t0_0; |
2'd1:DF_mbAddrA_RF_din <= t0_1; |
2'd2:DF_mbAddrA_RF_din <= t0_2; |
2'd3:DF_mbAddrA_RF_din <= t0_3; |
endcase |
end |
else |
DF_mbAddrA_RF_din <= 0; |
//------------------------------------------------------------------- |
//DF_mbAddrB_RAM control |
//------------------------------------------------------------------- |
assign DF_mbAddrB_RAM_rd = ((( |
DF_edge_counter_MR == 6'd4 || DF_edge_counter_MR == 6'd8 || DF_edge_counter_MR == 6'd12 || |
DF_edge_counter_MR == 6'd13 || DF_edge_counter_MR == 6'd36 || DF_edge_counter_MR == 6'd37 || |
DF_edge_counter_MR == 6'd44 || DF_edge_counter_MR == 6'd45) && mb_num_v_DF != 0) || |
DF_edge_counter_MR == 6'd20 || DF_edge_counter_MR == 6'd24 || DF_edge_counter_MR == 6'd28 || |
DF_edge_counter_MR == 6'd29); |
|
wire DF_mbAddrB_RAM_wr_curr; |
assign DF_mbAddrB_RAM_wr_curr = ((( |
DF_edge_counter_MW == 6'd21 || DF_edge_counter_MW == 6'd25 || DF_edge_counter_MW == 6'd30 || |
DF_edge_counter_MW == 6'd31 || DF_edge_counter_MW == 6'd38 || DF_edge_counter_MW == 6'd39 || |
DF_edge_counter_MW == 6'd46 || DF_edge_counter_MW == 6'd47) && mb_num_v_DF != 4'd8) || |
DF_edge_counter_MW == 6'd5 || DF_edge_counter_MW == 6'd9 || DF_edge_counter_MW == 6'd14 || |
DF_edge_counter_MW == 6'd15); |
|
wire DF_mbAddrB_RAM_wr_leftMB; |
assign DF_mbAddrB_RAM_wr_leftMB = (mb_num_h_DF != 0 && mb_num_v_DF != 4'd8 && ( |
DF_edge_counter_MW == 6'd20 || DF_edge_counter_MW == 6'd37 || DF_edge_counter_MW == 6'd45)); |
|
assign DF_mbAddrB_RAM_wr = DF_mbAddrB_RAM_wr_curr | DF_mbAddrB_RAM_wr_leftMB; |
|
reg [2:0] DF_mbAddrB_RAM_addr_blk4x4; |
always @ (DF_mbAddrB_RAM_rd or DF_edge_counter_MR or DF_mbAddrB_RAM_wr_curr |
or DF_mbAddrB_RAM_wr_leftMB or DF_edge_counter_MW) |
if (DF_mbAddrB_RAM_rd) |
case (DF_edge_counter_MR) |
6'd4, 6'd20:DF_mbAddrB_RAM_addr_blk4x4 <= 3'd0; |
6'd8, 6'd24:DF_mbAddrB_RAM_addr_blk4x4 <= 3'd1; |
6'd12,6'd28:DF_mbAddrB_RAM_addr_blk4x4 <= 3'd2; |
6'd13,6'd29:DF_mbAddrB_RAM_addr_blk4x4 <= 3'd3; |
6'd36 :DF_mbAddrB_RAM_addr_blk4x4 <= 3'd4; |
6'd37 :DF_mbAddrB_RAM_addr_blk4x4 <= 3'd5; |
6'd44 :DF_mbAddrB_RAM_addr_blk4x4 <= 3'd6; |
6'd45 :DF_mbAddrB_RAM_addr_blk4x4 <= 3'd7; |
default :DF_mbAddrB_RAM_addr_blk4x4 <= 0; |
endcase |
else if (DF_mbAddrB_RAM_wr_curr) |
case (DF_edge_counter_MW) |
6'd5, 6'd21:DF_mbAddrB_RAM_addr_blk4x4 <= 3'd0; |
6'd9, 6'd25:DF_mbAddrB_RAM_addr_blk4x4 <= 3'd1; |
6'd14,6'd30:DF_mbAddrB_RAM_addr_blk4x4 <= 3'd2; |
6'd15,6'd31:DF_mbAddrB_RAM_addr_blk4x4 <= 3'd3; |
6'd38 :DF_mbAddrB_RAM_addr_blk4x4 <= 3'd4; |
6'd39 :DF_mbAddrB_RAM_addr_blk4x4 <= 3'd5; |
6'd46 :DF_mbAddrB_RAM_addr_blk4x4 <= 3'd6; |
6'd47 :DF_mbAddrB_RAM_addr_blk4x4 <= 3'd7; |
default :DF_mbAddrB_RAM_addr_blk4x4 <= 0; |
endcase |
else if (DF_mbAddrB_RAM_wr_leftMB) |
case (DF_edge_counter_MW) |
6'd20:DF_mbAddrB_RAM_addr_blk4x4 <= 3'd3; |
6'd37:DF_mbAddrB_RAM_addr_blk4x4 <= 3'd5; |
default:DF_mbAddrB_RAM_addr_blk4x4 <= 3'd7; |
endcase |
else |
DF_mbAddrB_RAM_addr_blk4x4 <= 0; |
|
reg [1:0] DF_mbAddrB_RAM_addr_offset; |
always @ (DF_mbAddrB_RAM_rd or one_edge_counter_MR or DF_mbAddrB_RAM_wr or one_edge_counter_MW) |
if (DF_mbAddrB_RAM_rd) DF_mbAddrB_RAM_addr_offset <= one_edge_counter_MR; |
else if (DF_mbAddrB_RAM_wr) DF_mbAddrB_RAM_addr_offset <= one_edge_counter_MW; |
else DF_mbAddrB_RAM_addr_offset <= 0; |
|
wire [3:0] mb_num_h_DF_m1; |
assign mb_num_h_DF_m1 = {4{Is_mbAddrA_wr | DF_mbAddrB_RAM_wr_leftMB}} & (mb_num_h_DF - 1); |
|
wire [8:0] mb_num_h_DF_x32; |
assign mb_num_h_DF_x32 = (DF_mbAddrB_RAM_wr_leftMB)? {mb_num_h_DF_m1,5'b0}:{mb_num_h_DF,5'b0}; |
assign DF_mbAddrB_RAM_addr = mb_num_h_DF_x32 + {DF_mbAddrB_RAM_addr_blk4x4,2'b0} + DF_mbAddrB_RAM_addr_offset; |
|
reg [31:0] DF_mbAddrB_RAM_din; |
always @ (DF_mbAddrB_RAM_wr_curr or DF_mbAddrB_RAM_wr_leftMB or one_edge_counter_MW |
or q0_MW or q1_MW or q2_MW or q3_MW or t2_0 or t2_1 or t2_2 or t2_3) |
if (DF_mbAddrB_RAM_wr_curr) |
DF_mbAddrB_RAM_din <= {q3_MW,q2_MW,q1_MW,q0_MW}; |
else if (DF_mbAddrB_RAM_wr_leftMB) |
case (one_edge_counter_MW) |
2'd0:DF_mbAddrB_RAM_din <= t2_0; |
2'd1:DF_mbAddrB_RAM_din <= t2_1; |
2'd2:DF_mbAddrB_RAM_din <= t2_2; |
2'd3:DF_mbAddrB_RAM_din <= t2_3; |
endcase |
else |
DF_mbAddrB_RAM_din <= 0; |
//------------------------------------------------------------------- |
//dis_frame_RAM write control |
//------------------------------------------------------------------- |
//dis_frame_RAM_wr |
assign Is_mbAddrA_wr = (mb_num_h_DF != 0 && ( |
DF_edge_counter_MW == 6'd0 || DF_edge_counter_MW == 6'd2 || DF_edge_counter_MW == 6'd16 || |
DF_edge_counter_MW == 6'd18 || DF_edge_counter_MW == 6'd32 || DF_edge_counter_MW == 6'd34 || |
DF_edge_counter_MW == 6'd40 || DF_edge_counter_MW == 6'd42)); |
assign Is_mbAddrA_real_wr = (Is_mbAddrA_wr && bs_curr_MW != 0); |
assign Is_mbAddrA_virtual_wr = (Is_mbAddrA_wr && bs_curr_MW == 0); |
|
assign Is_mbAddrB_wr = (mb_num_v_DF != 0 && ( |
DF_edge_counter_MW == 6'd5 || DF_edge_counter_MW == 6'd9 || DF_edge_counter_MW == 6'd13 || |
DF_edge_counter_MW == 6'd14 || DF_edge_counter_MW == 6'd37 || DF_edge_counter_MW == 6'd38 || |
DF_edge_counter_MW == 6'd45 || DF_edge_counter_MW == 6'd46)); |
assign Is_currMB_wr = (( |
DF_edge_counter_MW == 6'd6 || DF_edge_counter_MW == 6'd10 || DF_edge_counter_MW == 6'd15 || |
DF_edge_counter_MW == 6'd17 || DF_edge_counter_MW == 6'd21 || DF_edge_counter_MW == 6'd22 || |
DF_edge_counter_MW == 6'd23 || DF_edge_counter_MW == 6'd25 || DF_edge_counter_MW == 6'd26 || |
DF_edge_counter_MW == 6'd27 || DF_edge_counter_MW == 6'd29 || DF_edge_counter_MW == 6'd30 || |
DF_edge_counter_MW == 6'd31 || DF_edge_counter_MW == 6'd33 || DF_edge_counter_MW == 6'd35 || |
DF_edge_counter_MW == 6'd36 || DF_edge_counter_MW == 6'd39 || DF_edge_counter_MW == 6'd41 || |
DF_edge_counter_MW == 6'd43 || DF_edge_counter_MW == 6'd44 || DF_edge_counter_MW == 6'd47) && |
one_edge_counter_MW != 3'd4); |
assign Is_12cycles_wr = (DF_12_cycles != 4'd12); |
|
assign dis_frame_RAM_wr_tmp = |
( disable_DF && blk4x4_sum_counter[2] != 1'b1) || |
(!disable_DF && (Is_mbAddrA_wr || Is_mbAddrB_wr || Is_currMB_wr || Is_12cycles_wr)); |
assign dis_frame_RAM_wr = (dis_frame_RAM_wr_tmp & (~Is_mbAddrA_virtual_wr)); |
|
wire Is_luma_wr; |
wire Is_chroma_wr; |
wire Is_1st_cycle_wr; //if it is the position of first line of a 4x4 block,for both DF disable & enable |
wire Is_MB_LeftTop_wr; //if it is the position of most left-top for a whole MB,only for DF is disabled |
assign Is_luma_wr = (dis_frame_RAM_wr_tmp && ( |
(disable_DF && blk4x4_rec_counter_2_raster_order[4] == 1'b0) || |
(!disable_DF && (((Is_mbAddrA_wr || Is_mbAddrB_wr) && !DF_edge_counter_MW[5]) || |
(Is_currMB_wr && DF_edge_counter_MW < 6'd39)))))? 1'b1:1'b0; |
|
assign Is_chroma_wr = (dis_frame_RAM_wr_tmp && !Is_luma_wr)? 1'b1:1'b0; |
|
assign Is_1st_cycle_wr = ( |
( disable_DF && blk4x4_sum_counter == 0) || |
(!disable_DF && (one_edge_counter_MW == 0 && (Is_mbAddrA_wr || Is_mbAddrB_wr || Is_currMB_wr)) || |
(DF_12_cycles[1:0] == 2'b00 && DF_12_cycles[3:2] != 2'b11)))? 1'b1:1'b0; |
|
assign Is_MB_LeftTop_wr = (disable_DF && blk4x4_sum_counter == 0 && ( |
(blk4x4_rec_counter_2_raster_order[4] == 1'b0 && blk4x4_rec_counter_2_raster_order[3:0] == 4'b0) || |
(blk4x4_rec_counter_2_raster_order[4] == 1'b1 && blk4x4_rec_counter_2_raster_order[1:0] == 2'b0))) ? 1'b1:1'b0; |
|
//--------------------------------------------------------------------------------- |
// dis_frame_RAM_wr_addr_base |
// Only updated at first write cycle(during 2,3,4 write cycle,it remains unchanged) |
// Luma:0 Cb:6336 Cr:7920 |
//--------------------------------------------------------------------------------- |
reg [12:0] dis_frame_RAM_wr_addr_base; |
always @ (disable_DF or Is_MB_LeftTop_wr or Is_1st_cycle_wr or Is_luma_wr or Is_12cycles_wr |
or blk4x4_rec_counter_2_raster_order[2] or DF_edge_counter_MW) |
if (disable_DF) |
begin |
if (Is_MB_LeftTop_wr) |
begin |
if (Is_luma_wr) //luma |
dis_frame_RAM_wr_addr_base <= 13'd0; |
else if (blk4x4_rec_counter_2_raster_order[2] == 1'b0) //Cb |
dis_frame_RAM_wr_addr_base <= 13'd6336; |
else //Cr |
dis_frame_RAM_wr_addr_base <= 13'd7920; |
end |
else |
dis_frame_RAM_wr_addr_base <= 13'd0; |
end |
else |
begin |
if (Is_1st_cycle_wr) //update only @ 1st write cycle |
begin |
if (Is_luma_wr) //luma |
dis_frame_RAM_wr_addr_base <= 13'd0; |
else if (DF_edge_counter_MW < 6'd45 && DF_edge_counter_MW != 40 && DF_edge_counter_MW != 42) //Cb |
dis_frame_RAM_wr_addr_base <= 13'd6336; |
else //Cr |
dis_frame_RAM_wr_addr_base <= 13'd7920; |
end |
else |
dis_frame_RAM_wr_addr_base <= 0; |
end |
//--------------------------------------------------------------------------------- |
// dis_frame_RAM_wr_addr_x |
// Only updated at first write cycle(during 2,3,4 write cycle,it remains unchanged) |
// x position inside a frame,since every 4 horizontal pixels have been combined as |
// a single 32bit word,thus 0 ~ 43 for luma and 0 ~ 21 for chroma |
//--------------------------------------------------------------------------------- |
wire [3:0] mb_num_v_DF_m1; |
assign mb_num_v_DF_m1 = {4{Is_mbAddrB_wr}} & (mb_num_v_DF - 1); |
|
reg [1:0] blk4x4_xoffset; //0 ~ 3,xoffset for blk4x4 inside a MB |
always @ (Is_luma_wr or Is_mbAddrA_wr or Is_mbAddrB_wr or Is_currMB_wr or DF_12_cycles or DF_edge_counter_MW) |
case ({Is_mbAddrA_wr,Is_mbAddrB_wr,Is_currMB_wr}) |
3'b100: //Is_mbAddrA_wr |
if (Is_luma_wr) blk4x4_xoffset <= 2'd3; |
else blk4x4_xoffset <= 2'd1; |
3'b010: //Is_mbAddrB_wr |
case (DF_edge_counter_MW) |
6'd5,6'd37,6'd45:blk4x4_xoffset <= 2'd0; |
6'd9,6'd38,6'd46:blk4x4_xoffset <= 2'd1; |
6'd13 :blk4x4_xoffset <= 2'd2; |
6'd14 :blk4x4_xoffset <= 2'd3; |
default :blk4x4_xoffset <= 0; |
endcase |
3'b001: //Is_currMB_wr |
case (DF_edge_counter_MW) |
//6'd6,6'd21,6'd23,6'd22,6'd39,6'd41,6'd47:blk4x4_xoffset <= 0; |
6'd10,6'd25,6'd27,6'd26,6'd43,6'd44 :blk4x4_xoffset <= 2'd1; |
6'd15,6'd29,6'd31,6'd33 :blk4x4_xoffset <= 2'd2; |
6'd17,6'd30,6'd35,6'd36 :blk4x4_xoffset <= 2'd3; |
default :blk4x4_xoffset <= 0; |
endcase |
default: |
if (DF_12_cycles != 4'd12) |
case (DF_12_cycles[3:2]) |
2'b00 :blk4x4_xoffset <= 0; //buf2 -> blk22 |
2'b01,2'b10 :blk4x4_xoffset <= 2'd1; //T0 -> blk21,T1 -> blk23 |
default :blk4x4_xoffset <= 0; |
endcase |
else |
blk4x4_xoffset <= 0; |
endcase |
|
reg [5:0] dis_frame_RAM_wr_addr_x; |
|
always @ (disable_DF or Is_MB_LeftTop_wr or Is_1st_cycle_wr or Is_luma_wr or Is_mbAddrA_wr |
or Is_mbAddrB_wr or Is_currMB_wr or blk4x4_rec_counter_2_raster_order[1:0] |
or mb_num_h or mb_num_h_DF_m1 or mb_num_h_DF or blk4x4_xoffset) |
if (disable_DF) |
begin |
if (Is_MB_LeftTop_wr) |
dis_frame_RAM_wr_addr_x <= (Is_luma_wr)? ({mb_num_h,2'b0} + blk4x4_rec_counter_2_raster_order[1:0]):({1'b0,mb_num_h,1'b0} + blk4x4_rec_counter_2_raster_order[0]); |
else |
dis_frame_RAM_wr_addr_x <= 0; |
end |
else |
begin |
if (Is_1st_cycle_wr) |
case ({Is_mbAddrA_wr,Is_mbAddrB_wr,Is_currMB_wr}) |
3'b100: //Is_mbAddrA_wr |
dis_frame_RAM_wr_addr_x <= (Is_luma_wr)? ({mb_num_h_DF_m1,2'b0} + blk4x4_xoffset):({1'b0,mb_num_h_DF_m1,1'b0} + blk4x4_xoffset); |
3'b010,3'b001: //Is_mbAddrB_wr,Is_currMB_wr |
dis_frame_RAM_wr_addr_x <= (Is_luma_wr)? ({mb_num_h_DF,2'b0} + blk4x4_xoffset):({1'b0,mb_num_h_DF,1'b0} + blk4x4_xoffset); |
|
default: //for DF_12_cycles != 4'd12 |
dis_frame_RAM_wr_addr_x <= {1'b0,mb_num_h_DF,1'b0} + blk4x4_xoffset; |
endcase |
else |
dis_frame_RAM_wr_addr_x <= 0; |
end |
//--------------------------------------------------------------------------------- |
// dis_frame_RAM_wr_addr_y |
// a)Only updated at first write cycle(during 2,3,4 write cycle,it remains unchanged) |
// b)For 2,3,4 write cycles,dis_frame_RAM_wr_addr is directly +44/+22 instead of |
// changing dis_frame_RAM_wr_addr_y |
// c)y addr increase 1 means +44 for luma or +22 for choma |
//--------------------------------------------------------------------------------- |
reg [1:0] blk4x4_yoffset; //0 ~ 3,yoffset for blk4x4 inside a MB |
always @ (Is_mbAddrA_wr or Is_currMB_wr or DF_12_cycles or DF_edge_counter_MW) |
if (Is_mbAddrA_wr) |
case (DF_edge_counter_MW) |
6'd0,6'd32,6'd40:blk4x4_yoffset <= 2'd0; |
6'd2,6'd34,6'd42:blk4x4_yoffset <= 2'd1; |
6'd16 :blk4x4_yoffset <= 2'd2; |
6'd18 :blk4x4_yoffset <= 2'd3; |
default :blk4x4_yoffset <= 0; |
endcase |
else if (Is_currMB_wr) |
case (DF_edge_counter_MW) |
//6'd6,6'd10,6'd15,6'd17,6'd39,6'd43,6'd47:blk4x4_yoffset <= 0; |
6'd21,6'd25,6'd29,6'd30,6'd41,6'd44 :blk4x4_yoffset <= 2'd1; |
6'd23,6'd27,6'd31,6'd35 :blk4x4_yoffset <= 2'd2; |
6'd22,6'd26,6'd33,6'd36 :blk4x4_yoffset <= 2'd3; |
default :blk4x4_yoffset <= 0; |
endcase |
else if (DF_12_cycles != 4'd12) |
case (DF_12_cycles[2]) |
1'b0:blk4x4_yoffset <= 2'd1; // 0 ~ 3:buf2->22; 8 ~ 11:T1->23 |
1'b1:blk4x4_yoffset <= 0; // 4 ~ 7:T0->21 |
endcase |
else |
blk4x4_yoffset <= 0; |
|
reg [7:0] dis_frame_RAM_wr_addr_y; //y position inside a frame,0 ~ 143 for luma & 0 ~ 71 for chroma |
always @ (disable_DF or Is_MB_LeftTop_wr or Is_1st_cycle_wr or Is_luma_wr |
or Is_mbAddrA_wr or Is_mbAddrB_wr or Is_mbAddrB_wr or Is_currMB_wr |
or blk4x4_sum_counter[1:0] or blk4x4_rec_counter_2_raster_order[4:1] |
or mb_num_v or mb_num_v_DF or mb_num_v_DF_m1 |
or one_edge_counter_MW or blk4x4_yoffset or DF_12_cycles) |
if (disable_DF) |
begin |
if (Is_MB_LeftTop_wr) |
dis_frame_RAM_wr_addr_y <= (Is_luma_wr)? |
({mb_num_v,4'b0} + {blk4x4_rec_counter_2_raster_order[3:2],2'b00} + blk4x4_sum_counter[1:0]): |
({1'b0,mb_num_v,3'b0} + {blk4x4_rec_counter_2_raster_order[1], 2'b00} + blk4x4_sum_counter[1:0]); |
else |
dis_frame_RAM_wr_addr_y <= 0; |
end |
else |
begin |
if (Is_1st_cycle_wr) |
case ({Is_mbAddrA_wr,Is_mbAddrB_wr,Is_currMB_wr}) |
3'b100: //Is_mbAddrA_wr |
dis_frame_RAM_wr_addr_y <= (Is_luma_wr)? //luma or chroma |
(({mb_num_v_DF,4'b0} + {2'b00,blk4x4_yoffset,2'b00}) + one_edge_counter_MW): |
(({1'b0,mb_num_v_DF,3'b0} + {2'b00,blk4x4_yoffset,2'b00}) + one_edge_counter_MW); |
3'b010: //Is_mbAddrB_wr |
dis_frame_RAM_wr_addr_y <= (Is_luma_wr)? //luma or chroma |
(({mb_num_v_DF_m1,4'b0} + 4'd12) + one_edge_counter_MW): |
(({1'b0,mb_num_v_DF_m1,3'b0} + 4'd4 ) + one_edge_counter_MW); |
3'b001: //Is_currMB_wr |
dis_frame_RAM_wr_addr_y <= (Is_luma_wr)? //luma or chroma |
(({mb_num_v_DF,4'b0} + {blk4x4_yoffset,2'b0}) + one_edge_counter_MW): |
(({1'b0,mb_num_v_DF,3'b0} + {blk4x4_yoffset,2'b0}) + one_edge_counter_MW); |
default: |
if (DF_12_cycles != 4'd12) |
dis_frame_RAM_wr_addr_y <= {mb_num_v_DF,3'b0} + {blk4x4_yoffset,2'b0} + DF_12_cycles[1:0]; |
else |
dis_frame_RAM_wr_addr_y <= 0; |
endcase |
else |
dis_frame_RAM_wr_addr_y <= 0; |
end |
|
|
wire [12:0] dis_frame_RAM_wr_addr_y_ext; //every "y" increase will increase 44(luma) or 22(chroma) for |
//dis_frame_RAM address |
|
assign dis_frame_RAM_wr_addr_y_ext = (Is_luma_wr)? |
//luma, x44 = x32 + x8 + x4 |
( {dis_frame_RAM_wr_addr_y,5'b0} + {2'b0,dis_frame_RAM_wr_addr_y,3'b0} + {3'b0,dis_frame_RAM_wr_addr_y,2'b0}): |
//chroma,x22 = x16 + x4 + x2 |
({1'b0,dis_frame_RAM_wr_addr_y,4'b0} + {3'b0,dis_frame_RAM_wr_addr_y,2'b0} + {4'b0,dis_frame_RAM_wr_addr_y,1'b0}); |
|
wire [13:0] dis_frame_RAM_wr_addr_tmp; |
reg [13:0] dis_frame_RAM_wr_addr_LeftTop_reg; |
reg [13:0] dis_frame_RAM_wr_addr_reg; |
reg [13:0] dis_frame_RAM_wr_addr; |
|
assign dis_frame_RAM_wr_addr_tmp = dis_frame_RAM_wr_addr_base + dis_frame_RAM_wr_addr_y_ext + dis_frame_RAM_wr_addr_x; |
always @ (posedge clk) |
if (reset_n == 1'b0) |
dis_frame_RAM_wr_addr_LeftTop_reg <= 0; |
else if (Is_MB_LeftTop_wr) |
dis_frame_RAM_wr_addr_LeftTop_reg <= dis_frame_RAM_wr_addr_tmp; |
|
always @ (disable_DF or Is_MB_LeftTop_wr or Is_1st_cycle_wr or Is_luma_wr or Is_chroma_wr or dis_frame_RAM_wr_addr_tmp |
or dis_frame_RAM_wr_addr_reg or blk4x4_rec_counter_2_raster_order or dis_frame_RAM_wr_addr_LeftTop_reg) |
if (disable_DF) |
begin |
if (Is_MB_LeftTop_wr) |
dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_tmp; |
else if (Is_1st_cycle_wr) |
case (blk4x4_rec_counter_2_raster_order[4]) |
1'b0: |
case (blk4x4_rec_counter_2_raster_order[3:2]) |
2'b00:dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_LeftTop_reg + blk4x4_rec_counter_2_raster_order[1:0]; |
2'b01:dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_LeftTop_reg + blk4x4_rec_counter_2_raster_order[1:0] + 176; |
2'b10:dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_LeftTop_reg + blk4x4_rec_counter_2_raster_order[1:0] + 352; |
2'b11:dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_LeftTop_reg + blk4x4_rec_counter_2_raster_order[1:0] + 528; |
endcase |
1'b1: |
dis_frame_RAM_wr_addr <= (blk4x4_rec_counter_2_raster_order[1])? |
(dis_frame_RAM_wr_addr_LeftTop_reg + 88 + blk4x4_rec_counter_2_raster_order[0]): |
(dis_frame_RAM_wr_addr_LeftTop_reg + blk4x4_rec_counter_2_raster_order[0]); |
endcase |
else if (Is_luma_wr) |
dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_reg + 44; |
else if (Is_chroma_wr) |
dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_reg + 22; |
else |
dis_frame_RAM_wr_addr <= 0; |
end |
else |
begin |
if (Is_1st_cycle_wr) |
dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_tmp; |
else if (Is_luma_wr) |
dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_reg + 44; |
else if (Is_chroma_wr) |
dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_reg + 22; |
else |
dis_frame_RAM_wr_addr <= 0; |
end |
|
always @ (posedge clk) |
if (reset_n == 1'b0) |
dis_frame_RAM_wr_addr_reg <= 0; |
else if (dis_frame_RAM_wr_tmp) |
dis_frame_RAM_wr_addr_reg <= dis_frame_RAM_wr_addr; |
|
//dis_frame_RAM_din |
wire Is_mbAddrB_t1; |
wire Is_currMB_buf0; |
wire Is_currMB_buf2; |
wire Is_currMB_buf3; |
wire Is_currMB_t1; |
assign Is_mbAddrB_t1 = (DF_edge_counter_MW == 6'd14 || DF_edge_counter_MW == 6'd38 || |
DF_edge_counter_MW == 6'd46); |
assign Is_currMB_buf0 = (DF_edge_counter_MW == 6'd6 || DF_edge_counter_MW == 6'd15 || |
DF_edge_counter_MW == 6'd31 || DF_edge_counter_MW == 6'd39 || |
DF_edge_counter_MW == 6'd47); |
assign Is_currMB_buf2 = (DF_edge_counter_MW == 6'd22 || DF_edge_counter_MW == 6'd33 || |
DF_edge_counter_MW == 6'd41); |
assign Is_currMB_buf3 = (DF_edge_counter_MW == 6'd26); |
assign Is_currMB_t1 = (DF_edge_counter_MW == 6'd10 || DF_edge_counter_MW == 6'd23 || |
DF_edge_counter_MW == 6'd27 || DF_edge_counter_MW == 6'd30 || |
DF_edge_counter_MW == 6'd36 || DF_edge_counter_MW == 6'd44); |
|
reg [31:0] dis_frame_RAM_din; |
always @ (disable_DF or dis_frame_RAM_wr or blk4x4_sum_counter or one_edge_counter_MW or |
DF_12_cycles or Is_mbAddrA_real_wr or Is_mbAddrB_wr or Is_mbAddrB_t1 or Is_currMB_buf0 or |
Is_currMB_buf2 or Is_currMB_buf3 or Is_currMB_t1 or Is_currMB_wr or |
blk4x4_sum_PE0_out or blk4x4_sum_PE1_out or blk4x4_sum_PE2_out or blk4x4_sum_PE3_out or |
p0_MW or p1_MW or p2_MW or p3_MW or |
buf0_0 or buf0_1 or buf0_2 or buf0_3 or |
buf2_0 or buf2_1 or buf2_2 or buf2_3 or buf3_0 or buf3_1 or buf3_2 or buf3_3 or |
t0_0 or t0_1 or t0_2 or t0_3 or t1_0 or t1_1 or t1_2 or t1_3) |
if (disable_DF && dis_frame_RAM_wr) |
begin |
if (blk4x4_sum_counter[2] == 1'b0) |
dis_frame_RAM_din <= {blk4x4_sum_PE3_out,blk4x4_sum_PE2_out,blk4x4_sum_PE1_out,blk4x4_sum_PE0_out}; |
else |
dis_frame_RAM_din <= 0; |
end |
else if (!disable_DF && dis_frame_RAM_wr) |
case ({Is_mbAddrA_real_wr,Is_mbAddrB_wr,Is_currMB_wr}) |
3'b100: //Is_mbAddrA_wr |
dis_frame_RAM_din <= {p0_MW,p1_MW,p2_MW,p3_MW}; |
3'b010: //Is_mbAddrB_wr |
begin |
if (Is_mbAddrB_t1) //T1 -> mbAddrB |
case (one_edge_counter_MW) |
2'd0:dis_frame_RAM_din <= t1_0; |
2'd1:dis_frame_RAM_din <= t1_1; |
2'd2:dis_frame_RAM_din <= t1_2; |
2'd3:dis_frame_RAM_din <= t1_3; |
endcase |
else //T0 -> mbAddrB |
case (one_edge_counter_MW) |
2'd0:dis_frame_RAM_din <= t0_0; |
2'd1:dis_frame_RAM_din <= t0_1; |
2'd2:dis_frame_RAM_din <= t0_2; |
2'd3:dis_frame_RAM_din <= t0_3; |
endcase |
end |
3'b001: //Is_currMB_wr |
case ({Is_currMB_buf0,Is_currMB_buf2,Is_currMB_buf3,Is_currMB_t1}) |
4'b1000: //Is_currMB_buf0 |
case (one_edge_counter_MW) |
2'd0:dis_frame_RAM_din <= buf0_0; |
2'd1:dis_frame_RAM_din <= buf0_1; |
2'd2:dis_frame_RAM_din <= buf0_2; |
2'd3:dis_frame_RAM_din <= buf0_3; |
endcase |
4'b0100: //Is_currMB_buf2 |
case (one_edge_counter_MW) |
2'd0:dis_frame_RAM_din <= buf2_0; |
2'd1:dis_frame_RAM_din <= buf2_1; |
2'd2:dis_frame_RAM_din <= buf2_2; |
2'd3:dis_frame_RAM_din <= buf2_3; |
endcase |
4'b0010: //Is_currMB_buf3 |
case (one_edge_counter_MW) |
2'd0:dis_frame_RAM_din <= buf3_0; |
2'd1:dis_frame_RAM_din <= buf3_1; |
2'd2:dis_frame_RAM_din <= buf3_2; |
2'd3:dis_frame_RAM_din <= buf3_3; |
endcase |
4'b0001: //Is_currMB_t1 |
case (one_edge_counter_MW) |
2'd0:dis_frame_RAM_din <= t1_0; |
2'd1:dis_frame_RAM_din <= t1_1; |
2'd2:dis_frame_RAM_din <= t1_2; |
2'd3:dis_frame_RAM_din <= t1_3; |
endcase |
default: //Is_currMB_t0 |
case (one_edge_counter_MW) |
2'd0:dis_frame_RAM_din <= t0_0; |
2'd1:dis_frame_RAM_din <= t0_1; |
2'd2:dis_frame_RAM_din <= t0_2; |
2'd3:dis_frame_RAM_din <= t0_3; |
endcase |
endcase |
default://additional 12 cycles |
case (DF_12_cycles[3:2]) |
2'b00: //0 ~ 3,buf2 -> blk22 |
case (DF_12_cycles[1:0]) |
2'd0:dis_frame_RAM_din <= buf2_0; |
2'd1:dis_frame_RAM_din <= buf2_1; |
2'd2:dis_frame_RAM_din <= buf2_2; |
2'd3:dis_frame_RAM_din <= buf2_3; |
endcase |
2'b01: //4 ~ 7,T0 -> blk21 |
case (DF_12_cycles[1:0]) |
2'd0:dis_frame_RAM_din <= t0_0; |
2'd1:dis_frame_RAM_din <= t0_1; |
2'd2:dis_frame_RAM_din <= t0_2; |
2'd3:dis_frame_RAM_din <= t0_3; |
endcase |
default://8 ~ 11,T1 -> blk23 |
case (DF_12_cycles[1:0]) |
2'd0:dis_frame_RAM_din <= t1_0; |
2'd1:dis_frame_RAM_din <= t1_1; |
2'd2:dis_frame_RAM_din <= t1_2; |
2'd3:dis_frame_RAM_din <= t1_3; |
endcase |
endcase |
endcase |
else |
dis_frame_RAM_din <= 0; |
endmodule |
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/trunk/src/Inter_pred_CPE.v
0,0 → 1,150
//-------------------------------------------------------------------------------------------------- |
// Design : nova |
// Author(s) : Ke Xu |
// Email : eexuke@yahoo.com |
// File : Inter_pred_CPE.v |
// Generated : Oct 14, 2005 |
// Copyright (C) 2008 Ke Xu |
//------------------------------------------------------------------------------------------------- |
// Description |
// Processing Element for Inter prediction of Chroma pixels |
//------------------------------------------------------------------------------------------------- |
|
// synopsys translate_off |
`include "timescale.v" |
// synopsys translate_on |
`include "nova_defines.v" |
|
module Inter_pred_CPE (xFracC,yFracC, |
Inter_C_window_0_0,Inter_C_window_1_0,Inter_C_window_2_0, |
Inter_C_window_0_1,Inter_C_window_1_1,Inter_C_window_2_1, |
Inter_C_window_0_2,Inter_C_window_1_2,Inter_C_window_2_2, |
CPE0_out,CPE1_out,CPE2_out,CPE3_out); |
input [2:0] xFracC,yFracC; |
input [7:0] Inter_C_window_0_0,Inter_C_window_1_0,Inter_C_window_2_0; |
input [7:0] Inter_C_window_0_1,Inter_C_window_1_1,Inter_C_window_2_1; |
input [7:0] Inter_C_window_0_2,Inter_C_window_1_2,Inter_C_window_2_2; |
output [7:0] CPE0_out,CPE1_out,CPE2_out,CPE3_out; |
|
wire [3:0] xFracC_n,yFracC_n; |
assign xFracC_n = 4'b1000 - xFracC; |
assign yFracC_n = 4'b1000 - yFracC; |
|
CPE CPE0 ( |
.xFracC(xFracC), |
.yFracC(yFracC), |
.xFracC_n(xFracC_n), |
.yFracC_n(yFracC_n), |
.a(Inter_C_window_0_0), |
.b(Inter_C_window_1_0), |
.c(Inter_C_window_0_1), |
.d(Inter_C_window_1_1), |
.out(CPE0_out) |
); |
CPE CPE1 ( |
.xFracC(xFracC), |
.yFracC(yFracC), |
.xFracC_n(xFracC_n), |
.yFracC_n(yFracC_n), |
.a(Inter_C_window_1_0), |
.b(Inter_C_window_2_0), |
.c(Inter_C_window_1_1), |
.d(Inter_C_window_2_1), |
.out(CPE1_out) |
); |
CPE CPE2 ( |
.xFracC(xFracC), |
.yFracC(yFracC), |
.xFracC_n(xFracC_n), |
.yFracC_n(yFracC_n), |
.a(Inter_C_window_0_1), |
.b(Inter_C_window_1_1), |
.c(Inter_C_window_0_2), |
.d(Inter_C_window_1_2), |
.out(CPE2_out) |
); |
CPE CPE3 ( |
.xFracC(xFracC), |
.yFracC(yFracC), |
.xFracC_n(xFracC_n), |
.yFracC_n(yFracC_n), |
.a(Inter_C_window_1_1), |
.b(Inter_C_window_2_1), |
.c(Inter_C_window_1_2), |
.d(Inter_C_window_2_2), |
.out(CPE3_out) |
); |
endmodule |
|
module CPE (xFracC,yFracC,xFracC_n,yFracC_n,a,b,c,d,out); |
input [2:0] xFracC,yFracC; |
input [3:0] xFracC_n,yFracC_n; |
input [7:0] a,b,c,d; |
output [7:0] out; |
|
wire [13:0] CPE_base0_out,CPE_base1_out,CPE_base2_out,CPE_base3_out; |
wire [13:0] out_tmp; |
|
CPE_base CPE_base0 ( |
.x(xFracC_n), |
.y(yFracC_n), |
.Int_pel(a), |
.out(CPE_base0_out) |
); |
CPE_base CPE_base1 ( |
.x({1'b0,xFracC}), |
.y(yFracC_n), |
.Int_pel(b), |
.out(CPE_base1_out) |
); |
CPE_base CPE_base2 ( |
.x(xFracC_n), |
.y({1'b0,yFracC}), |
.Int_pel(c), |
.out(CPE_base2_out) |
); |
CPE_base CPE_base3 ( |
.x({1'b0,xFracC}), |
.y({1'b0,yFracC}), |
.Int_pel(d), |
.out(CPE_base3_out) |
); |
assign out_tmp = (CPE_base0_out + CPE_base1_out) + (CPE_base2_out + CPE_base3_out) + 32; |
assign out = out_tmp[13:6]; |
endmodule |
|
module CPE_base (x,y,Int_pel,out); |
input [3:0] x; |
input [3:0] y; |
input [7:0] Int_pel; |
output [13:0] out; |
|
wire [10:0] sum_x3; |
wire [9:0] sum_x2; |
wire [8:0] sum_x1; |
wire [7:0] sum_x0; |
wire [10:0] sum_x; |
|
wire [13:0] sum_y3; |
wire [12:0] sum_y2; |
wire [11:0] sum_y1; |
wire [10:0] sum_y0; |
|
assign sum_x3 = (x[3] == 1'b1)? {Int_pel,3'b0}:0; |
assign sum_x2 = (x[2] == 1'b1)? {Int_pel,2'b0}:0; |
assign sum_x1 = (x[1] == 1'b1)? {Int_pel,1'b0}:0; |
assign sum_x0 = (x[0] == 1'b1)? Int_pel:0; |
assign sum_x = (sum_x3 + sum_x2) + (sum_x1 + sum_x0); |
|
assign sum_y3 = (y[3] == 1'b1)? {sum_x,3'b0}:0; |
assign sum_y2 = (y[2] == 1'b1)? {sum_x,2'b0}:0; |
assign sum_y1 = (y[1] == 1'b1)? {sum_x,1'b0}:0; |
assign sum_y0 = (y[0] == 1'b1)? sum_x:0; |
assign out = (sum_y3 + sum_y2) + (sum_y1 + sum_y0); |
endmodule |
|
|
|
|
|
|
/trunk/src/Inter_pred_LPE.v
0,0 → 1,591
//-------------------------------------------------------------------------------------------------- |
// Design : nova |
// Author(s) : Ke Xu |
// Email : eexuke@yahoo.com |
// File : Inter_pred_LPE.v |
// Generated : Oct 11, 2005 |
// Copyright (C) 2008 Ke Xu |
//------------------------------------------------------------------------------------------------- |
// Description |
// Processing Element for Inter prediction of Luma pixels |
//------------------------------------------------------------------------------------------------- |
|
// synopsys translate_off |
`include "timescale.v" |
// synopsys translate_on |
`include "nova_defines.v" |
|
module Inter_pred_LPE (clk,reset_n,pos_FracL,IsInterLuma, |
blk4x4_inter_calculate_counter, |
Inter_H_window_0_0,Inter_H_window_1_0,Inter_H_window_2_0,Inter_H_window_3_0,Inter_H_window_4_0,Inter_H_window_5_0, |
Inter_H_window_0_1,Inter_H_window_1_1,Inter_H_window_2_1,Inter_H_window_3_1,Inter_H_window_4_1,Inter_H_window_5_1, |
Inter_H_window_0_2,Inter_H_window_1_2,Inter_H_window_2_2,Inter_H_window_3_2,Inter_H_window_4_2,Inter_H_window_5_2, |
Inter_H_window_0_3,Inter_H_window_1_3,Inter_H_window_2_3,Inter_H_window_3_3,Inter_H_window_4_3,Inter_H_window_5_3, |
Inter_H_window_0_4,Inter_H_window_1_4,Inter_H_window_2_4,Inter_H_window_3_4,Inter_H_window_4_4,Inter_H_window_5_4, |
Inter_H_window_0_5,Inter_H_window_1_5,Inter_H_window_2_5,Inter_H_window_3_5,Inter_H_window_4_5,Inter_H_window_5_5, |
Inter_H_window_0_6,Inter_H_window_1_6,Inter_H_window_2_6,Inter_H_window_3_6,Inter_H_window_4_6,Inter_H_window_5_6, |
Inter_H_window_0_7,Inter_H_window_1_7,Inter_H_window_2_7,Inter_H_window_3_7,Inter_H_window_4_7,Inter_H_window_5_7, |
Inter_H_window_0_8,Inter_H_window_1_8,Inter_H_window_2_8,Inter_H_window_3_8,Inter_H_window_4_8,Inter_H_window_5_8, |
Inter_V_window_0,Inter_V_window_1,Inter_V_window_2,Inter_V_window_3,Inter_V_window_4, |
Inter_V_window_5,Inter_V_window_6,Inter_V_window_7,Inter_V_window_8, |
Inter_bi_window_0,Inter_bi_window_1,Inter_bi_window_2,Inter_bi_window_3, |
|
LPE0_out,LPE1_out,LPE2_out,LPE3_out |
); |
input clk,reset_n; |
input [3:0] pos_FracL; |
input IsInterLuma; |
input [3:0] blk4x4_inter_calculate_counter; |
|
input [7:0] Inter_H_window_0_0,Inter_H_window_1_0,Inter_H_window_2_0,Inter_H_window_3_0,Inter_H_window_4_0,Inter_H_window_5_0; |
input [7:0] Inter_H_window_0_1,Inter_H_window_1_1,Inter_H_window_2_1,Inter_H_window_3_1,Inter_H_window_4_1,Inter_H_window_5_1; |
input [7:0] Inter_H_window_0_2,Inter_H_window_1_2,Inter_H_window_2_2,Inter_H_window_3_2,Inter_H_window_4_2,Inter_H_window_5_2; |
input [7:0] Inter_H_window_0_3,Inter_H_window_1_3,Inter_H_window_2_3,Inter_H_window_3_3,Inter_H_window_4_3,Inter_H_window_5_3; |
input [7:0] Inter_H_window_0_4,Inter_H_window_1_4,Inter_H_window_2_4,Inter_H_window_3_4,Inter_H_window_4_4,Inter_H_window_5_4; |
input [7:0] Inter_H_window_0_5,Inter_H_window_1_5,Inter_H_window_2_5,Inter_H_window_3_5,Inter_H_window_4_5,Inter_H_window_5_5; |
input [7:0] Inter_H_window_0_6,Inter_H_window_1_6,Inter_H_window_2_6,Inter_H_window_3_6,Inter_H_window_4_6,Inter_H_window_5_6; |
input [7:0] Inter_H_window_0_7,Inter_H_window_1_7,Inter_H_window_2_7,Inter_H_window_3_7,Inter_H_window_4_7,Inter_H_window_5_7; |
input [7:0] Inter_H_window_0_8,Inter_H_window_1_8,Inter_H_window_2_8,Inter_H_window_3_8,Inter_H_window_4_8,Inter_H_window_5_8; |
input [7:0] Inter_V_window_0,Inter_V_window_1,Inter_V_window_2,Inter_V_window_3,Inter_V_window_4; |
input [7:0] Inter_V_window_5,Inter_V_window_6,Inter_V_window_7,Inter_V_window_8; |
input [7:0] Inter_bi_window_0,Inter_bi_window_1,Inter_bi_window_2,Inter_bi_window_3; |
|
output [7:0] LPE0_out,LPE1_out,LPE2_out,LPE3_out; |
|
reg [7:0] LPE0_out,LPE1_out,LPE2_out,LPE3_out; |
|
reg [14:0] b0_raw_reg,b1_raw_reg,b2_raw_reg,b3_raw_reg,b4_raw_reg,b5_raw_reg,b6_raw_reg,b7_raw_reg,b8_raw_reg; |
reg [7:0] b0_reg,b1_reg,b2_reg,b3_reg; |
reg [7:0] h0_reg,h1_reg,h2_reg,h3_reg; |
//------------------------ |
//Vertical 6tap filter |
//------------------------ |
wire Is_V_jfqik; //Is_V_jfqik: whether read from original [7:0] integer pixels and round as +16 >> 5 or read from b_raw[14:0] and round as +512 >> 10 |
wire [14:0] V_6tapfilter0_A,V_6tapfilter0_B,V_6tapfilter0_C,V_6tapfilter0_D,V_6tapfilter0_E,V_6tapfilter0_F; |
wire [14:0] V_6tapfilter1_A,V_6tapfilter1_B,V_6tapfilter1_C,V_6tapfilter1_D,V_6tapfilter1_E,V_6tapfilter1_F; |
wire [14:0] V_6tapfilter2_A,V_6tapfilter2_B,V_6tapfilter2_C,V_6tapfilter2_D,V_6tapfilter2_E,V_6tapfilter2_F; |
wire [14:0] V_6tapfilter3_A,V_6tapfilter3_B,V_6tapfilter3_C,V_6tapfilter3_D,V_6tapfilter3_E,V_6tapfilter3_F; |
wire [7:0] V_6tapfilter0_round_out,V_6tapfilter1_round_out,V_6tapfilter2_round_out,V_6tapfilter3_round_out; |
filterV_6tap V_6tapfilter0 ( |
.A(V_6tapfilter0_A), |
.B(V_6tapfilter0_B), |
.C(V_6tapfilter0_C), |
.D(V_6tapfilter0_D), |
.E(V_6tapfilter0_E), |
.F(V_6tapfilter0_F), |
.Is_jfqik(Is_V_jfqik), |
.round_out(V_6tapfilter0_round_out) |
); |
filterV_6tap V_6tapfilter1 ( |
.A(V_6tapfilter1_A), |
.B(V_6tapfilter1_B), |
.C(V_6tapfilter1_C), |
.D(V_6tapfilter1_D), |
.E(V_6tapfilter1_E), |
.F(V_6tapfilter1_F), |
.Is_jfqik(Is_V_jfqik), |
.round_out(V_6tapfilter1_round_out) |
); |
filterV_6tap V_6tapfilter2 ( |
.A(V_6tapfilter2_A), |
.B(V_6tapfilter2_B), |
.C(V_6tapfilter2_C), |
.D(V_6tapfilter2_D), |
.E(V_6tapfilter2_E), |
.F(V_6tapfilter2_F), |
.Is_jfqik(Is_V_jfqik), |
.round_out(V_6tapfilter2_round_out) |
); |
filterV_6tap V_6tapfilter3 ( |
.A(V_6tapfilter3_A), |
.B(V_6tapfilter3_B), |
.C(V_6tapfilter3_C), |
.D(V_6tapfilter3_D), |
.E(V_6tapfilter3_E), |
.F(V_6tapfilter3_F), |
.Is_jfqik(Is_V_jfqik), |
.round_out(V_6tapfilter3_round_out) |
); |
assign Is_V_jfqik = ( |
(pos_FracL == `pos_j && ( |
blk4x4_inter_calculate_counter == 4'd4 || blk4x4_inter_calculate_counter == 4'd3 || |
blk4x4_inter_calculate_counter == 4'd2 || blk4x4_inter_calculate_counter == 4'd1)) || |
((pos_FracL == `pos_f || pos_FracL == `pos_q) && ( |
blk4x4_inter_calculate_counter == 4'd4 || blk4x4_inter_calculate_counter == 4'd3 || |
blk4x4_inter_calculate_counter == 4'd2 || blk4x4_inter_calculate_counter == 4'd1)) || |
((pos_FracL == `pos_i || pos_FracL == `pos_k) && ( |
blk4x4_inter_calculate_counter == 4'd7 || blk4x4_inter_calculate_counter == 4'd5 || |
blk4x4_inter_calculate_counter == 4'd3 || blk4x4_inter_calculate_counter == 4'd1)))? 1'b1:1'b0; |
|
assign V_6tapfilter0_A = (Is_V_jfqik)? b0_raw_reg:{7'b0,Inter_V_window_0}; |
assign V_6tapfilter0_B = (Is_V_jfqik)? b1_raw_reg:{7'b0,Inter_V_window_1}; |
assign V_6tapfilter0_C = (Is_V_jfqik)? b2_raw_reg:{7'b0,Inter_V_window_2}; |
assign V_6tapfilter0_D = (Is_V_jfqik)? b3_raw_reg:{7'b0,Inter_V_window_3}; |
assign V_6tapfilter0_E = (Is_V_jfqik)? b4_raw_reg:{7'b0,Inter_V_window_4}; |
assign V_6tapfilter0_F = (Is_V_jfqik)? b5_raw_reg:{7'b0,Inter_V_window_5}; |
|
assign V_6tapfilter1_A = (Is_V_jfqik)? b1_raw_reg:{7'b0,Inter_V_window_1}; |
assign V_6tapfilter1_B = (Is_V_jfqik)? b2_raw_reg:{7'b0,Inter_V_window_2}; |
assign V_6tapfilter1_C = (Is_V_jfqik)? b3_raw_reg:{7'b0,Inter_V_window_3}; |
assign V_6tapfilter1_D = (Is_V_jfqik)? b4_raw_reg:{7'b0,Inter_V_window_4}; |
assign V_6tapfilter1_E = (Is_V_jfqik)? b5_raw_reg:{7'b0,Inter_V_window_5}; |
assign V_6tapfilter1_F = (Is_V_jfqik)? b6_raw_reg:{7'b0,Inter_V_window_6}; |
|
assign V_6tapfilter2_A = (Is_V_jfqik)? b2_raw_reg:{7'b0,Inter_V_window_2}; |
assign V_6tapfilter2_B = (Is_V_jfqik)? b3_raw_reg:{7'b0,Inter_V_window_3}; |
assign V_6tapfilter2_C = (Is_V_jfqik)? b4_raw_reg:{7'b0,Inter_V_window_4}; |
assign V_6tapfilter2_D = (Is_V_jfqik)? b5_raw_reg:{7'b0,Inter_V_window_5}; |
assign V_6tapfilter2_E = (Is_V_jfqik)? b6_raw_reg:{7'b0,Inter_V_window_6}; |
assign V_6tapfilter2_F = (Is_V_jfqik)? b7_raw_reg:{7'b0,Inter_V_window_7}; |
|
assign V_6tapfilter3_A = (Is_V_jfqik)? b3_raw_reg:{7'b0,Inter_V_window_3}; |
assign V_6tapfilter3_B = (Is_V_jfqik)? b4_raw_reg:{7'b0,Inter_V_window_4}; |
assign V_6tapfilter3_C = (Is_V_jfqik)? b5_raw_reg:{7'b0,Inter_V_window_5}; |
assign V_6tapfilter3_D = (Is_V_jfqik)? b6_raw_reg:{7'b0,Inter_V_window_6}; |
assign V_6tapfilter3_E = (Is_V_jfqik)? b7_raw_reg:{7'b0,Inter_V_window_7}; |
assign V_6tapfilter3_F = (Is_V_jfqik)? b8_raw_reg:{7'b0,Inter_V_window_8}; |
|
//------------------------ |
//Horizontal 6tap filter |
//------------------------ |
wire H_need_round; |
wire [14:0] H_6tapfilter0_raw_out; |
wire [14:0] H_6tapfilter1_raw_out; |
wire [14:0] H_6tapfilter2_raw_out; |
wire [14:0] H_6tapfilter3_raw_out; |
wire [14:0] H_6tapfilter4_raw_out; |
wire [14:0] H_6tapfilter5_raw_out; |
wire [14:0] H_6tapfilter6_raw_out; |
wire [14:0] H_6tapfilter7_raw_out; |
wire [14:0] H_6tapfilter8_raw_out; |
wire [7:0] H_6tapfilter0_round_out; |
wire [7:0] H_6tapfilter1_round_out; |
wire [7:0] H_6tapfilter2_round_out; |
wire [7:0] H_6tapfilter3_round_out; |
wire [7:0] H_6tapfilter4_round_out; |
wire [7:0] H_6tapfilter5_round_out; |
wire [7:0] H_6tapfilter6_round_out; |
wire [7:0] H_6tapfilter7_round_out; |
wire [7:0] H_6tapfilter8_round_out; |
|
assign H_need_round = (blk4x4_inter_calculate_counter != 0 && pos_FracL != `pos_Int && pos_FracL != `pos_i |
&& pos_FracL != `pos_j && pos_FracL != `pos_k && pos_FracL != `pos_d && pos_FracL != `pos_n); |
|
filterH_6tap H_6tapfilter0 ( |
.A(Inter_H_window_0_0), |
.B(Inter_H_window_1_0), |
.C(Inter_H_window_2_0), |
.D(Inter_H_window_3_0), |
.E(Inter_H_window_4_0), |
.F(Inter_H_window_5_0), |
.H_need_round(1'b0), |
.raw_out(H_6tapfilter0_raw_out), |
.round_out(H_6tapfilter0_round_out) |
); |
filterH_6tap H_6tapfilter1 ( |
.A(Inter_H_window_0_1), |
.B(Inter_H_window_1_1), |
.C(Inter_H_window_2_1), |
.D(Inter_H_window_3_1), |
.E(Inter_H_window_4_1), |
.F(Inter_H_window_5_1), |
.H_need_round(1'b0), |
.raw_out(H_6tapfilter1_raw_out), |
.round_out(H_6tapfilter1_round_out) |
); |
filterH_6tap H_6tapfilter2 ( |
.A(Inter_H_window_0_2), |
.B(Inter_H_window_1_2), |
.C(Inter_H_window_2_2), |
.D(Inter_H_window_3_2), |
.E(Inter_H_window_4_2), |
.F(Inter_H_window_5_2), |
.H_need_round(H_need_round), |
.raw_out(H_6tapfilter2_raw_out), |
.round_out(H_6tapfilter2_round_out) |
); |
filterH_6tap H_6tapfilter3 ( |
.A(Inter_H_window_0_3), |
.B(Inter_H_window_1_3), |
.C(Inter_H_window_2_3), |
.D(Inter_H_window_3_3), |
.E(Inter_H_window_4_3), |
.F(Inter_H_window_5_3), |
.H_need_round(H_need_round), |
.raw_out(H_6tapfilter3_raw_out), |
.round_out(H_6tapfilter3_round_out) |
); |
filterH_6tap H_6tapfilter4 ( |
.A(Inter_H_window_0_4), |
.B(Inter_H_window_1_4), |
.C(Inter_H_window_2_4), |
.D(Inter_H_window_3_4), |
.E(Inter_H_window_4_4), |
.F(Inter_H_window_5_4), |
.H_need_round(H_need_round), |
.raw_out(H_6tapfilter4_raw_out), |
.round_out(H_6tapfilter4_round_out) |
); |
filterH_6tap H_6tapfilter5 ( |
.A(Inter_H_window_0_5), |
.B(Inter_H_window_1_5), |
.C(Inter_H_window_2_5), |
.D(Inter_H_window_3_5), |
.E(Inter_H_window_4_5), |
.F(Inter_H_window_5_5), |
.H_need_round(H_need_round), |
.raw_out(H_6tapfilter5_raw_out), |
.round_out(H_6tapfilter5_round_out) |
); |
filterH_6tap H_6tapfilter6 ( |
.A(Inter_H_window_0_6), |
.B(Inter_H_window_1_6), |
.C(Inter_H_window_2_6), |
.D(Inter_H_window_3_6), |
.E(Inter_H_window_4_6), |
.F(Inter_H_window_5_6), |
.H_need_round(H_need_round), |
.raw_out(H_6tapfilter6_raw_out), |
.round_out(H_6tapfilter6_round_out) |
); |
filterH_6tap H_6tapfilter7 ( |
.A(Inter_H_window_0_7), |
.B(Inter_H_window_1_7), |
.C(Inter_H_window_2_7), |
.D(Inter_H_window_3_7), |
.E(Inter_H_window_4_7), |
.F(Inter_H_window_5_7), |
.H_need_round(1'b0), |
.raw_out(H_6tapfilter7_raw_out), |
.round_out(H_6tapfilter7_round_out) |
); |
filterH_6tap H_6tapfilter8 ( |
.A(Inter_H_window_0_8), |
.B(Inter_H_window_1_8), |
.C(Inter_H_window_2_8), |
.D(Inter_H_window_3_8), |
.E(Inter_H_window_4_8), |
.F(Inter_H_window_5_8), |
.H_need_round(1'b0), |
.raw_out(H_6tapfilter8_raw_out), |
.round_out(H_6tapfilter8_round_out) |
); |
|
//-------------------- |
//bilinear filter |
//-------------------- |
reg [7:0] bilinear0_A,bilinear0_B; |
reg [7:0] bilinear1_A,bilinear1_B; |
reg [7:0] bilinear2_A,bilinear2_B; |
reg [7:0] bilinear3_A,bilinear3_B; |
wire [7:0] bilinear0_out; |
wire [7:0] bilinear1_out; |
wire [7:0] bilinear2_out; |
wire [7:0] bilinear3_out; |
bilinear bilinear0 ( |
.A(bilinear0_A), |
.B(bilinear0_B), |
.bilinear_out(bilinear0_out) |
); |
bilinear bilinear1 ( |
.A(bilinear1_A), |
.B(bilinear1_B), |
.bilinear_out(bilinear1_out) |
); |
bilinear bilinear2 ( |
.A(bilinear2_A), |
.B(bilinear2_B), |
.bilinear_out(bilinear2_out) |
); |
bilinear bilinear3 ( |
.A(bilinear3_A), |
.B(bilinear3_B), |
.bilinear_out(bilinear3_out) |
); |
always @ (IsInterLuma or pos_FracL or blk4x4_inter_calculate_counter |
or Inter_bi_window_0 or Inter_bi_window_1 or Inter_bi_window_2 or Inter_bi_window_3 |
or H_6tapfilter2_round_out or H_6tapfilter3_round_out or H_6tapfilter4_round_out or H_6tapfilter5_round_out |
or V_6tapfilter0_round_out or V_6tapfilter1_round_out or V_6tapfilter2_round_out or V_6tapfilter3_round_out |
or b0_reg or b1_reg or b2_reg or b3_reg or h0_reg or h1_reg or h2_reg or h3_reg) |
if (IsInterLuma) |
case ({pos_FracL}) |
`pos_a,`pos_c: |
if (blk4x4_inter_calculate_counter != 4'd0) |
begin |
bilinear0_A <= Inter_bi_window_0; bilinear0_B <= H_6tapfilter2_round_out; |
bilinear1_A <= Inter_bi_window_1; bilinear1_B <= H_6tapfilter3_round_out; |
bilinear2_A <= Inter_bi_window_2; bilinear2_B <= H_6tapfilter4_round_out; |
bilinear3_A <= Inter_bi_window_3; bilinear3_B <= H_6tapfilter5_round_out; |
end |
else |
begin |
bilinear0_A <= 0; bilinear0_B <= 0; bilinear1_A <= 0; bilinear1_B <= 0; |
bilinear2_A <= 0; bilinear2_B <= 0; bilinear3_A <= 0; bilinear3_B <= 0; |
end |
`pos_d,`pos_n: |
if (blk4x4_inter_calculate_counter != 4'd0) |
begin |
bilinear0_A <= Inter_bi_window_0; bilinear0_B <= V_6tapfilter0_round_out; |
bilinear1_A <= Inter_bi_window_1; bilinear1_B <= V_6tapfilter1_round_out; |
bilinear2_A <= Inter_bi_window_2; bilinear2_B <= V_6tapfilter2_round_out; |
bilinear3_A <= Inter_bi_window_3; bilinear3_B <= V_6tapfilter3_round_out; |
end |
else |
begin |
bilinear0_A <= 0; bilinear0_B <= 0; bilinear1_A <= 0; bilinear1_B <= 0; |
bilinear2_A <= 0; bilinear2_B <= 0; bilinear3_A <= 0; bilinear3_B <= 0; |
end |
`pos_e,`pos_g,`pos_p,`pos_r: |
if (blk4x4_inter_calculate_counter != 4'd0) |
begin |
bilinear0_A <= H_6tapfilter2_round_out; bilinear0_B <= V_6tapfilter0_round_out; |
bilinear1_A <= H_6tapfilter3_round_out; bilinear1_B <= V_6tapfilter1_round_out; |
bilinear2_A <= H_6tapfilter4_round_out; bilinear2_B <= V_6tapfilter2_round_out; |
bilinear3_A <= H_6tapfilter5_round_out; bilinear3_B <= V_6tapfilter3_round_out; |
end |
else |
begin |
bilinear0_A <= 0; bilinear0_B <= 0; bilinear1_A <= 0; bilinear1_B <= 0; |
bilinear2_A <= 0; bilinear2_B <= 0; bilinear3_A <= 0; bilinear3_B <= 0; |
end |
`pos_i,`pos_k: |
if (blk4x4_inter_calculate_counter == 4'd7 || blk4x4_inter_calculate_counter == 4'd5 || |
blk4x4_inter_calculate_counter == 4'd3 || blk4x4_inter_calculate_counter == 4'd1) |
begin |
bilinear0_A <= h0_reg; bilinear0_B <= V_6tapfilter0_round_out; |
bilinear1_A <= h1_reg; bilinear1_B <= V_6tapfilter1_round_out; |
bilinear2_A <= h2_reg; bilinear2_B <= V_6tapfilter2_round_out; |
bilinear3_A <= h3_reg; bilinear3_B <= V_6tapfilter3_round_out; |
end |
else |
begin |
bilinear0_A <= 0; bilinear0_B <= 0; bilinear1_A <= 0; bilinear1_B <= 0; |
bilinear2_A <= 0; bilinear2_B <= 0; bilinear3_A <= 0; bilinear3_B <= 0; |
end |
`pos_f,`pos_q: |
if (blk4x4_inter_calculate_counter != 4'd5 && blk4x4_inter_calculate_counter != 4'd0) |
begin |
bilinear0_A <= b0_reg; bilinear0_B <= V_6tapfilter0_round_out; |
bilinear1_A <= b1_reg; bilinear1_B <= V_6tapfilter1_round_out; |
bilinear2_A <= b2_reg; bilinear2_B <= V_6tapfilter2_round_out; |
bilinear3_A <= b3_reg; bilinear3_B <= V_6tapfilter3_round_out; |
end |
else |
begin |
bilinear0_A <= 0; bilinear0_B <= 0; bilinear1_A <= 0; bilinear1_B <= 0; |
bilinear2_A <= 0; bilinear2_B <= 0; bilinear3_A <= 0; bilinear3_B <= 0; |
end |
default: |
begin |
bilinear0_A <= 0; bilinear0_B <= 0; bilinear1_A <= 0; bilinear1_B <= 0; |
bilinear2_A <= 0; bilinear2_B <= 0; bilinear3_A <= 0; bilinear3_B <= 0; |
end |
endcase |
else |
begin |
bilinear0_A <= 0; bilinear0_B <= 0; bilinear1_A <= 0; bilinear1_B <= 0; |
bilinear2_A <= 0; bilinear2_B <= 0; bilinear3_A <= 0; bilinear3_B <= 0; |
end |
|
//------------------------------------------------------------------------------------------ |
//only "b","h" and "j" of half-pel positions need to be stored to predict quater-pel samples |
//------------------------------------------------------------------------------------------ |
|
//b0_raw_reg0 ~ b8_raw_reg:update after j/f/q/i/k horizontal filtering |
wire b_raw_reg_ena; |
assign b_raw_reg_ena = (IsInterLuma && |
((pos_FracL == `pos_j && blk4x4_inter_calculate_counter != 4'd1 && blk4x4_inter_calculate_counter != 4'd0) || |
((pos_FracL == `pos_f || pos_FracL == `pos_q) && (blk4x4_inter_calculate_counter == 4'd5 || |
blk4x4_inter_calculate_counter == 4'd4 || |
blk4x4_inter_calculate_counter == 4'd3 || |
blk4x4_inter_calculate_counter == 4'd2)) || |
((pos_FracL == `pos_i || pos_FracL == `pos_k) && (blk4x4_inter_calculate_counter == 4'd8 || |
blk4x4_inter_calculate_counter == 4'd6 || |
blk4x4_inter_calculate_counter == 4'd4 || |
blk4x4_inter_calculate_counter == 4'd2)))); |
|
always @ (posedge clk) |
if (reset_n == 1'b0) |
begin |
b0_raw_reg <= 0; b1_raw_reg <= 0; b2_raw_reg <= 0; b3_raw_reg <= 0; b4_raw_reg <= 0; |
b5_raw_reg <= 0; b6_raw_reg <= 0; b7_raw_reg <= 0; b8_raw_reg <= 0; |
end |
else if (b_raw_reg_ena) |
begin |
b0_raw_reg <= H_6tapfilter0_raw_out;b1_raw_reg <= H_6tapfilter1_raw_out;b2_raw_reg <= H_6tapfilter2_raw_out; |
b3_raw_reg <= H_6tapfilter3_raw_out;b4_raw_reg <= H_6tapfilter4_raw_out;b5_raw_reg <= H_6tapfilter5_raw_out; |
b6_raw_reg <= H_6tapfilter6_raw_out;b7_raw_reg <= H_6tapfilter7_raw_out;b8_raw_reg <= H_6tapfilter8_raw_out; |
end |
|
//b0_reg ~ b3_reg:update for decoding f,q |
//Note:position q needs "b" of next line |
wire b_reg_ena; |
assign b_reg_ena = (IsInterLuma && ((pos_FracL == `pos_f || pos_FracL == `pos_q) && (blk4x4_inter_calculate_counter == 4'd5 || |
blk4x4_inter_calculate_counter == 4'd4 || blk4x4_inter_calculate_counter == 4'd3 || blk4x4_inter_calculate_counter == 4'd2))); |
|
always @ (posedge clk) |
if (reset_n == 1'b0) |
begin |
b0_reg <= 0; b1_reg <= 0; b2_reg <= 0; b3_reg <= 0; |
end |
else if (b_reg_ena) |
begin |
if (pos_FracL == `pos_q) |
begin |
b0_reg <= H_6tapfilter3_round_out; b1_reg <= H_6tapfilter4_round_out; |
b2_reg <= H_6tapfilter5_round_out; b3_reg <= H_6tapfilter6_round_out; |
end |
else |
begin |
b0_reg <= H_6tapfilter2_round_out; b1_reg <= H_6tapfilter3_round_out; |
b2_reg <= H_6tapfilter4_round_out; b3_reg <= H_6tapfilter5_round_out; |
end |
end |
|
//h0_reg ~ h3_reg:update for decoding i,k |
wire h_reg_ena; |
assign h_reg_ena = (IsInterLuma && ((pos_FracL == `pos_i || pos_FracL == `pos_k) && (blk4x4_inter_calculate_counter == 4'd8 || |
blk4x4_inter_calculate_counter == 4'd6 || blk4x4_inter_calculate_counter == 4'd4 || blk4x4_inter_calculate_counter == 4'd2))); |
|
always @ (posedge clk) |
if (reset_n == 1'b0) |
begin |
h0_reg <= 0; h1_reg <= 0; h2_reg <= 0; h3_reg <= 0; |
end |
else if (h_reg_ena) |
begin |
h0_reg <= V_6tapfilter0_round_out; h1_reg <= V_6tapfilter1_round_out; |
h2_reg <= V_6tapfilter2_round_out; h3_reg <= V_6tapfilter3_round_out; |
end |
//------------------------------------------------------------------------------------------ |
//LPE output |
//------------------------------------------------------------------------------------------ |
always @ (IsInterLuma or pos_FracL or blk4x4_inter_calculate_counter |
or V_6tapfilter0_round_out or V_6tapfilter1_round_out or V_6tapfilter2_round_out or V_6tapfilter3_round_out |
or H_6tapfilter2_round_out or H_6tapfilter3_round_out or H_6tapfilter4_round_out or H_6tapfilter5_round_out |
or bilinear0_out or bilinear1_out or bilinear2_out or bilinear3_out) |
if (IsInterLuma) |
case (pos_FracL) |
//pos_Int: directly bypassed by Inter_pix_copy0 ~ Inter_pix_copy3 |
`pos_b: |
if (blk4x4_inter_calculate_counter != 0) |
begin |
LPE0_out <= H_6tapfilter2_round_out; LPE1_out <= H_6tapfilter3_round_out; |
LPE2_out <= H_6tapfilter4_round_out; LPE3_out <= H_6tapfilter5_round_out; |
end |
else |
begin LPE0_out <= 0; LPE1_out <= 0;LPE2_out <= 0; LPE3_out <= 0;end |
`pos_h: |
if (blk4x4_inter_calculate_counter != 0) |
begin |
LPE0_out <= V_6tapfilter0_round_out; LPE1_out <= V_6tapfilter1_round_out; |
LPE2_out <= V_6tapfilter2_round_out; LPE3_out <= V_6tapfilter3_round_out; |
end |
else |
begin LPE0_out <= 0; LPE1_out <= 0;LPE2_out <= 0; LPE3_out <= 0;end |
`pos_j: |
if (blk4x4_inter_calculate_counter != 4'd5 && blk4x4_inter_calculate_counter != 0) |
begin |
LPE0_out <= V_6tapfilter0_round_out; LPE1_out <= V_6tapfilter1_round_out; |
LPE2_out <= V_6tapfilter2_round_out; LPE3_out <= V_6tapfilter3_round_out; |
end |
else |
begin LPE0_out <= 0; LPE1_out <= 0;LPE2_out <= 0; LPE3_out <= 0;end |
`pos_a,`pos_c,`pos_d,`pos_e,`pos_g,`pos_n,`pos_p,`pos_r,`pos_f,`pos_q: |
if (blk4x4_inter_calculate_counter == 4'd4 || blk4x4_inter_calculate_counter == 4'd3 || |
blk4x4_inter_calculate_counter == 4'd2 || blk4x4_inter_calculate_counter == 4'd1) |
begin |
LPE0_out <= bilinear0_out; LPE1_out <= bilinear1_out; |
LPE2_out <= bilinear2_out; LPE3_out <= bilinear3_out; |
end |
else |
begin LPE0_out <= 0; LPE1_out <= 0;LPE2_out <= 0; LPE3_out <= 0;end |
`pos_i,`pos_k: |
if (blk4x4_inter_calculate_counter == 4'd7 || blk4x4_inter_calculate_counter == 4'd5 || |
blk4x4_inter_calculate_counter == 4'd3 || blk4x4_inter_calculate_counter == 4'd1) |
begin |
LPE0_out <= bilinear0_out; LPE1_out <= bilinear1_out; |
LPE2_out <= bilinear2_out; LPE3_out <= bilinear3_out; |
end |
else |
begin LPE0_out <= 0; LPE1_out <= 0;LPE2_out <= 0; LPE3_out <= 0;end |
default: |
begin LPE0_out <= 0; LPE1_out <= 0;LPE2_out <= 0; LPE3_out <= 0;end |
endcase |
else |
begin LPE0_out <= 0; LPE1_out <= 0;LPE2_out <= 0; LPE3_out <= 0;end |
|
endmodule |
|
module filterH_6tap(A,B,C,D,E,F,H_need_round,raw_out,round_out); |
input [7:0] A,B,C,D,E,F; |
input H_need_round; |
output [14:0] raw_out; //always output |
output [7:0] round_out; |
|
wire [8:0] sum_AF; |
wire [8:0] sum_BE; |
wire [8:0] sum_CD; |
wire [10:0] sum_4CD; |
wire [11:0] sum_1; |
wire [12:0] sum_2; |
wire [13:0] sum_3; |
wire [14:0] sum_round; |
wire [9:0] round_tmp; |
|
assign sum_AF = A + F; |
assign sum_BE = B + E; |
assign sum_CD = C + D; |
assign sum_4CD = {sum_CD,2'b0}; |
assign sum_1 = {1'b0,sum_4CD} + {3'b111,~sum_BE} + 1; |
assign sum_2 = {4'b0,sum_AF} + {sum_1[11],sum_1}; |
assign sum_3 = {sum_1,2'b0}; |
assign raw_out = {{2{sum_2[12]}},sum_2} + {sum_3[13],sum_3}; |
//round |
assign sum_round = (H_need_round)? (raw_out + 16):0; |
assign round_tmp = (H_need_round)? sum_round[14:5]:0; |
assign round_out = (round_tmp[9])? 8'd0:((round_tmp[8])? 8'd255:round_tmp[7:0]); |
endmodule |
|
module filterV_6tap(A,B,C,D,E,F,Is_jfqik,round_out); |
input [14:0] A,B,C,D,E,F; |
input Is_jfqik; |
output [7:0] round_out; |
|
wire [15:0] sum_AF; |
wire [15:0] sum_BE; |
wire [15:0] sum_CD; |
wire [17:0] sum_4CD; |
wire [17:0] sum_1; |
wire [17:0] sum_2; |
wire [19:0] sum_3; |
wire [19:0] raw_out; |
|
wire [19:0] sum_round; |
wire [9:0] round_tmp; |
|
assign sum_AF = {A[14],A} + {F[14],F}; |
assign sum_BE = {B[14],B} + {E[14],E}; |
assign sum_CD = {C[14],C} + {D[14],D}; |
assign sum_4CD = {sum_CD,2'b0}; |
assign sum_1 = sum_4CD + {~sum_BE[15],~sum_BE[15],~sum_BE} + 1; |
assign sum_2 = {{2{sum_AF[15]}},sum_AF} + sum_1; |
assign sum_3 = {sum_1,2'b0}; |
assign raw_out = {{2{sum_2[17]}},sum_2} + sum_3; |
//round |
assign sum_round = (Is_jfqik)? (raw_out + 512):(raw_out + 16); |
assign round_tmp = (Is_jfqik)? sum_round[19:10]:sum_round[14:5]; |
assign round_out = (round_tmp[9])? 8'd0:((round_tmp[8])? 8'd255:round_tmp[7:0]); |
endmodule |
|
module bilinear (A,B,bilinear_out); |
input [7:0] A,B; |
output [7:0] bilinear_out; |
wire [8:0] sum_AB; |
|
assign sum_AB = A + B + 1; //here A and B should NOT extend as {A[7],A} |
assign bilinear_out = sum_AB[8:1]; |
endmodule |
|
|
|
/trunk/src/DF_reg_ctrl.v
0,0 → 1,335
//-------------------------------------------------------------------------------------------------- |
// Design : nova |
// Author(s) : Ke Xu |
// Email : eexuke@yahoo.com |
// File : DF_reg_ctrl.v |
// Generated : Nov 27,2005 |
// Copyright (C) 2008 Ke Xu |
//------------------------------------------------------------------------------------------------- |
// Description |
// buffer buf0 ~ buf3 & transpose reg t0 ~ t1 control |
//------------------------------------------------------------------------------------------------- |
|
// synopsys translate_off |
`include "timescale.v" |
// synopsys translate_on |
`include "nova_defines.v" |
|
module DF_reg_ctrl (gclk_DF,reset_n,DF_edge_counter_MW,one_edge_counter_MW, |
mb_num_h_DF,mb_num_v_DF,q0_MW,q1_MW,q2_MW,q3_MW,p0_MW,p1_MW,p2_MW,p3_MW, |
buf0_0,buf0_1,buf0_2,buf0_3,buf1_0,buf1_1,buf1_2,buf1_3, |
buf2_0,buf2_1,buf2_2,buf2_3,buf3_0,buf3_1,buf3_2,buf3_3, |
t0_0,t0_1,t0_2,t0_3,t1_0,t1_1,t1_2,t1_3,t2_0,t2_1,t2_2,t2_3); |
input gclk_DF,reset_n; |
input [5:0] DF_edge_counter_MW; |
input [1:0] one_edge_counter_MW; |
input [3:0] mb_num_h_DF; |
input [3:0] mb_num_v_DF; |
input [7:0] q0_MW,q1_MW,q2_MW,q3_MW; |
input [7:0] p0_MW,p1_MW,p2_MW,p3_MW; |
|
output [31:0] buf0_0,buf0_1,buf0_2,buf0_3; |
output [31:0] buf1_0,buf1_1,buf1_2,buf1_3; |
output [31:0] buf2_0,buf2_1,buf2_2,buf2_3; |
output [31:0] buf3_0,buf3_1,buf3_2,buf3_3; |
output [31:0] t0_0,t0_1,t0_2,t0_3; |
output [31:0] t1_0,t1_1,t1_2,t1_3; |
output [31:0] t2_0,t2_1,t2_2,t2_3; |
|
reg [31:0] buf0_0,buf0_1,buf0_2,buf0_3; |
reg [31:0] buf1_0,buf1_1,buf1_2,buf1_3; |
reg [31:0] buf2_0,buf2_1,buf2_2,buf2_3; |
reg [31:0] buf3_0,buf3_1,buf3_2,buf3_3; |
reg [31:0] t0_0,t0_1,t0_2,t0_3; |
reg [31:0] t1_0,t1_1,t1_2,t1_3; |
reg [31:0] t2_0,t2_1,t2_2,t2_3; |
//------------------------------------------------------ |
//buf0 |
//------------------------------------------------------ |
wire buf0_no_transpose; //buf0 updated without transpose |
wire buf0_transpose; //buf0 updated after transpose |
assign buf0_no_transpose = ( |
DF_edge_counter_MW == 6'd0 || DF_edge_counter_MW == 6'd4 || DF_edge_counter_MW == 6'd6 || |
DF_edge_counter_MW == 6'd12 || DF_edge_counter_MW == 6'd16 || DF_edge_counter_MW == 6'd20 || |
DF_edge_counter_MW == 6'd22 || DF_edge_counter_MW == 6'd28 || DF_edge_counter_MW == 6'd32 || |
DF_edge_counter_MW == 6'd36 || DF_edge_counter_MW == 6'd40 || DF_edge_counter_MW == 6'd44); |
assign buf0_transpose = ( |
DF_edge_counter_MW == 6'd1 || DF_edge_counter_MW == 6'd5 || DF_edge_counter_MW == 6'd10 || |
DF_edge_counter_MW == 6'd14 || DF_edge_counter_MW == 6'd17 || DF_edge_counter_MW == 6'd26 || |
DF_edge_counter_MW == 6'd30 || DF_edge_counter_MW == 6'd33 || DF_edge_counter_MW == 6'd38 || |
DF_edge_counter_MW == 6'd41 || DF_edge_counter_MW == 6'd46); |
|
always @ (posedge gclk_DF or negedge reset_n) |
if (reset_n == 1'b0) |
begin |
buf0_0 <= 0; buf0_1 <= 0; buf0_2 <= 0; buf0_3 <= 0; |
end |
//no transpose update,always "q" position (right or down of the edge to be filtered) |
else if (buf0_no_transpose) |
case (one_edge_counter_MW) |
2'd0:buf0_0 <= {q3_MW,q2_MW,q1_MW,q0_MW}; |
2'd1:buf0_1 <= {q3_MW,q2_MW,q1_MW,q0_MW}; |
2'd2:buf0_2 <= {q3_MW,q2_MW,q1_MW,q0_MW}; |
2'd3:buf0_3 <= {q3_MW,q2_MW,q1_MW,q0_MW}; |
endcase |
//transpose update,always "p" position (left or up of the edge to be filtered) |
else if (buf0_transpose) |
case (one_edge_counter_MW) |
2'd0:begin buf0_0[7:0] <= p3_MW; buf0_1[7:0] <= p2_MW; |
buf0_2[7:0] <= p1_MW; buf0_3[7:0] <= p0_MW; end |
2'd1:begin buf0_0[15:8] <= p3_MW; buf0_1[15:8] <= p2_MW; |
buf0_2[15:8] <= p1_MW; buf0_3[15:8] <= p0_MW; end |
2'd2:begin buf0_0[23:16] <= p3_MW; buf0_1[23:16] <= p2_MW; |
buf0_2[23:16] <= p1_MW; buf0_3[23:16] <= p0_MW; end |
2'd3:begin buf0_0[31:24] <= p3_MW; buf0_1[31:24] <= p2_MW; |
buf0_2[31:24] <= p1_MW; buf0_3[31:24] <= p0_MW; end |
endcase |
//------------------------------------------------------ |
//buf1 |
//------------------------------------------------------ |
wire buf1_no_transpose; //buf1 updated without transpose |
wire buf1_transpose; //buf1 updated after transpose |
wire buf1_transpose_p; //buf1 transpose and buf1 stores "p" position pixels |
assign buf1_no_transpose = ( |
DF_edge_counter_MW == 6'd1 || DF_edge_counter_MW == 6'd8 || DF_edge_counter_MW == 6'd13 || |
DF_edge_counter_MW == 6'd17 || DF_edge_counter_MW == 6'd24 || DF_edge_counter_MW == 6'd29 || |
DF_edge_counter_MW == 6'd37 || DF_edge_counter_MW == 6'd45); |
assign buf1_transpose = ( |
DF_edge_counter_MW == 6'd6 || DF_edge_counter_MW == 6'd10 || DF_edge_counter_MW == 6'd22 || |
DF_edge_counter_MW == 6'd26 || DF_edge_counter_MW == 6'd33 || DF_edge_counter_MW == 6'd41); |
assign buf1_transpose_p = (DF_edge_counter_MW == 6'd6 || DF_edge_counter_MW == 6'd9 |
|| DF_edge_counter_MW == 6'd22); |
always @ (posedge gclk_DF or negedge reset_n) |
if (reset_n == 1'b0) |
begin |
buf1_0 <= 0; buf1_1 <= 0; buf1_2 <= 0; buf1_3 <= 0; |
end |
//no transpose update,always "q" position (right or down of the edge to be filtered) |
else if (buf1_no_transpose) |
case (one_edge_counter_MW) |
2'd0:buf1_0 <= {q3_MW,q2_MW,q1_MW,q0_MW}; |
2'd1:buf1_1 <= {q3_MW,q2_MW,q1_MW,q0_MW}; |
2'd2:buf1_2 <= {q3_MW,q2_MW,q1_MW,q0_MW}; |
2'd3:buf1_3 <= {q3_MW,q2_MW,q1_MW,q0_MW}; |
endcase |
//transpose update,"p":6/9/22,"q":10,26,33,41 |
else if (buf1_transpose) |
begin |
if (buf1_transpose_p) // edge 6,22 "p" |
case (one_edge_counter_MW) |
2'd0:begin buf1_0[7:0] <= p3_MW; buf1_1[7:0] <= p2_MW; |
buf1_2[7:0] <= p1_MW; buf1_3[7:0] <= p0_MW; end |
2'd1:begin buf1_0[15:8] <= p3_MW; buf1_1[15:8] <= p2_MW; |
buf1_2[15:8] <= p1_MW; buf1_3[15:8] <= p0_MW; end |
2'd2:begin buf1_0[23:16] <= p3_MW; buf1_1[23:16] <= p2_MW; |
buf1_2[23:16] <= p1_MW; buf1_3[23:16] <= p0_MW; end |
2'd3:begin buf1_0[31:24] <= p3_MW; buf1_1[31:24] <= p2_MW; |
buf1_2[31:24] <= p1_MW; buf1_3[31:24] <= p0_MW; end |
endcase |
else //edge 10,26,33,41 "q" |
case (one_edge_counter_MW) |
2'd0:begin buf1_0[7:0] <= q0_MW; buf1_1[7:0] <= q1_MW; |
buf1_2[7:0] <= q2_MW; buf1_3[7:0] <= q3_MW; end |
2'd1:begin buf1_0[15:8] <= q0_MW; buf1_1[15:8] <= q1_MW; |
buf1_2[15:8] <= q2_MW; buf1_3[15:8] <= q3_MW; end |
2'd2:begin buf1_0[23:16] <= q0_MW; buf1_1[23:16] <= q1_MW; |
buf1_2[23:16] <= q2_MW; buf1_3[23:16] <= q3_MW; end |
2'd3:begin buf1_0[31:24] <= q0_MW; buf1_1[31:24] <= q1_MW; |
buf1_2[31:24] <= q2_MW; buf1_3[31:24] <= q3_MW; end |
endcase |
end |
//------------------------------------------------------ |
//buf2 |
//------------------------------------------------------ |
wire buf2_no_transpose; //buf2 updated without transpose |
wire buf2_transpose; //buf2 updated after transpose |
wire buf2_transpose_p; //buf2 transpose and buf2 stores "p" position pixels |
assign buf2_no_transpose = ( |
DF_edge_counter_MW == 6'd2 || DF_edge_counter_MW == 6'd7 || DF_edge_counter_MW == 6'd18 || |
DF_edge_counter_MW == 6'd23 || DF_edge_counter_MW == 6'd34 || DF_edge_counter_MW == 6'd42); |
assign buf2_transpose = ( |
DF_edge_counter_MW == 6'd3 || DF_edge_counter_MW == 6'd11 || DF_edge_counter_MW == 6'd19 || |
DF_edge_counter_MW == 6'd21 || DF_edge_counter_MW == 6'd27 || DF_edge_counter_MW == 6'd30 || |
DF_edge_counter_MW == 6'd35 || DF_edge_counter_MW == 6'd38 || DF_edge_counter_MW == 6'd43 || |
DF_edge_counter_MW == 6'd46); |
assign buf2_transpose_p = (DF_edge_counter_MW == 6'd3 || DF_edge_counter_MW == 6'd11 |
|| DF_edge_counter_MW == 6'd19 || DF_edge_counter_MW == 6'd27 |
|| DF_edge_counter_MW == 6'd35 || DF_edge_counter_MW == 6'd43); |
always @ (posedge gclk_DF or negedge reset_n) |
if (reset_n == 1'b0) |
begin |
buf2_0 <= 0; buf2_1 <= 0; buf2_2 <= 0; buf2_3 <= 0; |
end |
//no transpose update,always "q" position (right or down of the edge to be filtered) |
else if (buf2_no_transpose) |
case (one_edge_counter_MW) |
2'd0:buf2_0 <= {q3_MW,q2_MW,q1_MW,q0_MW}; |
2'd1:buf2_1 <= {q3_MW,q2_MW,q1_MW,q0_MW}; |
2'd2:buf2_2 <= {q3_MW,q2_MW,q1_MW,q0_MW}; |
2'd3:buf2_3 <= {q3_MW,q2_MW,q1_MW,q0_MW}; |
endcase |
//transpose update,"p":3,11,19,27,35,43 "q":21,30,38,46 |
else if (buf2_transpose) |
begin |
if (buf2_transpose_p) //"p":3,11,19,27,35,43 |
case (one_edge_counter_MW) |
2'd0:begin buf2_0[7:0] <= p3_MW; buf2_1[7:0] <= p2_MW; |
buf2_2[7:0] <= p1_MW; buf2_3[7:0] <= p0_MW; end |
2'd1:begin buf2_0[15:8] <= p3_MW; buf2_1[15:8] <= p2_MW; |
buf2_2[15:8] <= p1_MW; buf2_3[15:8] <= p0_MW; end |
2'd2:begin buf2_0[23:16] <= p3_MW; buf2_1[23:16] <= p2_MW; |
buf2_2[23:16] <= p1_MW; buf2_3[23:16] <= p0_MW; end |
2'd3:begin buf2_0[31:24] <= p3_MW; buf2_1[31:24] <= p2_MW; |
buf2_2[31:24] <= p1_MW; buf2_3[31:24] <= p0_MW; end |
endcase |
else //"q":21,30,38,46 |
case (one_edge_counter_MW) |
2'd0:begin buf2_0[7:0] <= q0_MW; buf2_1[7:0] <= q1_MW; |
buf2_2[7:0] <= q2_MW; buf2_3[7:0] <= q3_MW; end |
2'd1:begin buf2_0[15:8] <= q0_MW; buf2_1[15:8] <= q1_MW; |
buf2_2[15:8] <= q2_MW; buf2_3[15:8] <= q3_MW; end |
2'd2:begin buf2_0[23:16] <= q0_MW; buf2_1[23:16] <= q1_MW; |
buf2_2[23:16] <= q2_MW; buf2_3[23:16] <= q3_MW; end |
2'd3:begin buf2_0[31:24] <= q0_MW; buf2_1[31:24] <= q1_MW; |
buf2_2[31:24] <= q2_MW; buf2_3[31:24] <= q3_MW; end |
endcase |
end |
//------------------------------------------------------ |
//buf3 |
//------------------------------------------------------ |
wire buf3_no_transpose; //buf3 updated without transpose |
wire buf3_transpose; //buf3 updated after transpose |
wire buf3_transpose_p; //buf3 transpose and buf1 stores "p" position pixels |
assign buf3_no_transpose = (DF_edge_counter_MW == 6'd3 || DF_edge_counter_MW == 6'd19); |
assign buf3_transpose = ( DF_edge_counter_MW == 6'd7 || |
DF_edge_counter_MW == 6'd11 || DF_edge_counter_MW == 6'd23 || DF_edge_counter_MW == 6'd27 || |
DF_edge_counter_MW == 6'd25 || DF_edge_counter_MW == 6'd35 || DF_edge_counter_MW == 6'd43); |
assign buf3_transpose_p = (DF_edge_counter_MW == 6'd7 || DF_edge_counter_MW == 6'd23); |
always @ (posedge gclk_DF or negedge reset_n) |
if (reset_n == 1'b0) |
begin |
buf3_0 <= 0; buf3_1 <= 0; buf3_2 <= 0; buf3_3 <= 0; |
end |
//no transpose update,always "q" position (right or down of the edge to be filtered) |
else if (buf3_no_transpose) |
case (one_edge_counter_MW) |
2'd0:buf3_0 <= {q3_MW,q2_MW,q1_MW,q0_MW}; |
2'd1:buf3_1 <= {q3_MW,q2_MW,q1_MW,q0_MW}; |
2'd2:buf3_2 <= {q3_MW,q2_MW,q1_MW,q0_MW}; |
2'd3:buf3_3 <= {q3_MW,q2_MW,q1_MW,q0_MW}; |
endcase |
//transpose update,"p":7,23 "q":11,25,27,35,43 |
else if (buf3_transpose) |
begin |
if (buf3_transpose_p) //"p":7,23 |
case (one_edge_counter_MW) |
2'd0:begin buf3_0[7:0] <= p3_MW; buf3_1[7:0] <= p2_MW; |
buf3_2[7:0] <= p1_MW; buf3_3[7:0] <= p0_MW; end |
2'd1:begin buf3_0[15:8] <= p3_MW; buf3_1[15:8] <= p2_MW; |
buf3_2[15:8] <= p1_MW; buf3_3[15:8] <= p0_MW; end |
2'd2:begin buf3_0[23:16] <= p3_MW; buf3_1[23:16] <= p2_MW; |
buf3_2[23:16] <= p1_MW; buf3_3[23:16] <= p0_MW; end |
2'd3:begin buf3_0[31:24] <= p3_MW; buf3_1[31:24] <= p2_MW; |
buf3_2[31:24] <= p1_MW; buf3_3[31:24] <= p0_MW; end |
endcase |
else //"q":11,25,35,43 |
case (one_edge_counter_MW) |
2'd0:begin buf3_0[7:0] <= q0_MW; buf3_1[7:0] <= q1_MW; |
buf3_2[7:0] <= q2_MW; buf3_3[7:0] <= q3_MW; end |
2'd1:begin buf3_0[15:8] <= q0_MW; buf3_1[15:8] <= q1_MW; |
buf3_2[15:8] <= q2_MW; buf3_3[15:8] <= q3_MW; end |
2'd2:begin buf3_0[23:16] <= q0_MW; buf3_1[23:16] <= q1_MW; |
buf3_2[23:16] <= q2_MW; buf3_3[23:16] <= q3_MW; end |
2'd3:begin buf3_0[31:24] <= q0_MW; buf3_1[31:24] <= q1_MW; |
buf3_2[31:24] <= q2_MW; buf3_3[31:24] <= q3_MW; end |
endcase |
end |
//------------------------------------------------------ |
//T0:always updated after transpose,always "p" position |
//------------------------------------------------------ |
wire t0_transpose; //t0 updated after transpose |
assign t0_transpose = ( |
DF_edge_counter_MW == 6'd4 || DF_edge_counter_MW == 6'd8 || DF_edge_counter_MW == 6'd12 || DF_edge_counter_MW == 6'd36 || |
DF_edge_counter_MW == 6'd44 || DF_edge_counter_MW == 6'd15 || DF_edge_counter_MW == 6'd20 || DF_edge_counter_MW == 6'd24 || |
DF_edge_counter_MW == 6'd28 || DF_edge_counter_MW == 6'd31 || DF_edge_counter_MW == 6'd39 || DF_edge_counter_MW == 6'd47); |
|
always @ (posedge gclk_DF or negedge reset_n) |
if (reset_n == 1'b0) |
begin |
t0_0 <= 0; t0_1 <= 0; t0_2 <= 0; t0_3 <= 0; |
end |
//always transpose update for "p" position |
else if (t0_transpose) |
case (one_edge_counter_MW) |
2'd0:begin t0_0[7:0] <= p3_MW; t0_1[7:0] <= p2_MW; |
t0_2[7:0] <= p1_MW; t0_3[7:0] <= p0_MW; end |
2'd1:begin t0_0[15:8] <= p3_MW; t0_1[15:8] <= p2_MW; |
t0_2[15:8] <= p1_MW; t0_3[15:8] <= p0_MW; end |
2'd2:begin t0_0[23:16] <= p3_MW; t0_1[23:16] <= p2_MW; |
t0_2[23:16] <= p1_MW; t0_3[23:16] <= p0_MW; end |
2'd3:begin t0_0[31:24] <= p3_MW; t0_1[31:24] <= p2_MW; |
t0_2[31:24] <= p1_MW; t0_3[31:24] <= p0_MW; end |
endcase |
//------------------------------------------------------ |
//T1:always updated after transpose |
//------------------------------------------------------ |
wire t1_transpose; //t1 updated after transpose |
wire t1_transpose_q; //t1 transpose and t1 stores "q" position pixels |
assign t1_transpose = ( |
DF_edge_counter_MW == 6'd13 || DF_edge_counter_MW == 6'd37 || DF_edge_counter_MW == 6'd45 || DF_edge_counter_MW == 6'd9 || |
DF_edge_counter_MW == 6'd21 || DF_edge_counter_MW == 6'd25 || DF_edge_counter_MW == 6'd29 || DF_edge_counter_MW == 6'd31 || |
DF_edge_counter_MW == 6'd39 || DF_edge_counter_MW == 6'd47); |
|
assign t1_transpose_q = (DF_edge_counter_MW == 6'd31 || DF_edge_counter_MW == 6'd39 || |
DF_edge_counter_MW == 6'd47); |
always @ (posedge gclk_DF or negedge reset_n) |
if (reset_n == 1'b0) |
begin |
t1_0 <= 0; t1_1 <= 0; t1_2 <= 0; t1_3 <= 0; |
end |
else if (t1_transpose && !t1_transpose_q) //t1 transpose "p" |
case (one_edge_counter_MW) |
2'd0:begin t1_0[7:0] <= p3_MW; t1_1[7:0] <= p2_MW; |
t1_2[7:0] <= p1_MW; t1_3[7:0] <= p0_MW; end |
2'd1:begin t1_0[15:8] <= p3_MW; t1_1[15:8] <= p2_MW; |
t1_2[15:8] <= p1_MW; t1_3[15:8] <= p0_MW; end |
2'd2:begin t1_0[23:16] <= p3_MW; t1_1[23:16] <= p2_MW; |
t1_2[23:16] <= p1_MW; t1_3[23:16] <= p0_MW; end |
2'd3:begin t1_0[31:24] <= p3_MW; t1_1[31:24] <= p2_MW; |
t1_2[31:24] <= p1_MW; t1_3[31:24] <= p0_MW; end |
endcase |
else if (t1_transpose) //t1 transpose "q" |
case (one_edge_counter_MW) |
2'd0:begin t1_0[7:0] <= q0_MW; t1_1[7:0] <= q1_MW; |
t1_2[7:0] <= q2_MW; t1_3[7:0] <= q3_MW; end |
2'd1:begin t1_0[15:8] <= q0_MW; t1_1[15:8] <= q1_MW; |
t1_2[15:8] <= q2_MW; t1_3[15:8] <= q3_MW; end |
2'd2:begin t1_0[23:16] <= q0_MW; t1_1[23:16] <= q1_MW; |
t1_2[23:16] <= q2_MW; t1_3[23:16] <= q3_MW; end |
2'd3:begin t1_0[31:24] <= q0_MW; t1_1[31:24] <= q1_MW; |
t1_2[31:24] <= q2_MW; t1_3[31:24] <= q3_MW; end |
endcase |
//-------------------------------------------------------------------- |
//T2:only used after filter edge 18/34/42 to update mbAddrB of left MB |
//-------------------------------------------------------------------- |
wire t2_wr; |
assign t2_wr = ((mb_num_h_DF != 0 && mb_num_v_DF != 4'd8) && |
(DF_edge_counter_MW == 6'd18 || DF_edge_counter_MW == 6'd34 || DF_edge_counter_MW == 6'd42)); |
always @ (posedge gclk_DF or negedge reset_n) |
if (reset_n == 1'b0) |
begin |
t2_0 <= 0; t2_1 <= 0; t2_2 <= 0; t2_3 <= 0; |
end |
else if (t2_wr) |
case (one_edge_counter_MW) |
2'd0:begin t2_0[7:0] <= p3_MW; t2_1[7:0] <= p2_MW; |
t2_2[7:0] <= p1_MW; t2_3[7:0] <= p0_MW; end |
2'd1:begin t2_0[15:8] <= p3_MW; t2_1[15:8] <= p2_MW; |
t2_2[15:8] <= p1_MW; t2_3[15:8] <= p0_MW; end |
2'd2:begin t2_0[23:16] <= p3_MW; t2_1[23:16] <= p2_MW; |
t2_2[23:16] <= p1_MW; t2_3[23:16] <= p0_MW; end |
2'd3:begin t2_0[31:24] <= p3_MW; t2_1[31:24] <= p2_MW; |
t2_2[31:24] <= p1_MW; t2_3[31:24] <= p0_MW; end |
endcase |
endmodule |
|
/trunk/src/DF_top.v
0,0 → 1,205
//-------------------------------------------------------------------------------------------------- |
// Design : nova |
// Author(s) : Ke Xu |
// Email : eexuke@yahoo.com |
// File : DF_top.v |
// Generated : Dec 30, 2005 |
// Copyright (C) 2008 Ke Xu |
//------------------------------------------------------------------------------------------------- |
// Description |
// Top module of deblocking filter |
//------------------------------------------------------------------------------------------------- |
|
// synopsys translate_off |
`include "timescale.v" |
// synopsys translate_on |
`include "nova_defines.v" |
|
module DF_top (clk,reset_n,gclk_DF,gclk_end_of_MB_DEC,gclk_DF_mbAddrA_RF,gclk_DF_mbAddrB_RAM, |
end_of_BS_DEC,disable_DF,mb_num_h,mb_num_v, |
bs_V0,bs_V1,bs_V2,bs_V3,bs_H0,bs_H1,bs_H2,bs_H3, |
QPy,QPc,slice_alpha_c0_offset_div2,slice_beta_offset_div2, |
blk4x4_sum_counter,blk4x4_rec_counter_2_raster_order,rec_DF_RAM_dout, |
blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out, |
|
DF_duration,end_of_MB_DF,DF_edge_counter_MR,one_edge_counter_MR, |
DF_mbAddrA_RF_rd,DF_mbAddrA_RF_wr,DF_mbAddrB_RAM_rd,DF_mbAddrB_RAM_wr, |
dis_frame_RAM_wr,dis_frame_RAM_wr_addr,dis_frame_RAM_din); |
input clk; |
input gclk_DF; |
input gclk_end_of_MB_DEC; |
input gclk_DF_mbAddrA_RF; |
input gclk_DF_mbAddrB_RAM; |
input reset_n; |
input end_of_BS_DEC; |
input disable_DF; |
input [3:0] mb_num_h; |
input [3:0] mb_num_v; |
input [11:0] bs_V0,bs_V1,bs_V2,bs_V3; |
input [11:0] bs_H0,bs_H1,bs_H2,bs_H3; |
input [5:0] QPy,QPc; |
input [3:0] slice_alpha_c0_offset_div2; |
input [3:0] slice_beta_offset_div2; |
input [31:0] rec_DF_RAM_dout; |
input [2:0] blk4x4_sum_counter; |
input [4:0] blk4x4_rec_counter_2_raster_order; |
input [7:0] blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out; |
|
output DF_duration; |
output end_of_MB_DF; |
output [5:0] DF_edge_counter_MR; |
output [1:0] one_edge_counter_MR; |
output DF_mbAddrA_RF_rd,DF_mbAddrA_RF_wr; |
output DF_mbAddrB_RAM_rd,DF_mbAddrB_RAM_wr; |
output dis_frame_RAM_wr; |
output [13:0] dis_frame_RAM_wr_addr; |
output [31:0] dis_frame_RAM_din; |
|
wire end_of_MB_DF; |
wire end_of_lastMB_DF; |
wire [3:0] mb_num_h_DF; |
wire [3:0] mb_num_v_DF; |
wire [5:0] DF_edge_counter_MR,DF_edge_counter_MW; |
wire [1:0] one_edge_counter_MR,one_edge_counter_MW; |
wire [2:0] bs_curr_MR,bs_curr_MW; |
wire [7:0] q0_MW,q1_MW,q2_MW,q3_MW; |
wire [7:0] p0_MW,p1_MW,p2_MW,p3_MW; |
wire [31:0] buf0_0,buf0_1,buf0_2,buf0_3; |
wire [31:0] buf1_0,buf1_1,buf1_2,buf1_3; |
wire [31:0] buf2_0,buf2_1,buf2_2,buf2_3; |
wire [31:0] buf3_0,buf3_1,buf3_2,buf3_3; |
wire [31:0] t0_0,t0_1,t0_2,t0_3; |
wire [31:0] t1_0,t1_1,t1_2,t1_3; |
wire [31:0] t2_0,t2_1,t2_2,t2_3; |
wire DF_mbAddrA_RF_rd; |
wire DF_mbAddrA_RF_wr; |
wire [4:0] DF_mbAddrA_RF_rd_addr; |
wire [4:0] DF_mbAddrA_RF_wr_addr; |
wire [31:0] DF_mbAddrA_RF_din; |
wire [31:0] DF_mbAddrA_RF_dout; |
wire DF_mbAddrB_RAM_rd; |
wire DF_mbAddrB_RAM_wr; |
wire [8:0] DF_mbAddrB_RAM_addr; |
wire [31:0] DF_mbAddrB_RAM_din; |
wire [31:0] DF_mbAddrB_RAM_dout; |
|
DF_pipeline DF_pipeline ( |
.clk(clk), |
.gclk_DF(gclk_DF), |
.gclk_end_of_MB_DEC(gclk_end_of_MB_DEC), |
.reset_n(reset_n), |
.disable_DF(disable_DF), |
.end_of_BS_DEC(end_of_BS_DEC), |
.end_of_MB_DF(end_of_MB_DF), |
.end_of_lastMB_DF(end_of_lastMB_DF), |
.bs_V0(bs_V0),.bs_V1(bs_V1),.bs_V2(bs_V2),.bs_V3(bs_V3), |
.bs_H0(bs_H0),.bs_H1(bs_H1),.bs_H2(bs_H2),.bs_H3(bs_H3), |
.QPy(QPy), |
.QPc(QPc), |
.slice_alpha_c0_offset_div2(slice_alpha_c0_offset_div2), |
.slice_beta_offset_div2(slice_beta_offset_div2), |
.DF_mbAddrA_RF_dout(DF_mbAddrA_RF_dout), |
.DF_mbAddrB_RAM_dout(DF_mbAddrB_RAM_dout), |
.rec_DF_RAM_dout(rec_DF_RAM_dout), |
.buf0_0(buf0_0),.buf0_1(buf0_1),.buf0_2(buf0_2),.buf0_3(buf0_3), |
.buf1_0(buf1_0),.buf1_1(buf1_1),.buf1_2(buf1_2),.buf1_3(buf1_3), |
.buf2_0(buf2_0),.buf2_1(buf2_1),.buf2_2(buf2_2),.buf2_3(buf2_3), |
.buf3_0(buf3_0),.buf3_1(buf3_1),.buf3_2(buf3_2),.buf3_3(buf3_3), |
|
.DF_duration(DF_duration), |
.DF_edge_counter_MR(DF_edge_counter_MR), |
.DF_edge_counter_MW(DF_edge_counter_MW), |
.one_edge_counter_MR(one_edge_counter_MR), |
.one_edge_counter_MW(one_edge_counter_MW), |
.bs_curr_MR(bs_curr_MR), |
.bs_curr_MW(bs_curr_MW), |
.q0_MW(q0_MW),.q1_MW(q1_MW),.q2_MW(q2_MW),.q3_MW(q3_MW), |
.p0_MW(p0_MW),.p1_MW(p1_MW),.p2_MW(p2_MW),.p3_MW(p3_MW) |
); |
DF_reg_ctrl DF_reg_ctrl ( |
.gclk_DF(gclk_DF), |
.reset_n(reset_n), |
.DF_edge_counter_MW(DF_edge_counter_MW), |
.one_edge_counter_MW(one_edge_counter_MW), |
.mb_num_h_DF(mb_num_h_DF), |
.mb_num_v_DF(mb_num_v_DF), |
|
.q0_MW(q0_MW),.q1_MW(q1_MW),.q2_MW(q2_MW),.q3_MW(q3_MW), |
.p0_MW(p0_MW),.p1_MW(p1_MW),.p2_MW(p2_MW),.p3_MW(p3_MW), |
.buf0_0(buf0_0),.buf0_1(buf0_1),.buf0_2(buf0_2),.buf0_3(buf0_3), |
.buf1_0(buf1_0),.buf1_1(buf1_1),.buf1_2(buf1_2),.buf1_3(buf1_3), |
.buf2_0(buf2_0),.buf2_1(buf2_1),.buf2_2(buf2_2),.buf2_3(buf2_3), |
.buf3_0(buf3_0),.buf3_1(buf3_1),.buf3_2(buf3_2),.buf3_3(buf3_3), |
.t0_0(t0_0),.t0_1(t0_1),.t0_2(t0_2),.t0_3(t0_3), |
.t1_0(t1_0),.t1_1(t1_1),.t1_2(t1_2),.t1_3(t1_3), |
.t2_0(t2_0),.t2_1(t2_1),.t2_2(t2_2),.t2_3(t2_3) |
); |
|
DF_mem_ctrl DF_mem_ctrl ( |
.clk(clk), |
.reset_n(reset_n), |
.gclk_end_of_MB_DEC(gclk_end_of_MB_DEC), |
.disable_DF(disable_DF), |
.mb_num_h(mb_num_h), |
.mb_num_v(mb_num_v), |
.bs_curr_MR(bs_curr_MR), |
.bs_curr_MW(bs_curr_MW), |
.blk4x4_sum_counter(blk4x4_sum_counter), |
.blk4x4_rec_counter_2_raster_order(blk4x4_rec_counter_2_raster_order), |
.DF_edge_counter_MR(DF_edge_counter_MR), |
.DF_edge_counter_MW(DF_edge_counter_MW), |
.one_edge_counter_MR(one_edge_counter_MR), |
.one_edge_counter_MW(one_edge_counter_MW), |
.blk4x4_sum_PE0_out(blk4x4_sum_PE0_out), |
.blk4x4_sum_PE1_out(blk4x4_sum_PE1_out), |
.blk4x4_sum_PE2_out(blk4x4_sum_PE2_out), |
.blk4x4_sum_PE3_out(blk4x4_sum_PE3_out), |
.q0_MW(q0_MW),.q1_MW(q1_MW),.q2_MW(q2_MW),.q3_MW(q3_MW), |
.p0_MW(p0_MW),.p1_MW(p1_MW),.p2_MW(p2_MW),.p3_MW(p3_MW), |
.buf0_0(buf0_0),.buf0_1(buf0_1),.buf0_2(buf0_2),.buf0_3(buf0_3), |
.buf2_0(buf2_0),.buf2_1(buf2_1),.buf2_2(buf2_2),.buf2_3(buf2_3), |
.buf3_0(buf3_0),.buf3_1(buf3_1),.buf3_2(buf3_2),.buf3_3(buf3_3), |
.t0_0(t0_0),.t0_1(t0_1),.t0_2(t0_2),.t0_3(t0_3), |
.t1_0(t1_0),.t1_1(t1_1),.t1_2(t1_2),.t1_3(t1_3), |
.t2_0(t2_0),.t2_1(t2_1),.t2_2(t2_2),.t2_3(t2_3), |
|
.mb_num_h_DF(mb_num_h_DF), |
.mb_num_v_DF(mb_num_v_DF), |
.end_of_MB_DF(end_of_MB_DF), |
.end_of_lastMB_DF(end_of_lastMB_DF), |
.DF_mbAddrA_RF_rd(DF_mbAddrA_RF_rd), |
.DF_mbAddrA_RF_wr(DF_mbAddrA_RF_wr), |
.DF_mbAddrA_RF_rd_addr(DF_mbAddrA_RF_rd_addr), |
.DF_mbAddrA_RF_wr_addr(DF_mbAddrA_RF_wr_addr), |
.DF_mbAddrA_RF_din(DF_mbAddrA_RF_din), |
.DF_mbAddrB_RAM_rd(DF_mbAddrB_RAM_rd), |
.DF_mbAddrB_RAM_wr(DF_mbAddrB_RAM_wr), |
.DF_mbAddrB_RAM_addr(DF_mbAddrB_RAM_addr), |
.DF_mbAddrB_RAM_din(DF_mbAddrB_RAM_din), |
.dis_frame_RAM_wr(dis_frame_RAM_wr), |
.dis_frame_RAM_wr_addr(dis_frame_RAM_wr_addr), |
.dis_frame_RAM_din(dis_frame_RAM_din) |
); |
ram_sync_1r_sync_1w # (`DF_mbAddrA_RAM_data_width,`DF_mbAddrA_RAM_data_depth) |
DF_mbAddrA_RAM ( |
.clk(gclk_DF_mbAddrA_RF), |
.rst_n(reset_n), |
.wr_n(~DF_mbAddrA_RF_wr), |
.rd_n(~DF_mbAddrA_RF_rd), |
.wr_addr(DF_mbAddrA_RF_wr_addr), |
.rd_addr(DF_mbAddrA_RF_rd_addr), |
.data_in(DF_mbAddrA_RF_din), |
.data_out(DF_mbAddrA_RF_dout) |
); |
ram_sync_1r_sync_1w # (`DF_mbAddrB_RAM_data_width,`DF_mbAddrB_RAM_data_depth) |
DF_mbAddrB_RAM ( |
.clk(gclk_DF_mbAddrB_RAM), |
.rst_n(reset_n), |
.wr_n(~DF_mbAddrB_RAM_wr), |
.rd_n(~DF_mbAddrB_RAM_rd), |
.wr_addr(DF_mbAddrB_RAM_addr), |
.rd_addr(DF_mbAddrB_RAM_addr), |
.data_in(DF_mbAddrB_RAM_din), |
.data_out(DF_mbAddrB_RAM_dout) |
); |
endmodule |
/trunk/src/Inter_pred_reg_ctrl.v
0,0 → 1,1699
//-------------------------------------------------------------------------------------------------- |
// Design : nova |
// Author(s) : Ke Xu |
// Email : eexuke@yahoo.com |
// File : Inter_pred_reg_ctrl.v |
// Generated : Oct 17, 2005 |
// Copyright (C) 2008 Ke Xu |
//------------------------------------------------------------------------------------------------- |
// Description |
// Prepare the appropriate registers for Inter prediction (luma & chroma) |
// Including padding |
//------------------------------------------------------------------------------------------------- |
|
// synopsys translate_off |
`include "timescale.v" |
// synopsys translate_on |
`include "nova_defines.v" |
|
module Inter_pred_reg_ctrl (gclk_Inter_ref_rf,reset_n,blk4x4_inter_preload_counter,ref_frame_RAM_dout, |
IsInterLuma,IsInterChroma,xInt_addr_unclip,xInt_org_unclip_1to0,pos_FracL,xFracC,yFracC,mv_below8x8_curr, |
|
Inter_ref_00_00,Inter_ref_01_00,Inter_ref_02_00,Inter_ref_03_00,Inter_ref_04_00,Inter_ref_05_00, |
Inter_ref_06_00,Inter_ref_07_00,Inter_ref_08_00,Inter_ref_09_00,Inter_ref_10_00,Inter_ref_11_00,Inter_ref_12_00, |
Inter_ref_00_01,Inter_ref_01_01,Inter_ref_02_01,Inter_ref_03_01,Inter_ref_04_01,Inter_ref_05_01, |
Inter_ref_06_01,Inter_ref_07_01,Inter_ref_08_01,Inter_ref_09_01,Inter_ref_10_01,Inter_ref_11_01,Inter_ref_12_01, |
Inter_ref_00_02,Inter_ref_01_02,Inter_ref_02_02,Inter_ref_03_02,Inter_ref_04_02,Inter_ref_05_02, |
Inter_ref_06_02,Inter_ref_07_02,Inter_ref_08_02,Inter_ref_09_02,Inter_ref_10_02,Inter_ref_11_02,Inter_ref_12_02, |
Inter_ref_00_03,Inter_ref_01_03,Inter_ref_02_03,Inter_ref_03_03,Inter_ref_04_03,Inter_ref_05_03, |
Inter_ref_06_03,Inter_ref_07_03,Inter_ref_08_03,Inter_ref_09_03,Inter_ref_10_03,Inter_ref_11_03,Inter_ref_12_03, |
Inter_ref_00_04,Inter_ref_01_04,Inter_ref_02_04,Inter_ref_03_04,Inter_ref_04_04,Inter_ref_05_04, |
Inter_ref_06_04,Inter_ref_07_04,Inter_ref_08_04,Inter_ref_09_04,Inter_ref_10_04,Inter_ref_11_04,Inter_ref_12_04, |
Inter_ref_00_05,Inter_ref_01_05,Inter_ref_02_05,Inter_ref_03_05,Inter_ref_04_05,Inter_ref_05_05, |
Inter_ref_06_05,Inter_ref_07_05,Inter_ref_08_05,Inter_ref_09_05,Inter_ref_10_05,Inter_ref_11_05,Inter_ref_12_05, |
Inter_ref_00_06,Inter_ref_01_06,Inter_ref_02_06,Inter_ref_03_06,Inter_ref_04_06,Inter_ref_05_06, |
Inter_ref_06_06,Inter_ref_07_06,Inter_ref_08_06,Inter_ref_09_06,Inter_ref_10_06,Inter_ref_11_06,Inter_ref_12_06, |
Inter_ref_00_07,Inter_ref_01_07,Inter_ref_02_07,Inter_ref_03_07,Inter_ref_04_07,Inter_ref_05_07, |
Inter_ref_06_07,Inter_ref_07_07,Inter_ref_08_07,Inter_ref_09_07,Inter_ref_10_07,Inter_ref_11_07,Inter_ref_12_07, |
Inter_ref_00_08,Inter_ref_01_08,Inter_ref_02_08,Inter_ref_03_08,Inter_ref_04_08,Inter_ref_05_08, |
Inter_ref_06_08,Inter_ref_07_08,Inter_ref_08_08,Inter_ref_09_08,Inter_ref_10_08,Inter_ref_11_08,Inter_ref_12_08, |
Inter_ref_00_09,Inter_ref_01_09,Inter_ref_02_09,Inter_ref_03_09,Inter_ref_04_09,Inter_ref_05_09, |
Inter_ref_06_09,Inter_ref_07_09,Inter_ref_08_09,Inter_ref_09_09,Inter_ref_10_09,Inter_ref_11_09,Inter_ref_12_09, |
Inter_ref_00_10,Inter_ref_01_10,Inter_ref_02_10,Inter_ref_03_10,Inter_ref_04_10,Inter_ref_05_10, |
Inter_ref_06_10,Inter_ref_07_10,Inter_ref_08_10,Inter_ref_09_10,Inter_ref_10_10,Inter_ref_11_10,Inter_ref_12_10, |
Inter_ref_00_11,Inter_ref_01_11,Inter_ref_02_11,Inter_ref_03_11,Inter_ref_04_11,Inter_ref_05_11, |
Inter_ref_06_11,Inter_ref_07_11,Inter_ref_08_11,Inter_ref_09_11,Inter_ref_10_11,Inter_ref_11_11,Inter_ref_12_11, |
Inter_ref_00_12,Inter_ref_01_12,Inter_ref_02_12,Inter_ref_03_12,Inter_ref_04_12,Inter_ref_05_12, |
Inter_ref_06_12,Inter_ref_07_12,Inter_ref_08_12,Inter_ref_09_12,Inter_ref_10_12,Inter_ref_11_12,Inter_ref_12_12); |
|
input gclk_Inter_ref_rf; |
input reset_n; |
input [5:0] blk4x4_inter_preload_counter; |
input [31:0] ref_frame_RAM_dout; |
input IsInterLuma,IsInterChroma; |
input [8:0] xInt_addr_unclip; |
input [1:0] xInt_org_unclip_1to0; |
input [3:0] pos_FracL; |
input [2:0] xFracC,yFracC; |
input mv_below8x8_curr; |
|
output [7:0] Inter_ref_00_00,Inter_ref_01_00,Inter_ref_02_00,Inter_ref_03_00,Inter_ref_04_00,Inter_ref_05_00; |
output [7:0] Inter_ref_06_00,Inter_ref_07_00,Inter_ref_08_00,Inter_ref_09_00,Inter_ref_10_00,Inter_ref_11_00,Inter_ref_12_00; |
output [7:0] Inter_ref_00_01,Inter_ref_01_01,Inter_ref_02_01,Inter_ref_03_01,Inter_ref_04_01,Inter_ref_05_01; |
output [7:0] Inter_ref_06_01,Inter_ref_07_01,Inter_ref_08_01,Inter_ref_09_01,Inter_ref_10_01,Inter_ref_11_01,Inter_ref_12_01; |
output [7:0] Inter_ref_00_02,Inter_ref_01_02,Inter_ref_02_02,Inter_ref_03_02,Inter_ref_04_02,Inter_ref_05_02; |
output [7:0] Inter_ref_06_02,Inter_ref_07_02,Inter_ref_08_02,Inter_ref_09_02,Inter_ref_10_02,Inter_ref_11_02,Inter_ref_12_02; |
output [7:0] Inter_ref_00_03,Inter_ref_01_03,Inter_ref_02_03,Inter_ref_03_03,Inter_ref_04_03,Inter_ref_05_03; |
output [7:0] Inter_ref_06_03,Inter_ref_07_03,Inter_ref_08_03,Inter_ref_09_03,Inter_ref_10_03,Inter_ref_11_03,Inter_ref_12_03; |
output [7:0] Inter_ref_00_04,Inter_ref_01_04,Inter_ref_02_04,Inter_ref_03_04,Inter_ref_04_04,Inter_ref_05_04; |
output [7:0] Inter_ref_06_04,Inter_ref_07_04,Inter_ref_08_04,Inter_ref_09_04,Inter_ref_10_04,Inter_ref_11_04,Inter_ref_12_04; |
output [7:0] Inter_ref_00_05,Inter_ref_01_05,Inter_ref_02_05,Inter_ref_03_05,Inter_ref_04_05,Inter_ref_05_05; |
output [7:0] Inter_ref_06_05,Inter_ref_07_05,Inter_ref_08_05,Inter_ref_09_05,Inter_ref_10_05,Inter_ref_11_05,Inter_ref_12_05; |
output [7:0] Inter_ref_00_06,Inter_ref_01_06,Inter_ref_02_06,Inter_ref_03_06,Inter_ref_04_06,Inter_ref_05_06; |
output [7:0] Inter_ref_06_06,Inter_ref_07_06,Inter_ref_08_06,Inter_ref_09_06,Inter_ref_10_06,Inter_ref_11_06,Inter_ref_12_06; |
output [7:0] Inter_ref_00_07,Inter_ref_01_07,Inter_ref_02_07,Inter_ref_03_07,Inter_ref_04_07,Inter_ref_05_07; |
output [7:0] Inter_ref_06_07,Inter_ref_07_07,Inter_ref_08_07,Inter_ref_09_07,Inter_ref_10_07,Inter_ref_11_07,Inter_ref_12_07; |
output [7:0] Inter_ref_00_08,Inter_ref_01_08,Inter_ref_02_08,Inter_ref_03_08,Inter_ref_04_08,Inter_ref_05_08; |
output [7:0] Inter_ref_06_08,Inter_ref_07_08,Inter_ref_08_08,Inter_ref_09_08,Inter_ref_10_08,Inter_ref_11_08,Inter_ref_12_08; |
output [7:0] Inter_ref_00_09,Inter_ref_01_09,Inter_ref_02_09,Inter_ref_03_09,Inter_ref_04_09,Inter_ref_05_09; |
output [7:0] Inter_ref_06_09,Inter_ref_07_09,Inter_ref_08_09,Inter_ref_09_09,Inter_ref_10_09,Inter_ref_11_09,Inter_ref_12_09; |
output [7:0] Inter_ref_00_10,Inter_ref_01_10,Inter_ref_02_10,Inter_ref_03_10,Inter_ref_04_10,Inter_ref_05_10; |
output [7:0] Inter_ref_06_10,Inter_ref_07_10,Inter_ref_08_10,Inter_ref_09_10,Inter_ref_10_10,Inter_ref_11_10,Inter_ref_12_10; |
output [7:0] Inter_ref_00_11,Inter_ref_01_11,Inter_ref_02_11,Inter_ref_03_11,Inter_ref_04_11,Inter_ref_05_11; |
output [7:0] Inter_ref_06_11,Inter_ref_07_11,Inter_ref_08_11,Inter_ref_09_11,Inter_ref_10_11,Inter_ref_11_11,Inter_ref_12_11; |
output [7:0] Inter_ref_00_12,Inter_ref_01_12,Inter_ref_02_12,Inter_ref_03_12,Inter_ref_04_12,Inter_ref_05_12; |
output [7:0] Inter_ref_06_12,Inter_ref_07_12,Inter_ref_08_12,Inter_ref_09_12,Inter_ref_10_12,Inter_ref_11_12,Inter_ref_12_12; |
|
reg [7:0] Inter_ref_00_00,Inter_ref_01_00,Inter_ref_02_00,Inter_ref_03_00,Inter_ref_04_00,Inter_ref_05_00; |
reg [7:0] Inter_ref_06_00,Inter_ref_07_00,Inter_ref_08_00,Inter_ref_09_00,Inter_ref_10_00,Inter_ref_11_00,Inter_ref_12_00; |
reg [7:0] Inter_ref_00_01,Inter_ref_01_01,Inter_ref_02_01,Inter_ref_03_01,Inter_ref_04_01,Inter_ref_05_01; |
reg [7:0] Inter_ref_06_01,Inter_ref_07_01,Inter_ref_08_01,Inter_ref_09_01,Inter_ref_10_01,Inter_ref_11_01,Inter_ref_12_01; |
reg [7:0] Inter_ref_00_02,Inter_ref_01_02,Inter_ref_02_02,Inter_ref_03_02,Inter_ref_04_02,Inter_ref_05_02; |
reg [7:0] Inter_ref_06_02,Inter_ref_07_02,Inter_ref_08_02,Inter_ref_09_02,Inter_ref_10_02,Inter_ref_11_02,Inter_ref_12_02; |
reg [7:0] Inter_ref_00_03,Inter_ref_01_03,Inter_ref_02_03,Inter_ref_03_03,Inter_ref_04_03,Inter_ref_05_03; |
reg [7:0] Inter_ref_06_03,Inter_ref_07_03,Inter_ref_08_03,Inter_ref_09_03,Inter_ref_10_03,Inter_ref_11_03,Inter_ref_12_03; |
reg [7:0] Inter_ref_00_04,Inter_ref_01_04,Inter_ref_02_04,Inter_ref_03_04,Inter_ref_04_04,Inter_ref_05_04; |
reg [7:0] Inter_ref_06_04,Inter_ref_07_04,Inter_ref_08_04,Inter_ref_09_04,Inter_ref_10_04,Inter_ref_11_04,Inter_ref_12_04; |
reg [7:0] Inter_ref_00_05,Inter_ref_01_05,Inter_ref_02_05,Inter_ref_03_05,Inter_ref_04_05,Inter_ref_05_05; |
reg [7:0] Inter_ref_06_05,Inter_ref_07_05,Inter_ref_08_05,Inter_ref_09_05,Inter_ref_10_05,Inter_ref_11_05,Inter_ref_12_05; |
reg [7:0] Inter_ref_00_06,Inter_ref_01_06,Inter_ref_02_06,Inter_ref_03_06,Inter_ref_04_06,Inter_ref_05_06; |
reg [7:0] Inter_ref_06_06,Inter_ref_07_06,Inter_ref_08_06,Inter_ref_09_06,Inter_ref_10_06,Inter_ref_11_06,Inter_ref_12_06; |
reg [7:0] Inter_ref_00_07,Inter_ref_01_07,Inter_ref_02_07,Inter_ref_03_07,Inter_ref_04_07,Inter_ref_05_07; |
reg [7:0] Inter_ref_06_07,Inter_ref_07_07,Inter_ref_08_07,Inter_ref_09_07,Inter_ref_10_07,Inter_ref_11_07,Inter_ref_12_07; |
reg [7:0] Inter_ref_00_08,Inter_ref_01_08,Inter_ref_02_08,Inter_ref_03_08,Inter_ref_04_08,Inter_ref_05_08; |
reg [7:0] Inter_ref_06_08,Inter_ref_07_08,Inter_ref_08_08,Inter_ref_09_08,Inter_ref_10_08,Inter_ref_11_08,Inter_ref_12_08; |
reg [7:0] Inter_ref_00_09,Inter_ref_01_09,Inter_ref_02_09,Inter_ref_03_09,Inter_ref_04_09,Inter_ref_05_09; |
reg [7:0] Inter_ref_06_09,Inter_ref_07_09,Inter_ref_08_09,Inter_ref_09_09,Inter_ref_10_09,Inter_ref_11_09,Inter_ref_12_09; |
reg [7:0] Inter_ref_00_10,Inter_ref_01_10,Inter_ref_02_10,Inter_ref_03_10,Inter_ref_04_10,Inter_ref_05_10; |
reg [7:0] Inter_ref_06_10,Inter_ref_07_10,Inter_ref_08_10,Inter_ref_09_10,Inter_ref_10_10,Inter_ref_11_10,Inter_ref_12_10; |
reg [7:0] Inter_ref_00_11,Inter_ref_01_11,Inter_ref_02_11,Inter_ref_03_11,Inter_ref_04_11,Inter_ref_05_11; |
reg [7:0] Inter_ref_06_11,Inter_ref_07_11,Inter_ref_08_11,Inter_ref_09_11,Inter_ref_10_11,Inter_ref_11_11,Inter_ref_12_11; |
reg [7:0] Inter_ref_00_12,Inter_ref_01_12,Inter_ref_02_12,Inter_ref_03_12,Inter_ref_04_12,Inter_ref_05_12; |
reg [7:0] Inter_ref_06_12,Inter_ref_07_12,Inter_ref_08_12,Inter_ref_09_12,Inter_ref_10_12,Inter_ref_11_12,Inter_ref_12_12; |
|
//------------------------------------------------------------------------- |
//out of bound padding |
//------------------------------------------------------------------------- |
//In original version where ext_frame_RAM is read async,no need to latch xInt_addr_unclip |
//since it is used here in the same cycle as it is generated in Inter_pred_pipeline module. |
//However,when ext_frame_RAM is changed to sync read,xInt_addr_unclip will be used one cyle later. |
reg [8:0] xInt_addr_unclip_reg; |
always @ (posedge gclk_Inter_ref_rf or negedge reset_n) |
if (reset_n == 1'b0) |
xInt_addr_unclip_reg <= 0; |
else |
xInt_addr_unclip_reg <= xInt_addr_unclip; |
|
reg [31:0] RefFrameOutPadding; |
always @ (xInt_addr_unclip_reg or ref_frame_RAM_dout or IsInterLuma or IsInterChroma) |
if (xInt_addr_unclip_reg[8] == 1'b1) //out of left bound |
RefFrameOutPadding <= {ref_frame_RAM_dout[7:0],ref_frame_RAM_dout[7:0], |
ref_frame_RAM_dout[7:0],ref_frame_RAM_dout[7:0]}; |
else |
begin |
if ((IsInterLuma && xInt_addr_unclip_reg[7:2] > 6'b101011) || //out of right bound |
(IsInterChroma && xInt_addr_unclip_reg[7:2] > 6'b010101)) |
RefFrameOutPadding <= {ref_frame_RAM_dout[31:24],ref_frame_RAM_dout[31:24], |
ref_frame_RAM_dout[31:24],ref_frame_RAM_dout[31:24]}; |
else |
RefFrameOutPadding <= ref_frame_RAM_dout; |
end |
//------------------------------------------------------------------------- |
//Inter_ref_00_00 ~ Inter_ref_12_12 |
//------------------------------------------------------------------------- |
always @ (posedge gclk_Inter_ref_rf or negedge reset_n) |
if (reset_n == 0) |
begin |
Inter_ref_00_00 <= 0;Inter_ref_01_00 <= 0;Inter_ref_02_00 <= 0;Inter_ref_03_00 <= 0; |
Inter_ref_04_00 <= 0;Inter_ref_05_00 <= 0;Inter_ref_06_00 <= 0;Inter_ref_07_00 <= 0; |
Inter_ref_08_00 <= 0;Inter_ref_09_00 <= 0;Inter_ref_10_00 <= 0;Inter_ref_11_00 <= 0;Inter_ref_12_00 <= 0; |
Inter_ref_00_01 <= 0;Inter_ref_01_01 <= 0;Inter_ref_02_01 <= 0;Inter_ref_03_01 <= 0; |
Inter_ref_04_01 <= 0;Inter_ref_05_01 <= 0;Inter_ref_06_01 <= 0;Inter_ref_07_01 <= 0; |
Inter_ref_08_01 <= 0;Inter_ref_09_01 <= 0;Inter_ref_10_01 <= 0;Inter_ref_11_01 <= 0;Inter_ref_12_01 <= 0; |
Inter_ref_00_02 <= 0;Inter_ref_01_02 <= 0;Inter_ref_02_02 <= 0;Inter_ref_03_02 <= 0; |
Inter_ref_04_02 <= 0;Inter_ref_05_02 <= 0;Inter_ref_06_02 <= 0;Inter_ref_07_02 <= 0; |
Inter_ref_08_02 <= 0;Inter_ref_09_02 <= 0;Inter_ref_10_02 <= 0;Inter_ref_11_02 <= 0;Inter_ref_12_02 <= 0; |
Inter_ref_00_03 <= 0;Inter_ref_01_03 <= 0;Inter_ref_02_03 <= 0;Inter_ref_03_03 <= 0; |
Inter_ref_04_03 <= 0;Inter_ref_05_03 <= 0;Inter_ref_06_03 <= 0;Inter_ref_07_03 <= 0; |
Inter_ref_08_03 <= 0;Inter_ref_09_03 <= 0;Inter_ref_10_03 <= 0;Inter_ref_11_03 <= 0;Inter_ref_12_03 <= 0; |
Inter_ref_00_04 <= 0;Inter_ref_01_04 <= 0;Inter_ref_02_04 <= 0;Inter_ref_03_04 <= 0; |
Inter_ref_04_04 <= 0;Inter_ref_05_04 <= 0;Inter_ref_06_04 <= 0;Inter_ref_07_04 <= 0; |
Inter_ref_08_04 <= 0;Inter_ref_09_04 <= 0;Inter_ref_10_04 <= 0;Inter_ref_11_04 <= 0;Inter_ref_12_04 <= 0; |
Inter_ref_00_05 <= 0;Inter_ref_01_05 <= 0;Inter_ref_02_05 <= 0;Inter_ref_03_05 <= 0; |
Inter_ref_04_05 <= 0;Inter_ref_05_05 <= 0;Inter_ref_06_05 <= 0;Inter_ref_07_05 <= 0; |
Inter_ref_08_05 <= 0;Inter_ref_09_05 <= 0;Inter_ref_10_05 <= 0;Inter_ref_11_05 <= 0;Inter_ref_12_05 <= 0; |
Inter_ref_00_06 <= 0;Inter_ref_01_06 <= 0;Inter_ref_02_06 <= 0;Inter_ref_03_06 <= 0; |
Inter_ref_04_06 <= 0;Inter_ref_05_06 <= 0;Inter_ref_06_06 <= 0;Inter_ref_07_06 <= 0; |
Inter_ref_08_06 <= 0;Inter_ref_09_06 <= 0;Inter_ref_10_06 <= 0;Inter_ref_11_06 <= 0;Inter_ref_12_06 <= 0; |
Inter_ref_00_07 <= 0;Inter_ref_01_07 <= 0;Inter_ref_02_07 <= 0;Inter_ref_03_07 <= 0; |
Inter_ref_04_07 <= 0;Inter_ref_05_07 <= 0;Inter_ref_06_07 <= 0;Inter_ref_07_07 <= 0; |
Inter_ref_08_07 <= 0;Inter_ref_09_07 <= 0;Inter_ref_10_07 <= 0;Inter_ref_11_07 <= 0;Inter_ref_12_07 <= 0; |
Inter_ref_00_08 <= 0;Inter_ref_01_08 <= 0;Inter_ref_02_08 <= 0;Inter_ref_03_08 <= 0; |
Inter_ref_04_08 <= 0;Inter_ref_05_08 <= 0;Inter_ref_06_08 <= 0;Inter_ref_07_08 <= 0; |
Inter_ref_08_08 <= 0;Inter_ref_09_08 <= 0;Inter_ref_10_08 <= 0;Inter_ref_11_08 <= 0;Inter_ref_12_08 <= 0; |
Inter_ref_00_09 <= 0;Inter_ref_01_09 <= 0;Inter_ref_02_09 <= 0;Inter_ref_03_09 <= 0; |
Inter_ref_04_09 <= 0;Inter_ref_05_09 <= 0;Inter_ref_06_09 <= 0;Inter_ref_07_09 <= 0; |
Inter_ref_08_09 <= 0;Inter_ref_09_09 <= 0;Inter_ref_10_09 <= 0;Inter_ref_11_09 <= 0;Inter_ref_12_09 <= 0; |
Inter_ref_00_10 <= 0;Inter_ref_01_10 <= 0;Inter_ref_02_10 <= 0;Inter_ref_03_10 <= 0; |
Inter_ref_04_10 <= 0;Inter_ref_05_10 <= 0;Inter_ref_06_10 <= 0;Inter_ref_07_10 <= 0; |
Inter_ref_08_10 <= 0;Inter_ref_09_10 <= 0;Inter_ref_10_10 <= 0;Inter_ref_11_10 <= 0;Inter_ref_12_10 <= 0; |
Inter_ref_00_11 <= 0;Inter_ref_01_11 <= 0;Inter_ref_02_11 <= 0;Inter_ref_03_11 <= 0; |
Inter_ref_04_11 <= 0;Inter_ref_05_11 <= 0;Inter_ref_06_11 <= 0;Inter_ref_07_11 <= 0; |
Inter_ref_08_11 <= 0;Inter_ref_09_11 <= 0;Inter_ref_10_11 <= 0;Inter_ref_11_11 <= 0;Inter_ref_12_11 <= 0; |
Inter_ref_00_12 <= 0;Inter_ref_01_12 <= 0;Inter_ref_02_12 <= 0;Inter_ref_03_12 <= 0; |
Inter_ref_04_12 <= 0;Inter_ref_05_12 <= 0;Inter_ref_06_12 <= 0;Inter_ref_07_12 <= 0; |
Inter_ref_08_12 <= 0;Inter_ref_09_12 <= 0;Inter_ref_10_12 <= 0;Inter_ref_11_12 <= 0;Inter_ref_12_12 <= 0; |
end |
else if (IsInterLuma && blk4x4_inter_preload_counter != 0) |
case (mv_below8x8_curr) |
1'b0: |
case (pos_FracL) |
`pos_f,`pos_q,`pos_i,`pos_k,`pos_j: |
case (xInt_org_unclip_1to0) |
2'b00: |
case (blk4x4_inter_preload_counter) |
6'd52:{Inter_ref_01_00,Inter_ref_00_00} <= RefFrameOutPadding[31:16]; |
6'd51:{Inter_ref_05_00,Inter_ref_04_00,Inter_ref_03_00,Inter_ref_02_00} <= RefFrameOutPadding; |
6'd50:{Inter_ref_09_00,Inter_ref_08_00,Inter_ref_07_00,Inter_ref_06_00} <= RefFrameOutPadding; |
6'd49:{Inter_ref_12_00,Inter_ref_11_00,Inter_ref_10_00} <= RefFrameOutPadding[23:0]; |
6'd48:{Inter_ref_01_01,Inter_ref_00_01} <= RefFrameOutPadding[31:16]; |
6'd47:{Inter_ref_05_01,Inter_ref_04_01,Inter_ref_03_01,Inter_ref_02_01} <= RefFrameOutPadding; |
6'd46:{Inter_ref_09_01,Inter_ref_08_01,Inter_ref_07_01,Inter_ref_06_01} <= RefFrameOutPadding; |
6'd45:{Inter_ref_12_01,Inter_ref_11_01,Inter_ref_10_01} <= RefFrameOutPadding[23:0]; |
6'd44:{Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding[31:16]; |
6'd43:{Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding; |
6'd42:{Inter_ref_09_02,Inter_ref_08_02,Inter_ref_07_02,Inter_ref_06_02} <= RefFrameOutPadding; |
6'd41:{Inter_ref_12_02,Inter_ref_11_02,Inter_ref_10_02} <= RefFrameOutPadding[23:0]; |
6'd40:{Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding[31:16]; |
6'd39:{Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding; |
6'd38:{Inter_ref_09_03,Inter_ref_08_03,Inter_ref_07_03,Inter_ref_06_03} <= RefFrameOutPadding; |
6'd37:{Inter_ref_12_03,Inter_ref_11_03,Inter_ref_10_03} <= RefFrameOutPadding[23:0]; |
6'd36:{Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding[31:16]; |
6'd35:{Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04} <= RefFrameOutPadding; |
6'd34:{Inter_ref_09_04,Inter_ref_08_04,Inter_ref_07_04,Inter_ref_06_04} <= RefFrameOutPadding; |
6'd33:{Inter_ref_12_04,Inter_ref_11_04,Inter_ref_10_04} <= RefFrameOutPadding[23:0]; |
6'd32:{Inter_ref_01_05,Inter_ref_00_05} <= RefFrameOutPadding[31:16]; |
6'd31:{Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05} <= RefFrameOutPadding; |
6'd30:{Inter_ref_09_05,Inter_ref_08_05,Inter_ref_07_05,Inter_ref_06_05} <= RefFrameOutPadding; |
6'd29:{Inter_ref_12_05,Inter_ref_11_05,Inter_ref_10_05} <= RefFrameOutPadding[23:0]; |
6'd28:{Inter_ref_01_06,Inter_ref_00_06} <= RefFrameOutPadding[31:16]; |
6'd27:{Inter_ref_05_06,Inter_ref_04_06,Inter_ref_03_06,Inter_ref_02_06} <= RefFrameOutPadding; |
6'd26:{Inter_ref_09_06,Inter_ref_08_06,Inter_ref_07_06,Inter_ref_06_06} <= RefFrameOutPadding; |
6'd25:{Inter_ref_12_06,Inter_ref_11_06,Inter_ref_10_06} <= RefFrameOutPadding[23:0]; |
6'd24:{Inter_ref_01_07,Inter_ref_00_07} <= RefFrameOutPadding[31:16]; |
6'd23:{Inter_ref_05_07,Inter_ref_04_07,Inter_ref_03_07,Inter_ref_02_07} <= RefFrameOutPadding; |
6'd22:{Inter_ref_09_07,Inter_ref_08_07,Inter_ref_07_07,Inter_ref_06_07} <= RefFrameOutPadding; |
6'd21:{Inter_ref_12_07,Inter_ref_11_07,Inter_ref_10_07} <= RefFrameOutPadding[23:0]; |
6'd20:{Inter_ref_01_08,Inter_ref_00_08} <= RefFrameOutPadding[31:16]; |
6'd19:{Inter_ref_05_08,Inter_ref_04_08,Inter_ref_03_08,Inter_ref_02_08} <= RefFrameOutPadding; |
6'd18:{Inter_ref_09_08,Inter_ref_08_08,Inter_ref_07_08,Inter_ref_06_08} <= RefFrameOutPadding; |
6'd17:{Inter_ref_12_08,Inter_ref_11_08,Inter_ref_10_08} <= RefFrameOutPadding[23:0]; |
6'd16:{Inter_ref_01_09,Inter_ref_00_09} <= RefFrameOutPadding[31:16]; |
6'd15:{Inter_ref_05_09,Inter_ref_04_09,Inter_ref_03_09,Inter_ref_02_09} <= RefFrameOutPadding; |
6'd14:{Inter_ref_09_09,Inter_ref_08_09,Inter_ref_07_09,Inter_ref_06_09} <= RefFrameOutPadding; |
6'd13:{Inter_ref_12_09,Inter_ref_11_09,Inter_ref_10_09} <= RefFrameOutPadding[23:0]; |
6'd12:{Inter_ref_01_10,Inter_ref_00_10} <= RefFrameOutPadding[31:16]; |
6'd11:{Inter_ref_05_10,Inter_ref_04_10,Inter_ref_03_10,Inter_ref_02_10} <= RefFrameOutPadding; |
6'd10:{Inter_ref_09_10,Inter_ref_08_10,Inter_ref_07_10,Inter_ref_06_10} <= RefFrameOutPadding; |
6'd9 :{Inter_ref_12_10,Inter_ref_11_10,Inter_ref_10_10} <= RefFrameOutPadding[23:0]; |
6'd8 :{Inter_ref_01_11,Inter_ref_00_11} <= RefFrameOutPadding[31:16]; |
6'd7 :{Inter_ref_05_11,Inter_ref_04_11,Inter_ref_03_11,Inter_ref_02_11} <= RefFrameOutPadding; |
6'd6 :{Inter_ref_09_11,Inter_ref_08_11,Inter_ref_07_11,Inter_ref_06_11} <= RefFrameOutPadding; |
6'd5 :{Inter_ref_12_11,Inter_ref_11_11,Inter_ref_10_11} <= RefFrameOutPadding[23:0]; |
6'd4 :{Inter_ref_01_12,Inter_ref_00_12} <= RefFrameOutPadding[31:16]; |
6'd3 :{Inter_ref_05_12,Inter_ref_04_12,Inter_ref_03_12,Inter_ref_02_12} <= RefFrameOutPadding; |
6'd2 :{Inter_ref_09_12,Inter_ref_08_12,Inter_ref_07_12,Inter_ref_06_12} <= RefFrameOutPadding; |
6'd1 :{Inter_ref_12_12,Inter_ref_11_12,Inter_ref_10_12} <= RefFrameOutPadding[23:0]; |
endcase |
2'b01: |
case (blk4x4_inter_preload_counter) |
6'd52:Inter_ref_00_00 <= RefFrameOutPadding[31:24]; |
6'd51:{Inter_ref_04_00,Inter_ref_03_00,Inter_ref_02_00,Inter_ref_01_00} <= RefFrameOutPadding; |
6'd50:{Inter_ref_08_00,Inter_ref_07_00,Inter_ref_06_00,Inter_ref_05_00} <= RefFrameOutPadding; |
6'd49:{Inter_ref_12_00,Inter_ref_11_00,Inter_ref_10_00,Inter_ref_09_00} <= RefFrameOutPadding; |
6'd48:Inter_ref_00_01 <= RefFrameOutPadding[31:24]; |
6'd47:{Inter_ref_04_01,Inter_ref_03_01,Inter_ref_02_01,Inter_ref_01_01} <= RefFrameOutPadding; |
6'd46:{Inter_ref_08_01,Inter_ref_07_01,Inter_ref_06_01,Inter_ref_05_01} <= RefFrameOutPadding; |
6'd45:{Inter_ref_12_01,Inter_ref_11_01,Inter_ref_10_01,Inter_ref_09_01} <= RefFrameOutPadding; |
6'd44:Inter_ref_00_02 <= RefFrameOutPadding[31:24]; |
6'd43:{Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02,Inter_ref_01_02} <= RefFrameOutPadding; |
6'd42:{Inter_ref_08_02,Inter_ref_07_02,Inter_ref_06_02,Inter_ref_05_02} <= RefFrameOutPadding; |
6'd41:{Inter_ref_12_02,Inter_ref_11_02,Inter_ref_10_02,Inter_ref_09_02} <= RefFrameOutPadding; |
6'd40:Inter_ref_00_03 <= RefFrameOutPadding[31:24]; |
6'd39:{Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03,Inter_ref_01_03} <= RefFrameOutPadding; |
6'd38:{Inter_ref_08_03,Inter_ref_07_03,Inter_ref_06_03,Inter_ref_05_03} <= RefFrameOutPadding; |
6'd37:{Inter_ref_12_03,Inter_ref_11_03,Inter_ref_10_03,Inter_ref_09_03} <= RefFrameOutPadding; |
6'd36:Inter_ref_00_04 <= RefFrameOutPadding[31:24]; |
6'd35:{Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04,Inter_ref_01_04} <= RefFrameOutPadding; |
6'd34:{Inter_ref_08_04,Inter_ref_07_04,Inter_ref_06_04,Inter_ref_05_04} <= RefFrameOutPadding; |
6'd33:{Inter_ref_12_04,Inter_ref_11_04,Inter_ref_10_04,Inter_ref_09_04} <= RefFrameOutPadding; |
6'd32:Inter_ref_00_05 <= RefFrameOutPadding[31:24]; |
6'd31:{Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05,Inter_ref_01_05} <= RefFrameOutPadding; |
6'd30:{Inter_ref_08_05,Inter_ref_07_05,Inter_ref_06_05,Inter_ref_05_05} <= RefFrameOutPadding; |
6'd29:{Inter_ref_12_05,Inter_ref_11_05,Inter_ref_10_05,Inter_ref_09_05} <= RefFrameOutPadding; |
6'd28:Inter_ref_00_06 <= RefFrameOutPadding[31:24]; |
6'd27:{Inter_ref_04_06,Inter_ref_03_06,Inter_ref_02_06,Inter_ref_01_06} <= RefFrameOutPadding; |
6'd26:{Inter_ref_08_06,Inter_ref_07_06,Inter_ref_06_06,Inter_ref_05_06} <= RefFrameOutPadding; |
6'd25:{Inter_ref_12_06,Inter_ref_11_06,Inter_ref_10_06,Inter_ref_09_06} <= RefFrameOutPadding; |
6'd24:Inter_ref_00_07 <= RefFrameOutPadding[31:24]; |
6'd23:{Inter_ref_04_07,Inter_ref_03_07,Inter_ref_02_07,Inter_ref_01_07} <= RefFrameOutPadding; |
6'd22:{Inter_ref_08_07,Inter_ref_07_07,Inter_ref_06_07,Inter_ref_05_07} <= RefFrameOutPadding; |
6'd21:{Inter_ref_12_07,Inter_ref_11_07,Inter_ref_10_07,Inter_ref_09_07} <= RefFrameOutPadding; |
6'd20:Inter_ref_00_08 <= RefFrameOutPadding[31:24]; |
6'd19:{Inter_ref_04_08,Inter_ref_03_08,Inter_ref_02_08,Inter_ref_01_08} <= RefFrameOutPadding; |
6'd18:{Inter_ref_08_08,Inter_ref_07_08,Inter_ref_06_08,Inter_ref_05_08} <= RefFrameOutPadding; |
6'd17:{Inter_ref_12_08,Inter_ref_11_08,Inter_ref_10_08,Inter_ref_09_08} <= RefFrameOutPadding; |
6'd16:Inter_ref_00_09 <= RefFrameOutPadding[31:24]; |
6'd15:{Inter_ref_04_09,Inter_ref_03_09,Inter_ref_02_09,Inter_ref_01_09} <= RefFrameOutPadding; |
6'd14:{Inter_ref_08_09,Inter_ref_07_09,Inter_ref_06_09,Inter_ref_05_09} <= RefFrameOutPadding; |
6'd13:{Inter_ref_12_09,Inter_ref_11_09,Inter_ref_10_09,Inter_ref_09_09} <= RefFrameOutPadding; |
6'd12:Inter_ref_00_10 <= RefFrameOutPadding[31:24]; |
6'd11:{Inter_ref_04_10,Inter_ref_03_10,Inter_ref_02_10,Inter_ref_01_10} <= RefFrameOutPadding; |
6'd10:{Inter_ref_08_10,Inter_ref_07_10,Inter_ref_06_10,Inter_ref_05_10} <= RefFrameOutPadding; |
6'd9 :{Inter_ref_12_10,Inter_ref_11_10,Inter_ref_10_10,Inter_ref_09_10} <= RefFrameOutPadding; |
6'd8 :Inter_ref_00_11 <= RefFrameOutPadding[31:24]; |
6'd7 :{Inter_ref_04_11,Inter_ref_03_11,Inter_ref_02_11,Inter_ref_01_11} <= RefFrameOutPadding; |
6'd6 :{Inter_ref_08_11,Inter_ref_07_11,Inter_ref_06_11,Inter_ref_05_11} <= RefFrameOutPadding; |
6'd5 :{Inter_ref_12_11,Inter_ref_11_11,Inter_ref_10_11,Inter_ref_09_11} <= RefFrameOutPadding; |
6'd4 :Inter_ref_00_12 <= RefFrameOutPadding[31:24]; |
6'd3 :{Inter_ref_04_12,Inter_ref_03_12,Inter_ref_02_12,Inter_ref_01_12} <= RefFrameOutPadding; |
6'd2 :{Inter_ref_08_12,Inter_ref_07_12,Inter_ref_06_12,Inter_ref_05_12} <= RefFrameOutPadding; |
6'd1 :{Inter_ref_12_12,Inter_ref_11_12,Inter_ref_10_12,Inter_ref_09_12} <= RefFrameOutPadding; |
endcase |
2'b10: |
case (blk4x4_inter_preload_counter) |
6'd52:{Inter_ref_03_00,Inter_ref_02_00,Inter_ref_01_00,Inter_ref_00_00} <= RefFrameOutPadding; |
6'd51:{Inter_ref_07_00,Inter_ref_06_00,Inter_ref_05_00,Inter_ref_04_00} <= RefFrameOutPadding; |
6'd50:{Inter_ref_11_00,Inter_ref_10_00,Inter_ref_09_00,Inter_ref_08_00} <= RefFrameOutPadding; |
6'd49:Inter_ref_12_00 <= RefFrameOutPadding[7:0]; |
6'd48:{Inter_ref_03_01,Inter_ref_02_01,Inter_ref_01_01,Inter_ref_00_01} <= RefFrameOutPadding; |
6'd47:{Inter_ref_07_01,Inter_ref_06_01,Inter_ref_05_01,Inter_ref_04_01} <= RefFrameOutPadding; |
6'd46:{Inter_ref_11_01,Inter_ref_10_01,Inter_ref_09_01,Inter_ref_08_01} <= RefFrameOutPadding; |
6'd45:Inter_ref_12_01 <= RefFrameOutPadding[7:0]; |
6'd44:{Inter_ref_03_02,Inter_ref_02_02,Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding; |
6'd43:{Inter_ref_07_02,Inter_ref_06_02,Inter_ref_05_02,Inter_ref_04_02} <= RefFrameOutPadding; |
6'd42:{Inter_ref_11_02,Inter_ref_10_02,Inter_ref_09_02,Inter_ref_08_02} <= RefFrameOutPadding; |
6'd41:Inter_ref_12_02 <= RefFrameOutPadding[7:0]; |
6'd40:{Inter_ref_03_03,Inter_ref_02_03,Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding; |
6'd39:{Inter_ref_07_03,Inter_ref_06_03,Inter_ref_05_03,Inter_ref_04_03} <= RefFrameOutPadding; |
6'd38:{Inter_ref_11_03,Inter_ref_10_03,Inter_ref_09_03,Inter_ref_08_03} <= RefFrameOutPadding; |
6'd37:Inter_ref_12_03 <= RefFrameOutPadding[7:0]; |
6'd36:{Inter_ref_03_04,Inter_ref_02_04,Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding; |
6'd35:{Inter_ref_07_04,Inter_ref_06_04,Inter_ref_05_04,Inter_ref_04_04} <= RefFrameOutPadding; |
6'd34:{Inter_ref_11_04,Inter_ref_10_04,Inter_ref_09_04,Inter_ref_08_04} <= RefFrameOutPadding; |
6'd33:Inter_ref_12_04 <= RefFrameOutPadding[7:0]; |
6'd32:{Inter_ref_03_05,Inter_ref_02_05,Inter_ref_01_05,Inter_ref_00_05} <= RefFrameOutPadding; |
6'd31:{Inter_ref_07_05,Inter_ref_06_05,Inter_ref_05_05,Inter_ref_04_05} <= RefFrameOutPadding; |
6'd30:{Inter_ref_11_05,Inter_ref_10_05,Inter_ref_09_05,Inter_ref_08_05} <= RefFrameOutPadding; |
6'd29:Inter_ref_12_05 <= RefFrameOutPadding[7:0]; |
6'd28:{Inter_ref_03_06,Inter_ref_02_06,Inter_ref_01_06,Inter_ref_00_06} <= RefFrameOutPadding; |
6'd27:{Inter_ref_07_06,Inter_ref_06_06,Inter_ref_05_06,Inter_ref_04_06} <= RefFrameOutPadding; |
6'd26:{Inter_ref_11_06,Inter_ref_10_06,Inter_ref_09_06,Inter_ref_08_06} <= RefFrameOutPadding; |
6'd25:Inter_ref_12_06 <= RefFrameOutPadding[7:0]; |
6'd24:{Inter_ref_03_07,Inter_ref_02_07,Inter_ref_01_07,Inter_ref_00_07} <= RefFrameOutPadding; |
6'd23:{Inter_ref_07_07,Inter_ref_06_07,Inter_ref_05_07,Inter_ref_04_07} <= RefFrameOutPadding; |
6'd22:{Inter_ref_11_07,Inter_ref_10_07,Inter_ref_09_07,Inter_ref_08_07} <= RefFrameOutPadding; |
6'd21:Inter_ref_12_07 <= RefFrameOutPadding[7:0]; |
6'd20:{Inter_ref_03_08,Inter_ref_02_08,Inter_ref_01_08,Inter_ref_00_08} <= RefFrameOutPadding; |
6'd19:{Inter_ref_07_08,Inter_ref_06_08,Inter_ref_05_08,Inter_ref_04_08} <= RefFrameOutPadding; |
6'd18:{Inter_ref_11_08,Inter_ref_10_08,Inter_ref_09_08,Inter_ref_08_08} <= RefFrameOutPadding; |
6'd17:Inter_ref_12_08 <= RefFrameOutPadding[7:0]; |
6'd16:{Inter_ref_03_09,Inter_ref_02_09,Inter_ref_01_09,Inter_ref_00_09} <= RefFrameOutPadding; |
6'd15:{Inter_ref_07_09,Inter_ref_06_09,Inter_ref_05_09,Inter_ref_04_09} <= RefFrameOutPadding; |
6'd14:{Inter_ref_11_09,Inter_ref_10_09,Inter_ref_09_09,Inter_ref_08_09} <= RefFrameOutPadding; |
6'd13:Inter_ref_12_09 <= RefFrameOutPadding[7:0]; |
6'd12:{Inter_ref_03_10,Inter_ref_02_10,Inter_ref_01_10,Inter_ref_00_10} <= RefFrameOutPadding; |
6'd11:{Inter_ref_07_10,Inter_ref_06_10,Inter_ref_05_10,Inter_ref_04_10} <= RefFrameOutPadding; |
6'd10:{Inter_ref_11_10,Inter_ref_10_10,Inter_ref_09_10,Inter_ref_08_10} <= RefFrameOutPadding; |
6'd9 :Inter_ref_12_10 <= RefFrameOutPadding[7:0]; |
6'd8 :{Inter_ref_03_11,Inter_ref_02_11,Inter_ref_01_11,Inter_ref_00_11} <= RefFrameOutPadding; |
6'd7 :{Inter_ref_07_11,Inter_ref_06_11,Inter_ref_05_11,Inter_ref_04_11} <= RefFrameOutPadding; |
6'd6 :{Inter_ref_11_11,Inter_ref_10_11,Inter_ref_09_11,Inter_ref_08_11} <= RefFrameOutPadding; |
6'd5 :Inter_ref_12_11 <= RefFrameOutPadding[7:0]; |
6'd4 :{Inter_ref_03_12,Inter_ref_02_12,Inter_ref_01_12,Inter_ref_00_12} <= RefFrameOutPadding; |
6'd3 :{Inter_ref_07_12,Inter_ref_06_12,Inter_ref_05_12,Inter_ref_04_12} <= RefFrameOutPadding; |
6'd2 :{Inter_ref_11_12,Inter_ref_10_12,Inter_ref_09_12,Inter_ref_08_12} <= RefFrameOutPadding; |
6'd1 :Inter_ref_12_12 <= RefFrameOutPadding[7:0]; |
endcase |
2'b11: |
case (blk4x4_inter_preload_counter) |
6'd52:{Inter_ref_02_00,Inter_ref_01_00,Inter_ref_00_00} <= RefFrameOutPadding[31:8]; |
6'd51:{Inter_ref_06_00,Inter_ref_05_00,Inter_ref_04_00,Inter_ref_03_00} <= RefFrameOutPadding; |
6'd50:{Inter_ref_10_00,Inter_ref_09_00,Inter_ref_08_00,Inter_ref_07_00} <= RefFrameOutPadding; |
6'd49:{Inter_ref_12_00,Inter_ref_11_00} <= RefFrameOutPadding[15:0]; |
6'd48:{Inter_ref_02_01,Inter_ref_01_01,Inter_ref_00_01} <= RefFrameOutPadding[31:8]; |
6'd47:{Inter_ref_06_01,Inter_ref_05_01,Inter_ref_04_01,Inter_ref_03_01} <= RefFrameOutPadding; |
6'd46:{Inter_ref_10_01,Inter_ref_09_01,Inter_ref_08_01,Inter_ref_07_01} <= RefFrameOutPadding; |
6'd45:{Inter_ref_12_01,Inter_ref_11_01} <= RefFrameOutPadding[15:0]; |
6'd44:{Inter_ref_02_02,Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding[31:8]; |
6'd43:{Inter_ref_06_02,Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02} <= RefFrameOutPadding; |
6'd42:{Inter_ref_10_02,Inter_ref_09_02,Inter_ref_08_02,Inter_ref_07_02} <= RefFrameOutPadding; |
6'd41:{Inter_ref_12_02,Inter_ref_11_02} <= RefFrameOutPadding[15:0]; |
6'd40:{Inter_ref_02_03,Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding[31:8]; |
6'd39:{Inter_ref_06_03,Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03} <= RefFrameOutPadding; |
6'd38:{Inter_ref_10_03,Inter_ref_09_03,Inter_ref_08_03,Inter_ref_07_03} <= RefFrameOutPadding; |
6'd37:{Inter_ref_12_03,Inter_ref_11_03} <= RefFrameOutPadding[15:0]; |
6'd36:{Inter_ref_02_04,Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding[31:8]; |
6'd35:{Inter_ref_06_04,Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04} <= RefFrameOutPadding; |
6'd34:{Inter_ref_10_04,Inter_ref_09_04,Inter_ref_08_04,Inter_ref_07_04} <= RefFrameOutPadding; |
6'd33:{Inter_ref_12_04,Inter_ref_11_04} <= RefFrameOutPadding[15:0]; |
6'd32:{Inter_ref_02_05,Inter_ref_01_05,Inter_ref_00_05} <= RefFrameOutPadding[31:8]; |
6'd31:{Inter_ref_06_05,Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05} <= RefFrameOutPadding; |
6'd30:{Inter_ref_10_05,Inter_ref_09_05,Inter_ref_08_05,Inter_ref_07_05} <= RefFrameOutPadding; |
6'd29:{Inter_ref_12_05,Inter_ref_11_05} <= RefFrameOutPadding[15:0]; |
6'd28:{Inter_ref_02_06,Inter_ref_01_06,Inter_ref_00_06} <= RefFrameOutPadding[31:8]; |
6'd27:{Inter_ref_06_06,Inter_ref_05_06,Inter_ref_04_06,Inter_ref_03_06} <= RefFrameOutPadding; |
6'd26:{Inter_ref_10_06,Inter_ref_09_06,Inter_ref_08_06,Inter_ref_07_06} <= RefFrameOutPadding; |
6'd25:{Inter_ref_12_06,Inter_ref_11_06} <= RefFrameOutPadding[15:0]; |
6'd24:{Inter_ref_02_07,Inter_ref_01_07,Inter_ref_00_07} <= RefFrameOutPadding[31:8]; |
6'd23:{Inter_ref_06_07,Inter_ref_05_07,Inter_ref_04_07,Inter_ref_03_07} <= RefFrameOutPadding; |
6'd22:{Inter_ref_10_07,Inter_ref_09_07,Inter_ref_08_07,Inter_ref_07_07} <= RefFrameOutPadding; |
6'd21:{Inter_ref_12_07,Inter_ref_11_07} <= RefFrameOutPadding[15:0]; |
6'd20:{Inter_ref_02_08,Inter_ref_01_08,Inter_ref_00_08} <= RefFrameOutPadding[31:8]; |
6'd19:{Inter_ref_06_08,Inter_ref_05_08,Inter_ref_04_08,Inter_ref_03_08} <= RefFrameOutPadding; |
6'd18:{Inter_ref_10_08,Inter_ref_09_08,Inter_ref_08_08,Inter_ref_07_08} <= RefFrameOutPadding; |
6'd17:{Inter_ref_12_08,Inter_ref_11_08} <= RefFrameOutPadding[15:0]; |
6'd16:{Inter_ref_02_09,Inter_ref_01_09,Inter_ref_00_09} <= RefFrameOutPadding[31:8]; |
6'd15:{Inter_ref_06_09,Inter_ref_05_09,Inter_ref_04_09,Inter_ref_03_09} <= RefFrameOutPadding; |
6'd14:{Inter_ref_10_09,Inter_ref_09_09,Inter_ref_08_09,Inter_ref_07_09} <= RefFrameOutPadding; |
6'd13:{Inter_ref_12_09,Inter_ref_11_09} <= RefFrameOutPadding[15:0]; |
6'd12:{Inter_ref_02_10,Inter_ref_01_10,Inter_ref_00_10} <= RefFrameOutPadding[31:8]; |
6'd11:{Inter_ref_06_10,Inter_ref_05_10,Inter_ref_04_10,Inter_ref_03_10} <= RefFrameOutPadding; |
6'd10:{Inter_ref_10_10,Inter_ref_09_10,Inter_ref_08_10,Inter_ref_07_10} <= RefFrameOutPadding; |
6'd9 :{Inter_ref_12_10,Inter_ref_11_10} <= RefFrameOutPadding[15:0]; |
6'd8 :{Inter_ref_02_11,Inter_ref_01_11,Inter_ref_00_11} <= RefFrameOutPadding[31:8]; |
6'd7 :{Inter_ref_06_11,Inter_ref_05_11,Inter_ref_04_11,Inter_ref_03_11} <= RefFrameOutPadding; |
6'd6 :{Inter_ref_10_11,Inter_ref_09_11,Inter_ref_08_11,Inter_ref_07_11} <= RefFrameOutPadding; |
6'd5 :{Inter_ref_12_11,Inter_ref_11_11} <= RefFrameOutPadding[15:0]; |
6'd4 :{Inter_ref_02_12,Inter_ref_01_12,Inter_ref_00_12} <= RefFrameOutPadding[31:8]; |
6'd3 :{Inter_ref_06_12,Inter_ref_05_12,Inter_ref_04_12,Inter_ref_03_12} <= RefFrameOutPadding; |
6'd2 :{Inter_ref_10_12,Inter_ref_09_12,Inter_ref_08_12,Inter_ref_07_12} <= RefFrameOutPadding; |
6'd1 :{Inter_ref_12_12,Inter_ref_11_12} <= RefFrameOutPadding[15:0]; |
endcase |
endcase |
`pos_d,`pos_h,`pos_n: |
case (xInt_org_unclip_1to0) |
2'b00: |
case (blk4x4_inter_preload_counter) |
6'd26:{Inter_ref_05_00,Inter_ref_04_00,Inter_ref_03_00,Inter_ref_02_00} <= RefFrameOutPadding; |
6'd25:{Inter_ref_09_00,Inter_ref_08_00,Inter_ref_07_00,Inter_ref_06_00} <= RefFrameOutPadding; |
6'd24:{Inter_ref_05_01,Inter_ref_04_01,Inter_ref_03_01,Inter_ref_02_01} <= RefFrameOutPadding; |
6'd23:{Inter_ref_09_01,Inter_ref_08_01,Inter_ref_07_01,Inter_ref_06_01} <= RefFrameOutPadding; |
6'd22:{Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding; |
6'd21:{Inter_ref_09_02,Inter_ref_08_02,Inter_ref_07_02,Inter_ref_06_02} <= RefFrameOutPadding; |
6'd20:{Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding; |
6'd19:{Inter_ref_09_03,Inter_ref_08_03,Inter_ref_07_03,Inter_ref_06_03} <= RefFrameOutPadding; |
6'd18:{Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04} <= RefFrameOutPadding; |
6'd17:{Inter_ref_09_04,Inter_ref_08_04,Inter_ref_07_04,Inter_ref_06_04} <= RefFrameOutPadding; |
6'd16:{Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05} <= RefFrameOutPadding; |
6'd15:{Inter_ref_09_05,Inter_ref_08_05,Inter_ref_07_05,Inter_ref_06_05} <= RefFrameOutPadding; |
6'd14:{Inter_ref_05_06,Inter_ref_04_06,Inter_ref_03_06,Inter_ref_02_06} <= RefFrameOutPadding; |
6'd13:{Inter_ref_09_06,Inter_ref_08_06,Inter_ref_07_06,Inter_ref_06_06} <= RefFrameOutPadding; |
6'd12:{Inter_ref_05_07,Inter_ref_04_07,Inter_ref_03_07,Inter_ref_02_07} <= RefFrameOutPadding; |
6'd11:{Inter_ref_09_07,Inter_ref_08_07,Inter_ref_07_07,Inter_ref_06_07} <= RefFrameOutPadding; |
6'd10:{Inter_ref_05_08,Inter_ref_04_08,Inter_ref_03_08,Inter_ref_02_08} <= RefFrameOutPadding; |
6'd9 :{Inter_ref_09_08,Inter_ref_08_08,Inter_ref_07_08,Inter_ref_06_08} <= RefFrameOutPadding; |
6'd8 :{Inter_ref_05_09,Inter_ref_04_09,Inter_ref_03_09,Inter_ref_02_09} <= RefFrameOutPadding; |
6'd7 :{Inter_ref_09_09,Inter_ref_08_09,Inter_ref_07_09,Inter_ref_06_09} <= RefFrameOutPadding; |
6'd6 :{Inter_ref_05_10,Inter_ref_04_10,Inter_ref_03_10,Inter_ref_02_10} <= RefFrameOutPadding; |
6'd5 :{Inter_ref_09_10,Inter_ref_08_10,Inter_ref_07_10,Inter_ref_06_10} <= RefFrameOutPadding; |
6'd4 :{Inter_ref_05_11,Inter_ref_04_11,Inter_ref_03_11,Inter_ref_02_11} <= RefFrameOutPadding; |
6'd3 :{Inter_ref_09_11,Inter_ref_08_11,Inter_ref_07_11,Inter_ref_06_11} <= RefFrameOutPadding; |
6'd2 :{Inter_ref_05_12,Inter_ref_04_12,Inter_ref_03_12,Inter_ref_02_12} <= RefFrameOutPadding; |
6'd1 :{Inter_ref_09_12,Inter_ref_08_12,Inter_ref_07_12,Inter_ref_06_12} <= RefFrameOutPadding; |
endcase |
2'b01: |
case (blk4x4_inter_preload_counter) |
6'd39:{Inter_ref_04_00,Inter_ref_03_00,Inter_ref_02_00} <= RefFrameOutPadding[31:8]; |
6'd38:{Inter_ref_08_00,Inter_ref_07_00,Inter_ref_06_00,Inter_ref_05_00} <= RefFrameOutPadding; |
6'd37:Inter_ref_09_00 <= RefFrameOutPadding[7:0]; |
6'd36:{Inter_ref_04_01,Inter_ref_03_01,Inter_ref_02_01} <= RefFrameOutPadding[31:8]; |
6'd35:{Inter_ref_08_01,Inter_ref_07_01,Inter_ref_06_01,Inter_ref_05_01} <= RefFrameOutPadding; |
6'd34:Inter_ref_09_01 <= RefFrameOutPadding[7:0]; |
6'd33:{Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding[31:8]; |
6'd32:{Inter_ref_08_02,Inter_ref_07_02,Inter_ref_06_02,Inter_ref_05_02} <= RefFrameOutPadding; |
6'd31:Inter_ref_09_02 <= RefFrameOutPadding[7:0]; |
6'd30:{Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding[31:8]; |
6'd29:{Inter_ref_08_03,Inter_ref_07_03,Inter_ref_06_03,Inter_ref_05_03} <= RefFrameOutPadding; |
6'd28:Inter_ref_09_03 <= RefFrameOutPadding[7:0]; |
6'd27:{Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04} <= RefFrameOutPadding[31:8]; |
6'd26:{Inter_ref_08_04,Inter_ref_07_04,Inter_ref_06_04,Inter_ref_05_04} <= RefFrameOutPadding; |
6'd25:Inter_ref_09_04 <= RefFrameOutPadding[7:0]; |
6'd24:{Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05} <= RefFrameOutPadding[31:8]; |
6'd23:{Inter_ref_08_05,Inter_ref_07_05,Inter_ref_06_05,Inter_ref_05_05} <= RefFrameOutPadding; |
6'd22:Inter_ref_09_05 <= RefFrameOutPadding[7:0]; |
6'd21:{Inter_ref_04_06,Inter_ref_03_06,Inter_ref_02_06} <= RefFrameOutPadding[31:8]; |
6'd20:{Inter_ref_08_06,Inter_ref_07_06,Inter_ref_06_06,Inter_ref_05_06} <= RefFrameOutPadding; |
6'd19:Inter_ref_09_06 <= RefFrameOutPadding[7:0]; |
6'd18:{Inter_ref_04_07,Inter_ref_03_07,Inter_ref_02_07} <= RefFrameOutPadding[31:8]; |
6'd17:{Inter_ref_08_07,Inter_ref_07_07,Inter_ref_06_07,Inter_ref_05_07} <= RefFrameOutPadding; |
6'd16:Inter_ref_09_07 <= RefFrameOutPadding[7:0]; |
6'd15:{Inter_ref_04_08,Inter_ref_03_08,Inter_ref_02_08} <= RefFrameOutPadding[31:8]; |
6'd14:{Inter_ref_08_08,Inter_ref_07_08,Inter_ref_06_08,Inter_ref_05_08} <= RefFrameOutPadding; |
6'd13:Inter_ref_09_08 <= RefFrameOutPadding[7:0]; |
6'd12:{Inter_ref_04_09,Inter_ref_03_09,Inter_ref_02_09} <= RefFrameOutPadding[31:8]; |
6'd11:{Inter_ref_08_09,Inter_ref_07_09,Inter_ref_06_09,Inter_ref_05_09} <= RefFrameOutPadding; |
6'd10:Inter_ref_09_09 <= RefFrameOutPadding[7:0]; |
6'd9 :{Inter_ref_04_10,Inter_ref_03_10,Inter_ref_02_10} <= RefFrameOutPadding[31:8]; |
6'd8 :{Inter_ref_08_10,Inter_ref_07_10,Inter_ref_06_10,Inter_ref_05_10} <= RefFrameOutPadding; |
6'd7 :Inter_ref_09_10 <= RefFrameOutPadding[7:0]; |
6'd6 :{Inter_ref_04_11,Inter_ref_03_11,Inter_ref_02_11} <= RefFrameOutPadding[31:8]; |
6'd5 :{Inter_ref_08_11,Inter_ref_07_11,Inter_ref_06_11,Inter_ref_05_11} <= RefFrameOutPadding; |
6'd4 :Inter_ref_09_11 <= RefFrameOutPadding[7:0]; |
6'd3 :{Inter_ref_04_12,Inter_ref_03_12,Inter_ref_02_12} <= RefFrameOutPadding[31:8]; |
6'd2 :{Inter_ref_08_12,Inter_ref_07_12,Inter_ref_06_12,Inter_ref_05_12} <= RefFrameOutPadding; |
6'd1 :Inter_ref_09_12 <= RefFrameOutPadding[7:0]; |
endcase |
2'b10: |
case (blk4x4_inter_preload_counter) |
6'd39:{Inter_ref_03_00,Inter_ref_02_00} <= RefFrameOutPadding[31:16]; |
6'd38:{Inter_ref_07_00,Inter_ref_06_00,Inter_ref_05_00,Inter_ref_04_00} <= RefFrameOutPadding; |
6'd37:{Inter_ref_09_00,Inter_ref_08_00} <= RefFrameOutPadding[15:0]; |
6'd36:{Inter_ref_03_01,Inter_ref_02_01} <= RefFrameOutPadding[31:16]; |
6'd35:{Inter_ref_07_01,Inter_ref_06_01,Inter_ref_05_01,Inter_ref_04_01} <= RefFrameOutPadding; |
6'd34:{Inter_ref_09_01,Inter_ref_08_01} <= RefFrameOutPadding[15:0]; |
6'd33:{Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding[31:16]; |
6'd32:{Inter_ref_07_02,Inter_ref_06_02,Inter_ref_05_02,Inter_ref_04_02} <= RefFrameOutPadding; |
6'd31:{Inter_ref_09_02,Inter_ref_08_02} <= RefFrameOutPadding[15:0]; |
6'd30:{Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding[31:16]; |
6'd29:{Inter_ref_07_03,Inter_ref_06_03,Inter_ref_05_03,Inter_ref_04_03} <= RefFrameOutPadding; |
6'd28:{Inter_ref_09_03,Inter_ref_08_03} <= RefFrameOutPadding[15:0]; |
6'd27:{Inter_ref_03_04,Inter_ref_02_04} <= RefFrameOutPadding[31:16]; |
6'd26:{Inter_ref_07_04,Inter_ref_06_04,Inter_ref_05_04,Inter_ref_04_04} <= RefFrameOutPadding; |
6'd25:{Inter_ref_09_04,Inter_ref_08_04} <= RefFrameOutPadding[15:0]; |
6'd24:{Inter_ref_03_05,Inter_ref_02_05} <= RefFrameOutPadding[31:16]; |
6'd23:{Inter_ref_07_05,Inter_ref_06_05,Inter_ref_05_05,Inter_ref_04_05} <= RefFrameOutPadding; |
6'd22:{Inter_ref_09_05,Inter_ref_08_05} <= RefFrameOutPadding[15:0]; |
6'd21:{Inter_ref_03_06,Inter_ref_02_06} <= RefFrameOutPadding[31:16]; |
6'd20:{Inter_ref_07_06,Inter_ref_06_06,Inter_ref_05_06,Inter_ref_04_06} <= RefFrameOutPadding; |
6'd19:{Inter_ref_09_06,Inter_ref_08_06} <= RefFrameOutPadding[15:0]; |
6'd18:{Inter_ref_03_07,Inter_ref_02_07} <= RefFrameOutPadding[31:16]; |
6'd17:{Inter_ref_07_07,Inter_ref_06_07,Inter_ref_05_07,Inter_ref_04_07} <= RefFrameOutPadding; |
6'd16:{Inter_ref_09_07,Inter_ref_08_07} <= RefFrameOutPadding[15:0]; |
6'd15:{Inter_ref_03_08,Inter_ref_02_08} <= RefFrameOutPadding[31:16]; |
6'd14:{Inter_ref_07_08,Inter_ref_06_08,Inter_ref_05_08,Inter_ref_04_08} <= RefFrameOutPadding; |
6'd13:{Inter_ref_09_08,Inter_ref_08_08} <= RefFrameOutPadding[15:0]; |
6'd12:{Inter_ref_03_09,Inter_ref_02_09} <= RefFrameOutPadding[31:16]; |
6'd11:{Inter_ref_07_09,Inter_ref_06_09,Inter_ref_05_09,Inter_ref_04_09} <= RefFrameOutPadding; |
6'd10:{Inter_ref_09_09,Inter_ref_08_09} <= RefFrameOutPadding[15:0]; |
6'd9 :{Inter_ref_03_10,Inter_ref_02_10} <= RefFrameOutPadding[31:16]; |
6'd8 :{Inter_ref_07_10,Inter_ref_06_10,Inter_ref_05_10,Inter_ref_04_10} <= RefFrameOutPadding; |
6'd7 :{Inter_ref_09_10,Inter_ref_08_10} <= RefFrameOutPadding[15:0]; |
6'd6 :{Inter_ref_03_11,Inter_ref_02_11} <= RefFrameOutPadding[31:16]; |
6'd5 :{Inter_ref_07_11,Inter_ref_06_11,Inter_ref_05_11,Inter_ref_04_11} <= RefFrameOutPadding; |
6'd4 :{Inter_ref_09_11,Inter_ref_08_11} <= RefFrameOutPadding[15:0]; |
6'd3 :{Inter_ref_03_12,Inter_ref_02_12} <= RefFrameOutPadding[31:16]; |
6'd2 :{Inter_ref_07_12,Inter_ref_06_12,Inter_ref_05_12,Inter_ref_04_12} <= RefFrameOutPadding; |
6'd1 :{Inter_ref_09_12,Inter_ref_08_12} <= RefFrameOutPadding[15:0]; |
endcase |
2'b11: |
case (blk4x4_inter_preload_counter) |
6'd39:{Inter_ref_02_00} <= RefFrameOutPadding[31:24]; |
6'd38:{Inter_ref_06_00,Inter_ref_05_00,Inter_ref_04_00,Inter_ref_03_00} <= RefFrameOutPadding; |
6'd37:{Inter_ref_09_00,Inter_ref_08_00,Inter_ref_07_00} <= RefFrameOutPadding[23:0]; |
6'd36:{Inter_ref_02_01} <= RefFrameOutPadding[31:24]; |
6'd35:{Inter_ref_06_01,Inter_ref_05_01,Inter_ref_04_01,Inter_ref_03_01} <= RefFrameOutPadding; |
6'd34:{Inter_ref_09_01,Inter_ref_08_01,Inter_ref_07_01} <= RefFrameOutPadding[23:0]; |
6'd33:{Inter_ref_02_02} <= RefFrameOutPadding[31:24]; |
6'd32:{Inter_ref_06_02,Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02} <= RefFrameOutPadding; |
6'd31:{Inter_ref_09_02,Inter_ref_08_02,Inter_ref_07_02} <= RefFrameOutPadding[23:0]; |
6'd30:{Inter_ref_02_03} <= RefFrameOutPadding[31:24]; |
6'd29:{Inter_ref_06_03,Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03} <= RefFrameOutPadding; |
6'd28:{Inter_ref_09_03,Inter_ref_08_03,Inter_ref_07_03} <= RefFrameOutPadding[23:0]; |
6'd27:{Inter_ref_02_04} <= RefFrameOutPadding[31:24]; |
6'd26:{Inter_ref_06_04,Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04} <= RefFrameOutPadding; |
6'd25:{Inter_ref_09_04,Inter_ref_08_04,Inter_ref_07_04} <= RefFrameOutPadding[23:0]; |
6'd24:{Inter_ref_02_05} <= RefFrameOutPadding[31:24]; |
6'd23:{Inter_ref_06_05,Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05} <= RefFrameOutPadding; |
6'd22:{Inter_ref_09_05,Inter_ref_08_05,Inter_ref_07_05} <= RefFrameOutPadding[23:0]; |
6'd21:{Inter_ref_02_06} <= RefFrameOutPadding[31:24]; |
6'd20:{Inter_ref_06_06,Inter_ref_05_06,Inter_ref_04_06,Inter_ref_03_06} <= RefFrameOutPadding; |
6'd19:{Inter_ref_09_06,Inter_ref_08_06,Inter_ref_07_06} <= RefFrameOutPadding[23:0]; |
6'd18:{Inter_ref_02_07} <= RefFrameOutPadding[31:24]; |
6'd17:{Inter_ref_06_07,Inter_ref_05_07,Inter_ref_04_07,Inter_ref_03_07} <= RefFrameOutPadding; |
6'd16:{Inter_ref_09_07,Inter_ref_08_07,Inter_ref_07_07} <= RefFrameOutPadding[23:0]; |
6'd15:{Inter_ref_02_08} <= RefFrameOutPadding[31:24]; |
6'd14:{Inter_ref_06_08,Inter_ref_05_08,Inter_ref_04_08,Inter_ref_03_08} <= RefFrameOutPadding; |
6'd13:{Inter_ref_09_08,Inter_ref_08_08,Inter_ref_07_08} <= RefFrameOutPadding[23:0]; |
6'd12:{Inter_ref_02_09} <= RefFrameOutPadding[31:24]; |
6'd11:{Inter_ref_06_09,Inter_ref_05_09,Inter_ref_04_09,Inter_ref_03_09} <= RefFrameOutPadding; |
6'd10:{Inter_ref_09_09,Inter_ref_08_09,Inter_ref_07_09} <= RefFrameOutPadding[23:0]; |
6'd9 :{Inter_ref_02_10} <= RefFrameOutPadding[31:24]; |
6'd8 :{Inter_ref_06_10,Inter_ref_05_10,Inter_ref_04_10,Inter_ref_03_10} <= RefFrameOutPadding; |
6'd7 :{Inter_ref_09_10,Inter_ref_08_10,Inter_ref_07_10} <= RefFrameOutPadding[23:0]; |
6'd6 :{Inter_ref_02_11} <= RefFrameOutPadding[31:24]; |
6'd5 :{Inter_ref_06_11,Inter_ref_05_11,Inter_ref_04_11,Inter_ref_03_11} <= RefFrameOutPadding; |
6'd4 :{Inter_ref_09_11,Inter_ref_08_11,Inter_ref_07_11} <= RefFrameOutPadding[23:0]; |
6'd3 :{Inter_ref_02_12} <= RefFrameOutPadding[31:24]; |
6'd2 :{Inter_ref_06_12,Inter_ref_05_12,Inter_ref_04_12,Inter_ref_03_12} <= RefFrameOutPadding; |
6'd1 :{Inter_ref_09_12,Inter_ref_08_12,Inter_ref_07_12} <= RefFrameOutPadding[23:0]; |
endcase |
endcase |
`pos_a,`pos_b,`pos_c: |
case (xInt_org_unclip_1to0) |
2'b00: |
case (blk4x4_inter_preload_counter) |
6'd32:{Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding[31:16]; |
6'd31:{Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding; |
6'd30:{Inter_ref_09_02,Inter_ref_08_02,Inter_ref_07_02,Inter_ref_06_02} <= RefFrameOutPadding; |
6'd29:{Inter_ref_12_02,Inter_ref_11_02,Inter_ref_10_02} <= RefFrameOutPadding[23:0]; |
6'd28:{Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding[31:16]; |
6'd27:{Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding; |
6'd26:{Inter_ref_09_03,Inter_ref_08_03,Inter_ref_07_03,Inter_ref_06_03} <= RefFrameOutPadding; |
6'd25:{Inter_ref_12_03,Inter_ref_11_03,Inter_ref_10_03} <= RefFrameOutPadding[23:0]; |
6'd24:{Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding[31:16]; |
6'd23:{Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04} <= RefFrameOutPadding; |
6'd22:{Inter_ref_09_04,Inter_ref_08_04,Inter_ref_07_04,Inter_ref_06_04} <= RefFrameOutPadding; |
6'd21:{Inter_ref_12_04,Inter_ref_11_04,Inter_ref_10_04} <= RefFrameOutPadding[23:0]; |
6'd20:{Inter_ref_01_05,Inter_ref_00_05} <= RefFrameOutPadding[31:16]; |
6'd19:{Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05} <= RefFrameOutPadding; |
6'd18:{Inter_ref_09_05,Inter_ref_08_05,Inter_ref_07_05,Inter_ref_06_05} <= RefFrameOutPadding; |
6'd17:{Inter_ref_12_05,Inter_ref_11_05,Inter_ref_10_05} <= RefFrameOutPadding[23:0]; |
6'd16:{Inter_ref_01_06,Inter_ref_00_06} <= RefFrameOutPadding[31:16]; |
6'd15:{Inter_ref_05_06,Inter_ref_04_06,Inter_ref_03_06,Inter_ref_02_06} <= RefFrameOutPadding; |
6'd14:{Inter_ref_09_06,Inter_ref_08_06,Inter_ref_07_06,Inter_ref_06_06} <= RefFrameOutPadding; |
6'd13:{Inter_ref_12_06,Inter_ref_11_06,Inter_ref_10_06} <= RefFrameOutPadding[23:0]; |
6'd12:{Inter_ref_01_07,Inter_ref_00_07} <= RefFrameOutPadding[31:16]; |
6'd11:{Inter_ref_05_07,Inter_ref_04_07,Inter_ref_03_07,Inter_ref_02_07} <= RefFrameOutPadding; |
6'd10:{Inter_ref_09_07,Inter_ref_08_07,Inter_ref_07_07,Inter_ref_06_07} <= RefFrameOutPadding; |
6'd9 :{Inter_ref_12_07,Inter_ref_11_07,Inter_ref_10_07} <= RefFrameOutPadding[23:0]; |
6'd8 :{Inter_ref_01_08,Inter_ref_00_08} <= RefFrameOutPadding[31:16]; |
6'd7 :{Inter_ref_05_08,Inter_ref_04_08,Inter_ref_03_08,Inter_ref_02_08} <= RefFrameOutPadding; |
6'd6 :{Inter_ref_09_08,Inter_ref_08_08,Inter_ref_07_08,Inter_ref_06_08} <= RefFrameOutPadding; |
6'd5 :{Inter_ref_12_08,Inter_ref_11_08,Inter_ref_10_08} <= RefFrameOutPadding[23:0]; |
6'd4 :{Inter_ref_01_09,Inter_ref_00_09} <= RefFrameOutPadding[31:16]; |
6'd3 :{Inter_ref_05_09,Inter_ref_04_09,Inter_ref_03_09,Inter_ref_02_09} <= RefFrameOutPadding; |
6'd2 :{Inter_ref_09_09,Inter_ref_08_09,Inter_ref_07_09,Inter_ref_06_09} <= RefFrameOutPadding; |
6'd1 :{Inter_ref_12_09,Inter_ref_11_09,Inter_ref_10_09} <= RefFrameOutPadding[23:0]; |
endcase |
2'b01: |
case (blk4x4_inter_preload_counter) |
6'd32:Inter_ref_00_02 <= RefFrameOutPadding[31:24]; |
6'd31:{Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02,Inter_ref_01_02} <= RefFrameOutPadding; |
6'd30:{Inter_ref_08_02,Inter_ref_07_02,Inter_ref_06_02,Inter_ref_05_02} <= RefFrameOutPadding; |
6'd29:{Inter_ref_12_02,Inter_ref_11_02,Inter_ref_10_02,Inter_ref_09_02} <= RefFrameOutPadding; |
6'd28:Inter_ref_00_03 <= RefFrameOutPadding[31:24]; |
6'd27:{Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03,Inter_ref_01_03} <= RefFrameOutPadding; |
6'd26:{Inter_ref_08_03,Inter_ref_07_03,Inter_ref_06_03,Inter_ref_05_03} <= RefFrameOutPadding; |
6'd25:{Inter_ref_12_03,Inter_ref_11_03,Inter_ref_10_03,Inter_ref_09_03} <= RefFrameOutPadding; |
6'd24:Inter_ref_00_04 <= RefFrameOutPadding[31:24]; |
6'd23:{Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04,Inter_ref_01_04} <= RefFrameOutPadding; |
6'd22:{Inter_ref_08_04,Inter_ref_07_04,Inter_ref_06_04,Inter_ref_05_04} <= RefFrameOutPadding; |
6'd21:{Inter_ref_12_04,Inter_ref_11_04,Inter_ref_10_04,Inter_ref_09_04} <= RefFrameOutPadding; |
6'd20:Inter_ref_00_05 <= RefFrameOutPadding[31:24]; |
6'd19:{Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05,Inter_ref_01_05} <= RefFrameOutPadding; |
6'd18:{Inter_ref_08_05,Inter_ref_07_05,Inter_ref_06_05,Inter_ref_05_05} <= RefFrameOutPadding; |
6'd17:{Inter_ref_12_05,Inter_ref_11_05,Inter_ref_10_05,Inter_ref_09_05} <= RefFrameOutPadding; |
6'd16:Inter_ref_00_06 <= RefFrameOutPadding[31:24]; |
6'd15:{Inter_ref_04_06,Inter_ref_03_06,Inter_ref_02_06,Inter_ref_01_06} <= RefFrameOutPadding; |
6'd14:{Inter_ref_08_06,Inter_ref_07_06,Inter_ref_06_06,Inter_ref_05_06} <= RefFrameOutPadding; |
6'd13:{Inter_ref_12_06,Inter_ref_11_06,Inter_ref_10_06,Inter_ref_09_06} <= RefFrameOutPadding; |
6'd12:Inter_ref_00_07 <= RefFrameOutPadding[31:24]; |
6'd11:{Inter_ref_04_07,Inter_ref_03_07,Inter_ref_02_07,Inter_ref_01_07} <= RefFrameOutPadding; |
6'd10:{Inter_ref_08_07,Inter_ref_07_07,Inter_ref_06_07,Inter_ref_05_07} <= RefFrameOutPadding; |
6'd9 :{Inter_ref_12_07,Inter_ref_11_07,Inter_ref_10_07,Inter_ref_09_07} <= RefFrameOutPadding; |
6'd8 :Inter_ref_00_08 <= RefFrameOutPadding[31:24]; |
6'd7 :{Inter_ref_04_08,Inter_ref_03_08,Inter_ref_02_08,Inter_ref_01_08} <= RefFrameOutPadding; |
6'd6 :{Inter_ref_08_08,Inter_ref_07_08,Inter_ref_06_08,Inter_ref_05_08} <= RefFrameOutPadding; |
6'd5 :{Inter_ref_12_08,Inter_ref_11_08,Inter_ref_10_08,Inter_ref_09_08} <= RefFrameOutPadding; |
6'd4 :Inter_ref_00_09 <= RefFrameOutPadding[31:24]; |
6'd3 :{Inter_ref_04_09,Inter_ref_03_09,Inter_ref_02_09,Inter_ref_01_09} <= RefFrameOutPadding; |
6'd2 :{Inter_ref_08_09,Inter_ref_07_09,Inter_ref_06_09,Inter_ref_05_09} <= RefFrameOutPadding; |
6'd1 :{Inter_ref_12_09,Inter_ref_11_09,Inter_ref_10_09,Inter_ref_09_09} <= RefFrameOutPadding; |
endcase |
2'b10: |
case (blk4x4_inter_preload_counter) |
6'd32:{Inter_ref_03_02,Inter_ref_02_02,Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding; |
6'd31:{Inter_ref_07_02,Inter_ref_06_02,Inter_ref_05_02,Inter_ref_04_02} <= RefFrameOutPadding; |
6'd30:{Inter_ref_11_02,Inter_ref_10_02,Inter_ref_09_02,Inter_ref_08_02} <= RefFrameOutPadding; |
6'd29:Inter_ref_12_02 <= RefFrameOutPadding[7:0]; |
6'd28:{Inter_ref_03_03,Inter_ref_02_03,Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding; |
6'd27:{Inter_ref_07_03,Inter_ref_06_03,Inter_ref_05_03,Inter_ref_04_03} <= RefFrameOutPadding; |
6'd26:{Inter_ref_11_03,Inter_ref_10_03,Inter_ref_09_03,Inter_ref_08_03} <= RefFrameOutPadding; |
6'd25:Inter_ref_12_03 <= RefFrameOutPadding[7:0]; |
6'd24:{Inter_ref_03_04,Inter_ref_02_04,Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding; |
6'd23:{Inter_ref_07_04,Inter_ref_06_04,Inter_ref_05_04,Inter_ref_04_04} <= RefFrameOutPadding; |
6'd22:{Inter_ref_11_04,Inter_ref_10_04,Inter_ref_09_04,Inter_ref_08_04} <= RefFrameOutPadding; |
6'd21:Inter_ref_12_04 <= RefFrameOutPadding[7:0]; |
6'd20:{Inter_ref_03_05,Inter_ref_02_05,Inter_ref_01_05,Inter_ref_00_05} <= RefFrameOutPadding; |
6'd19:{Inter_ref_07_05,Inter_ref_06_05,Inter_ref_05_05,Inter_ref_04_05} <= RefFrameOutPadding; |
6'd18:{Inter_ref_11_05,Inter_ref_10_05,Inter_ref_09_05,Inter_ref_08_05} <= RefFrameOutPadding; |
6'd17:Inter_ref_12_05 <= RefFrameOutPadding[7:0]; |
6'd16:{Inter_ref_03_06,Inter_ref_02_06,Inter_ref_01_06,Inter_ref_00_06} <= RefFrameOutPadding; |
6'd15:{Inter_ref_07_06,Inter_ref_06_06,Inter_ref_05_06,Inter_ref_04_06} <= RefFrameOutPadding; |
6'd14:{Inter_ref_11_06,Inter_ref_10_06,Inter_ref_09_06,Inter_ref_08_06} <= RefFrameOutPadding; |
6'd13:Inter_ref_12_06 <= RefFrameOutPadding[7:0]; |
6'd12:{Inter_ref_03_07,Inter_ref_02_07,Inter_ref_01_07,Inter_ref_00_07} <= RefFrameOutPadding; |
6'd11:{Inter_ref_07_07,Inter_ref_06_07,Inter_ref_05_07,Inter_ref_04_07} <= RefFrameOutPadding; |
6'd10:{Inter_ref_11_07,Inter_ref_10_07,Inter_ref_09_07,Inter_ref_08_07} <= RefFrameOutPadding; |
6'd9 :Inter_ref_12_07 <= RefFrameOutPadding[7:0]; |
6'd8 :{Inter_ref_03_08,Inter_ref_02_08,Inter_ref_01_08,Inter_ref_00_08} <= RefFrameOutPadding; |
6'd7 :{Inter_ref_07_08,Inter_ref_06_08,Inter_ref_05_08,Inter_ref_04_08} <= RefFrameOutPadding; |
6'd6 :{Inter_ref_11_08,Inter_ref_10_08,Inter_ref_09_08,Inter_ref_08_08} <= RefFrameOutPadding; |
6'd5 :Inter_ref_12_08 <= RefFrameOutPadding[7:0]; |
6'd4 :{Inter_ref_03_09,Inter_ref_02_09,Inter_ref_01_09,Inter_ref_00_09} <= RefFrameOutPadding; |
6'd3 :{Inter_ref_07_09,Inter_ref_06_09,Inter_ref_05_09,Inter_ref_04_09} <= RefFrameOutPadding; |
6'd2 :{Inter_ref_11_09,Inter_ref_10_09,Inter_ref_09_09,Inter_ref_08_09} <= RefFrameOutPadding; |
6'd1 :Inter_ref_12_09 <= RefFrameOutPadding[7:0]; |
endcase |
2'b11: |
case (blk4x4_inter_preload_counter) |
6'd32:{Inter_ref_02_02,Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding[31:8]; |
6'd31:{Inter_ref_06_02,Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02} <= RefFrameOutPadding; |
6'd30:{Inter_ref_10_02,Inter_ref_09_02,Inter_ref_08_02,Inter_ref_07_02} <= RefFrameOutPadding; |
6'd29:{Inter_ref_12_02,Inter_ref_11_02} <= RefFrameOutPadding[15:0]; |
6'd28:{Inter_ref_02_03,Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding[31:8]; |
6'd27:{Inter_ref_06_03,Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03} <= RefFrameOutPadding; |
6'd26:{Inter_ref_10_03,Inter_ref_09_03,Inter_ref_08_03,Inter_ref_07_03} <= RefFrameOutPadding; |
6'd25:{Inter_ref_12_03,Inter_ref_11_03} <= RefFrameOutPadding[15:0]; |
6'd24:{Inter_ref_02_04,Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding[31:8]; |
6'd23:{Inter_ref_06_04,Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04} <= RefFrameOutPadding; |
6'd22:{Inter_ref_10_04,Inter_ref_09_04,Inter_ref_08_04,Inter_ref_07_04} <= RefFrameOutPadding; |
6'd21:{Inter_ref_12_04,Inter_ref_11_04} <= RefFrameOutPadding[15:0]; |
6'd20:{Inter_ref_02_05,Inter_ref_01_05,Inter_ref_00_05} <= RefFrameOutPadding[31:8]; |
6'd19:{Inter_ref_06_05,Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05} <= RefFrameOutPadding; |
6'd18:{Inter_ref_10_05,Inter_ref_09_05,Inter_ref_08_05,Inter_ref_07_05} <= RefFrameOutPadding; |
6'd17:{Inter_ref_12_05,Inter_ref_11_05} <= RefFrameOutPadding[15:0]; |
6'd16:{Inter_ref_02_06,Inter_ref_01_06,Inter_ref_00_06} <= RefFrameOutPadding[31:8]; |
6'd15:{Inter_ref_06_06,Inter_ref_05_06,Inter_ref_04_06,Inter_ref_03_06} <= RefFrameOutPadding; |
6'd14:{Inter_ref_10_06,Inter_ref_09_06,Inter_ref_08_06,Inter_ref_07_06} <= RefFrameOutPadding; |
6'd13:{Inter_ref_12_06,Inter_ref_11_06} <= RefFrameOutPadding[15:0]; |
6'd12:{Inter_ref_02_07,Inter_ref_01_07,Inter_ref_00_07} <= RefFrameOutPadding[31:8]; |
6'd11:{Inter_ref_06_07,Inter_ref_05_07,Inter_ref_04_07,Inter_ref_03_07} <= RefFrameOutPadding; |
6'd10:{Inter_ref_10_07,Inter_ref_09_07,Inter_ref_08_07,Inter_ref_07_07} <= RefFrameOutPadding; |
6'd9 :{Inter_ref_12_07,Inter_ref_11_07} <= RefFrameOutPadding[15:0]; |
6'd8 :{Inter_ref_02_08,Inter_ref_01_08,Inter_ref_00_08} <= RefFrameOutPadding[31:8]; |
6'd7 :{Inter_ref_06_08,Inter_ref_05_08,Inter_ref_04_08,Inter_ref_03_08} <= RefFrameOutPadding; |
6'd6 :{Inter_ref_10_08,Inter_ref_09_08,Inter_ref_08_08,Inter_ref_07_08} <= RefFrameOutPadding; |
6'd5 :{Inter_ref_12_08,Inter_ref_11_08} <= RefFrameOutPadding[15:0]; |
6'd4 :{Inter_ref_02_09,Inter_ref_01_09,Inter_ref_00_09} <= RefFrameOutPadding[31:8]; |
6'd3 :{Inter_ref_06_09,Inter_ref_05_09,Inter_ref_04_09,Inter_ref_03_09} <= RefFrameOutPadding; |
6'd2 :{Inter_ref_10_09,Inter_ref_09_09,Inter_ref_08_09,Inter_ref_07_09} <= RefFrameOutPadding; |
6'd1 :{Inter_ref_12_09,Inter_ref_11_09} <= RefFrameOutPadding[15:0]; |
endcase |
endcase |
`pos_Int: |
case (xInt_org_unclip_1to0) |
2'b00: |
case (blk4x4_inter_preload_counter) |
6'd16:{Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding; |
6'd15:{Inter_ref_09_02,Inter_ref_08_02,Inter_ref_07_02,Inter_ref_06_02} <= RefFrameOutPadding; |
6'd14:{Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding; |
6'd13:{Inter_ref_09_03,Inter_ref_08_03,Inter_ref_07_03,Inter_ref_06_03} <= RefFrameOutPadding; |
6'd12:{Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04} <= RefFrameOutPadding; |
6'd11:{Inter_ref_09_04,Inter_ref_08_04,Inter_ref_07_04,Inter_ref_06_04} <= RefFrameOutPadding; |
6'd10:{Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05} <= RefFrameOutPadding; |
6'd9 :{Inter_ref_09_05,Inter_ref_08_05,Inter_ref_07_05,Inter_ref_06_05} <= RefFrameOutPadding; |
6'd8 :{Inter_ref_05_06,Inter_ref_04_06,Inter_ref_03_06,Inter_ref_02_06} <= RefFrameOutPadding; |
6'd7 :{Inter_ref_09_06,Inter_ref_08_06,Inter_ref_07_06,Inter_ref_06_06} <= RefFrameOutPadding; |
6'd6 :{Inter_ref_05_07,Inter_ref_04_07,Inter_ref_03_07,Inter_ref_02_07} <= RefFrameOutPadding; |
6'd5 :{Inter_ref_09_07,Inter_ref_08_07,Inter_ref_07_07,Inter_ref_06_07} <= RefFrameOutPadding; |
6'd4 :{Inter_ref_05_08,Inter_ref_04_08,Inter_ref_03_08,Inter_ref_02_08} <= RefFrameOutPadding; |
6'd3 :{Inter_ref_09_08,Inter_ref_08_08,Inter_ref_07_08,Inter_ref_06_08} <= RefFrameOutPadding; |
6'd2 :{Inter_ref_05_09,Inter_ref_04_09,Inter_ref_03_09,Inter_ref_02_09} <= RefFrameOutPadding; |
6'd1 :{Inter_ref_09_09,Inter_ref_08_09,Inter_ref_07_09,Inter_ref_06_09} <= RefFrameOutPadding; |
endcase |
2'b01: |
case (blk4x4_inter_preload_counter) |
6'd24:{Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding[31:8]; |
6'd23:{Inter_ref_08_02,Inter_ref_07_02,Inter_ref_06_02,Inter_ref_05_02} <= RefFrameOutPadding; |
6'd22:Inter_ref_09_02 <= RefFrameOutPadding[7:0]; |
6'd21:{Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding[31:8]; |
6'd20:{Inter_ref_08_03,Inter_ref_07_03,Inter_ref_06_03,Inter_ref_05_03} <= RefFrameOutPadding; |
6'd19:Inter_ref_09_03 <= RefFrameOutPadding[7:0]; |
6'd18:{Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04} <= RefFrameOutPadding[31:8]; |
6'd17:{Inter_ref_08_04,Inter_ref_07_04,Inter_ref_06_04,Inter_ref_05_04} <= RefFrameOutPadding; |
6'd16:Inter_ref_09_04 <= RefFrameOutPadding[7:0]; |
6'd15:{Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05} <= RefFrameOutPadding[31:8]; |
6'd14:{Inter_ref_08_05,Inter_ref_07_05,Inter_ref_06_05,Inter_ref_05_05} <= RefFrameOutPadding; |
6'd13:Inter_ref_09_05 <= RefFrameOutPadding[7:0]; |
6'd12:{Inter_ref_04_06,Inter_ref_03_06,Inter_ref_02_06} <= RefFrameOutPadding[31:8]; |
6'd11:{Inter_ref_08_06,Inter_ref_07_06,Inter_ref_06_06,Inter_ref_05_06} <= RefFrameOutPadding; |
6'd10:Inter_ref_09_06 <= RefFrameOutPadding[7:0]; |
6'd9 :{Inter_ref_04_07,Inter_ref_03_07,Inter_ref_02_07} <= RefFrameOutPadding[31:8]; |
6'd8 :{Inter_ref_08_07,Inter_ref_07_07,Inter_ref_06_07,Inter_ref_05_07} <= RefFrameOutPadding; |
6'd7 :Inter_ref_09_07 <= RefFrameOutPadding[7:0]; |
6'd6 :{Inter_ref_04_08,Inter_ref_03_08,Inter_ref_02_08} <= RefFrameOutPadding[31:8]; |
6'd5 :{Inter_ref_08_08,Inter_ref_07_08,Inter_ref_06_08,Inter_ref_05_08} <= RefFrameOutPadding; |
6'd4 :Inter_ref_09_08 <= RefFrameOutPadding[7:0]; |
6'd3 :{Inter_ref_04_09,Inter_ref_03_09,Inter_ref_02_09} <= RefFrameOutPadding[31:8]; |
6'd2 :{Inter_ref_08_09,Inter_ref_07_09,Inter_ref_06_09,Inter_ref_05_09} <= RefFrameOutPadding; |
6'd1 :Inter_ref_09_09 <= RefFrameOutPadding[7:0]; |
endcase |
2'b10: |
case (blk4x4_inter_preload_counter) |
6'd24:{Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding[31:16]; |
6'd23:{Inter_ref_07_02,Inter_ref_06_02,Inter_ref_05_02,Inter_ref_04_02} <= RefFrameOutPadding; |
6'd22:{Inter_ref_09_02,Inter_ref_08_02} <= RefFrameOutPadding[15:0]; |
6'd21:{Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding[31:16]; |
6'd20:{Inter_ref_07_03,Inter_ref_06_03,Inter_ref_05_03,Inter_ref_04_03} <= RefFrameOutPadding; |
6'd19:{Inter_ref_09_03,Inter_ref_08_03} <= RefFrameOutPadding[15:0]; |
6'd18:{Inter_ref_03_04,Inter_ref_02_04} <= RefFrameOutPadding[31:16]; |
6'd17:{Inter_ref_07_04,Inter_ref_06_04,Inter_ref_05_04,Inter_ref_04_04} <= RefFrameOutPadding; |
6'd16:{Inter_ref_09_04,Inter_ref_08_04} <= RefFrameOutPadding[15:0]; |
6'd15:{Inter_ref_03_05,Inter_ref_02_05} <= RefFrameOutPadding[31:16]; |
6'd14:{Inter_ref_07_05,Inter_ref_06_05,Inter_ref_05_05,Inter_ref_04_05} <= RefFrameOutPadding; |
6'd13:{Inter_ref_09_05,Inter_ref_08_05} <= RefFrameOutPadding[15:0]; |
6'd12:{Inter_ref_03_06,Inter_ref_02_06} <= RefFrameOutPadding[31:16]; |
6'd11:{Inter_ref_07_06,Inter_ref_06_06,Inter_ref_05_06,Inter_ref_04_06} <= RefFrameOutPadding; |
6'd10:{Inter_ref_09_06,Inter_ref_08_06} <= RefFrameOutPadding[15:0]; |
6'd9 :{Inter_ref_03_07,Inter_ref_02_07} <= RefFrameOutPadding[31:16]; |
6'd8 :{Inter_ref_07_07,Inter_ref_06_07,Inter_ref_05_07,Inter_ref_04_07} <= RefFrameOutPadding; |
6'd7 :{Inter_ref_09_07,Inter_ref_08_07} <= RefFrameOutPadding[15:0]; |
6'd6 :{Inter_ref_03_08,Inter_ref_02_08} <= RefFrameOutPadding[31:16]; |
6'd5 :{Inter_ref_07_08,Inter_ref_06_08,Inter_ref_05_08,Inter_ref_04_08} <= RefFrameOutPadding; |
6'd4 :{Inter_ref_09_08,Inter_ref_08_08} <= RefFrameOutPadding[15:0]; |
6'd3 :{Inter_ref_03_09,Inter_ref_02_09} <= RefFrameOutPadding[31:16]; |
6'd2 :{Inter_ref_07_09,Inter_ref_06_09,Inter_ref_05_09,Inter_ref_04_09} <= RefFrameOutPadding; |
6'd1 :{Inter_ref_09_09,Inter_ref_08_09} <= RefFrameOutPadding[15:0]; |
endcase |
2'b11: |
case (blk4x4_inter_preload_counter) |
6'd24:{Inter_ref_02_02} <= RefFrameOutPadding[31:24]; |
6'd23:{Inter_ref_06_02,Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02} <= RefFrameOutPadding; |
6'd22:{Inter_ref_09_02,Inter_ref_08_02,Inter_ref_07_02} <= RefFrameOutPadding[23:0]; |
6'd21:{Inter_ref_02_03} <= RefFrameOutPadding[31:24]; |
6'd20:{Inter_ref_06_03,Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03} <= RefFrameOutPadding; |
6'd19:{Inter_ref_09_03,Inter_ref_08_03,Inter_ref_07_03} <= RefFrameOutPadding[23:0]; |
6'd18:{Inter_ref_02_04} <= RefFrameOutPadding[31:24]; |
6'd17:{Inter_ref_06_04,Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04} <= RefFrameOutPadding; |
6'd16:{Inter_ref_09_04,Inter_ref_08_04,Inter_ref_07_04} <= RefFrameOutPadding[23:0]; |
6'd15:{Inter_ref_02_05} <= RefFrameOutPadding[31:24]; |
6'd14:{Inter_ref_06_05,Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05} <= RefFrameOutPadding; |
6'd13:{Inter_ref_09_05,Inter_ref_08_05,Inter_ref_07_05} <= RefFrameOutPadding[23:0]; |
6'd12:{Inter_ref_02_06} <= RefFrameOutPadding[31:24]; |
6'd11:{Inter_ref_06_06,Inter_ref_05_06,Inter_ref_04_06,Inter_ref_03_06} <= RefFrameOutPadding; |
6'd10:{Inter_ref_09_06,Inter_ref_08_06,Inter_ref_07_06} <= RefFrameOutPadding[23:0]; |
6'd9 :{Inter_ref_02_07} <= RefFrameOutPadding[31:24]; |
6'd8 :{Inter_ref_06_07,Inter_ref_05_07,Inter_ref_04_07,Inter_ref_03_07} <= RefFrameOutPadding; |
6'd7 :{Inter_ref_09_07,Inter_ref_08_07,Inter_ref_07_07} <= RefFrameOutPadding[23:0]; |
6'd6 :{Inter_ref_02_08} <= RefFrameOutPadding[31:24]; |
6'd5 :{Inter_ref_06_08,Inter_ref_05_08,Inter_ref_04_08,Inter_ref_03_08} <= RefFrameOutPadding; |
6'd4 :{Inter_ref_09_08,Inter_ref_08_08,Inter_ref_07_08} <= RefFrameOutPadding[23:0]; |
6'd3 :{Inter_ref_02_09} <= RefFrameOutPadding[31:24]; |
6'd2 :{Inter_ref_06_09,Inter_ref_05_09,Inter_ref_04_09,Inter_ref_03_09} <= RefFrameOutPadding; |
6'd1 :{Inter_ref_09_09,Inter_ref_08_09,Inter_ref_07_09} <= RefFrameOutPadding[23:0]; |
endcase |
endcase |
`pos_e,`pos_g,`pos_p,`pos_r: |
case (xInt_org_unclip_1to0) |
2'b00: |
case (blk4x4_inter_preload_counter) |
6'd48:{Inter_ref_05_00,Inter_ref_04_00,Inter_ref_03_00,Inter_ref_02_00} <= RefFrameOutPadding; |
6'd47:{Inter_ref_09_00,Inter_ref_08_00,Inter_ref_07_00,Inter_ref_06_00} <= RefFrameOutPadding; |
6'd46:Inter_ref_10_00 <= RefFrameOutPadding[7:0]; |
6'd45:{Inter_ref_05_01,Inter_ref_04_01,Inter_ref_03_01,Inter_ref_02_01} <= RefFrameOutPadding; |
6'd44:{Inter_ref_09_01,Inter_ref_08_01,Inter_ref_07_01,Inter_ref_06_01} <= RefFrameOutPadding; |
6'd43:Inter_ref_10_01 <= RefFrameOutPadding[7:0]; |
|
6'd42:{Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding[31:16]; |
6'd41:{Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding; |
6'd40:{Inter_ref_09_02,Inter_ref_08_02,Inter_ref_07_02,Inter_ref_06_02} <= RefFrameOutPadding; |
6'd39:{Inter_ref_12_02,Inter_ref_11_02,Inter_ref_10_02} <= RefFrameOutPadding[23:0]; |
6'd38:{Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding[31:16]; |
6'd37:{Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding; |
6'd36:{Inter_ref_09_03,Inter_ref_08_03,Inter_ref_07_03,Inter_ref_06_03} <= RefFrameOutPadding; |
6'd35:{Inter_ref_12_03,Inter_ref_11_03,Inter_ref_10_03} <= RefFrameOutPadding[23:0]; |
6'd34:{Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding[31:16]; |
6'd33:{Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04} <= RefFrameOutPadding; |
6'd32:{Inter_ref_09_04,Inter_ref_08_04,Inter_ref_07_04,Inter_ref_06_04} <= RefFrameOutPadding; |
6'd31:{Inter_ref_12_04,Inter_ref_11_04,Inter_ref_10_04} <= RefFrameOutPadding[23:0]; |
6'd30:{Inter_ref_01_05,Inter_ref_00_05} <= RefFrameOutPadding[31:16]; |
6'd29:{Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05} <= RefFrameOutPadding; |
6'd28:{Inter_ref_09_05,Inter_ref_08_05,Inter_ref_07_05,Inter_ref_06_05} <= RefFrameOutPadding; |
6'd27:{Inter_ref_12_05,Inter_ref_11_05,Inter_ref_10_05} <= RefFrameOutPadding[23:0]; |
6'd26:{Inter_ref_01_06,Inter_ref_00_06} <= RefFrameOutPadding[31:16]; |
6'd25:{Inter_ref_05_06,Inter_ref_04_06,Inter_ref_03_06,Inter_ref_02_06} <= RefFrameOutPadding; |
6'd24:{Inter_ref_09_06,Inter_ref_08_06,Inter_ref_07_06,Inter_ref_06_06} <= RefFrameOutPadding; |
6'd23:{Inter_ref_12_06,Inter_ref_11_06,Inter_ref_10_06} <= RefFrameOutPadding[23:0]; |
6'd22:{Inter_ref_01_07,Inter_ref_00_07} <= RefFrameOutPadding[31:16]; |
6'd21:{Inter_ref_05_07,Inter_ref_04_07,Inter_ref_03_07,Inter_ref_02_07} <= RefFrameOutPadding; |
6'd20:{Inter_ref_09_07,Inter_ref_08_07,Inter_ref_07_07,Inter_ref_06_07} <= RefFrameOutPadding; |
6'd19:{Inter_ref_12_07,Inter_ref_11_07,Inter_ref_10_07} <= RefFrameOutPadding[23:0]; |
6'd18:{Inter_ref_01_08,Inter_ref_00_08} <= RefFrameOutPadding[31:16]; |
6'd17:{Inter_ref_05_08,Inter_ref_04_08,Inter_ref_03_08,Inter_ref_02_08} <= RefFrameOutPadding; |
6'd16:{Inter_ref_09_08,Inter_ref_08_08,Inter_ref_07_08,Inter_ref_06_08} <= RefFrameOutPadding; |
6'd15:{Inter_ref_12_08,Inter_ref_11_08,Inter_ref_10_08} <= RefFrameOutPadding[23:0]; |
6'd14:{Inter_ref_01_09,Inter_ref_00_09} <= RefFrameOutPadding[31:16]; |
6'd13:{Inter_ref_05_09,Inter_ref_04_09,Inter_ref_03_09,Inter_ref_02_09} <= RefFrameOutPadding; |
6'd12:{Inter_ref_09_09,Inter_ref_08_09,Inter_ref_07_09,Inter_ref_06_09} <= RefFrameOutPadding; |
6'd11:{Inter_ref_12_09,Inter_ref_11_09,Inter_ref_10_09} <= RefFrameOutPadding[23:0]; |
6'd10:{Inter_ref_01_10,Inter_ref_00_10} <= RefFrameOutPadding[31:16]; |
6'd9 :{Inter_ref_05_10,Inter_ref_04_10,Inter_ref_03_10,Inter_ref_02_10} <= RefFrameOutPadding; |
6'd8 :{Inter_ref_09_10,Inter_ref_08_10,Inter_ref_07_10,Inter_ref_06_10} <= RefFrameOutPadding; |
6'd7 :{Inter_ref_12_10,Inter_ref_11_10,Inter_ref_10_10} <= RefFrameOutPadding[23:0]; |
|
6'd6 :{Inter_ref_05_11,Inter_ref_04_11,Inter_ref_03_11,Inter_ref_02_11} <= RefFrameOutPadding; |
6'd5 :{Inter_ref_09_11,Inter_ref_08_11,Inter_ref_07_11,Inter_ref_06_11} <= RefFrameOutPadding; |
6'd4 :Inter_ref_10_11 <= RefFrameOutPadding[7:0]; |
6'd3 :{Inter_ref_05_12,Inter_ref_04_12,Inter_ref_03_12,Inter_ref_02_12} <= RefFrameOutPadding; |
6'd2 :{Inter_ref_09_12,Inter_ref_08_12,Inter_ref_07_12,Inter_ref_06_12} <= RefFrameOutPadding; |
6'd1 :Inter_ref_10_12 <= RefFrameOutPadding[7:0]; |
endcase |
2'b01: |
case (blk4x4_inter_preload_counter) |
6'd48:{Inter_ref_04_00,Inter_ref_03_00,Inter_ref_02_00} <= RefFrameOutPadding[31:8]; |
6'd47:{Inter_ref_08_00,Inter_ref_07_00,Inter_ref_06_00,Inter_ref_05_00} <= RefFrameOutPadding; |
6'd46:{Inter_ref_10_00,Inter_ref_09_00} <= RefFrameOutPadding[15:0]; |
6'd45:{Inter_ref_04_01,Inter_ref_03_01,Inter_ref_02_01} <= RefFrameOutPadding[31:8]; |
6'd44:{Inter_ref_08_01,Inter_ref_07_01,Inter_ref_06_01,Inter_ref_05_01} <= RefFrameOutPadding; |
6'd43:{Inter_ref_10_01,Inter_ref_09_01} <= RefFrameOutPadding[15:0]; |
|
6'd42:Inter_ref_00_02 <= RefFrameOutPadding[31:24]; |
6'd41:{Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02,Inter_ref_01_02} <= RefFrameOutPadding; |
6'd40:{Inter_ref_08_02,Inter_ref_07_02,Inter_ref_06_02,Inter_ref_05_02} <= RefFrameOutPadding; |
6'd39:{Inter_ref_12_02,Inter_ref_11_02,Inter_ref_10_02,Inter_ref_09_02} <= RefFrameOutPadding; |
6'd38:Inter_ref_00_03 <= RefFrameOutPadding[31:24]; |
6'd37:{Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03,Inter_ref_01_03} <= RefFrameOutPadding; |
6'd36:{Inter_ref_08_03,Inter_ref_07_03,Inter_ref_06_03,Inter_ref_05_03} <= RefFrameOutPadding; |
6'd35:{Inter_ref_12_03,Inter_ref_11_03,Inter_ref_10_03,Inter_ref_09_03} <= RefFrameOutPadding; |
6'd34:Inter_ref_00_04 <= RefFrameOutPadding[31:24]; |
6'd33:{Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04,Inter_ref_01_04} <= RefFrameOutPadding; |
6'd32:{Inter_ref_08_04,Inter_ref_07_04,Inter_ref_06_04,Inter_ref_05_04} <= RefFrameOutPadding; |
6'd31:{Inter_ref_12_04,Inter_ref_11_04,Inter_ref_10_04,Inter_ref_09_04} <= RefFrameOutPadding; |
6'd30:Inter_ref_00_05 <= RefFrameOutPadding[31:24]; |
6'd29:{Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05,Inter_ref_01_05} <= RefFrameOutPadding; |
6'd28:{Inter_ref_08_05,Inter_ref_07_05,Inter_ref_06_05,Inter_ref_05_05} <= RefFrameOutPadding; |
6'd27:{Inter_ref_12_05,Inter_ref_11_05,Inter_ref_10_05,Inter_ref_09_05} <= RefFrameOutPadding; |
6'd26:Inter_ref_00_06 <= RefFrameOutPadding[31:24]; |
6'd25:{Inter_ref_04_06,Inter_ref_03_06,Inter_ref_02_06,Inter_ref_01_06} <= RefFrameOutPadding; |
6'd24:{Inter_ref_08_06,Inter_ref_07_06,Inter_ref_06_06,Inter_ref_05_06} <= RefFrameOutPadding; |
6'd23:{Inter_ref_12_06,Inter_ref_11_06,Inter_ref_10_06,Inter_ref_09_06} <= RefFrameOutPadding; |
6'd22:Inter_ref_00_07 <= RefFrameOutPadding[31:24]; |
6'd21:{Inter_ref_04_07,Inter_ref_03_07,Inter_ref_02_07,Inter_ref_01_07} <= RefFrameOutPadding; |
6'd20:{Inter_ref_08_07,Inter_ref_07_07,Inter_ref_06_07,Inter_ref_05_07} <= RefFrameOutPadding; |
6'd19:{Inter_ref_12_07,Inter_ref_11_07,Inter_ref_10_07,Inter_ref_09_07} <= RefFrameOutPadding; |
6'd18:Inter_ref_00_08 <= RefFrameOutPadding[31:24]; |
6'd17:{Inter_ref_04_08,Inter_ref_03_08,Inter_ref_02_08,Inter_ref_01_08} <= RefFrameOutPadding; |
6'd16:{Inter_ref_08_08,Inter_ref_07_08,Inter_ref_06_08,Inter_ref_05_08} <= RefFrameOutPadding; |
6'd15:{Inter_ref_12_08,Inter_ref_11_08,Inter_ref_10_08,Inter_ref_09_08} <= RefFrameOutPadding; |
6'd14:Inter_ref_00_09 <= RefFrameOutPadding[31:24]; |
6'd13:{Inter_ref_04_09,Inter_ref_03_09,Inter_ref_02_09,Inter_ref_01_09} <= RefFrameOutPadding; |
6'd12:{Inter_ref_08_09,Inter_ref_07_09,Inter_ref_06_09,Inter_ref_05_09} <= RefFrameOutPadding; |
6'd11:{Inter_ref_12_09,Inter_ref_11_09,Inter_ref_10_09,Inter_ref_09_09} <= RefFrameOutPadding; |
6'd10:Inter_ref_00_10 <= RefFrameOutPadding[31:24]; |
6'd9 :{Inter_ref_04_10,Inter_ref_03_10,Inter_ref_02_10,Inter_ref_01_10} <= RefFrameOutPadding; |
6'd8 :{Inter_ref_08_10,Inter_ref_07_10,Inter_ref_06_10,Inter_ref_05_10} <= RefFrameOutPadding; |
6'd7 :{Inter_ref_12_10,Inter_ref_11_10,Inter_ref_10_10,Inter_ref_09_10} <= RefFrameOutPadding; |
|
6'd6 :{Inter_ref_04_11,Inter_ref_03_11,Inter_ref_02_11} <= RefFrameOutPadding[31:8]; |
6'd5 :{Inter_ref_08_11,Inter_ref_07_11,Inter_ref_06_11,Inter_ref_05_11} <= RefFrameOutPadding; |
6'd4 :{Inter_ref_10_11,Inter_ref_09_11} <= RefFrameOutPadding[15:0]; |
6'd3 :{Inter_ref_04_12,Inter_ref_03_12,Inter_ref_02_12} <= RefFrameOutPadding[31:8]; |
6'd2 :{Inter_ref_08_12,Inter_ref_07_12,Inter_ref_06_12,Inter_ref_05_12} <= RefFrameOutPadding; |
6'd1 :{Inter_ref_10_12,Inter_ref_09_12} <= RefFrameOutPadding[15:0]; |
endcase |
2'b10: |
case (blk4x4_inter_preload_counter) |
6'd48:{Inter_ref_03_00,Inter_ref_02_00} <= RefFrameOutPadding[31:16]; |
6'd47:{Inter_ref_07_00,Inter_ref_06_00,Inter_ref_05_00,Inter_ref_04_00} <= RefFrameOutPadding; |
6'd46:{Inter_ref_10_00,Inter_ref_09_00,Inter_ref_08_00} <= RefFrameOutPadding[23:0]; |
6'd45:{Inter_ref_03_01,Inter_ref_02_01} <= RefFrameOutPadding[31:16]; |
6'd44:{Inter_ref_07_01,Inter_ref_06_01,Inter_ref_05_01,Inter_ref_04_01} <= RefFrameOutPadding; |
6'd43:{Inter_ref_10_01,Inter_ref_09_01,Inter_ref_08_01} <= RefFrameOutPadding[23:0]; |
|
6'd42:{Inter_ref_03_02,Inter_ref_02_02,Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding; |
6'd41:{Inter_ref_07_02,Inter_ref_06_02,Inter_ref_05_02,Inter_ref_04_02} <= RefFrameOutPadding; |
6'd40:{Inter_ref_11_02,Inter_ref_10_02,Inter_ref_09_02,Inter_ref_08_02} <= RefFrameOutPadding; |
6'd39:Inter_ref_12_02 <= RefFrameOutPadding[7:0]; |
6'd38:{Inter_ref_03_03,Inter_ref_02_03,Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding; |
6'd37:{Inter_ref_07_03,Inter_ref_06_03,Inter_ref_05_03,Inter_ref_04_03} <= RefFrameOutPadding; |
6'd36:{Inter_ref_11_03,Inter_ref_10_03,Inter_ref_09_03,Inter_ref_08_03} <= RefFrameOutPadding; |
6'd35:Inter_ref_12_03 <= RefFrameOutPadding[7:0]; |
6'd34:{Inter_ref_03_04,Inter_ref_02_04,Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding; |
6'd33:{Inter_ref_07_04,Inter_ref_06_04,Inter_ref_05_04,Inter_ref_04_04} <= RefFrameOutPadding; |
6'd32:{Inter_ref_11_04,Inter_ref_10_04,Inter_ref_09_04,Inter_ref_08_04} <= RefFrameOutPadding; |
6'd31:Inter_ref_12_04 <= RefFrameOutPadding[7:0]; |
6'd30:{Inter_ref_03_05,Inter_ref_02_05,Inter_ref_01_05,Inter_ref_00_05} <= RefFrameOutPadding; |
6'd29:{Inter_ref_07_05,Inter_ref_06_05,Inter_ref_05_05,Inter_ref_04_05} <= RefFrameOutPadding; |
6'd28:{Inter_ref_11_05,Inter_ref_10_05,Inter_ref_09_05,Inter_ref_08_05} <= RefFrameOutPadding; |
6'd27:Inter_ref_12_05 <= RefFrameOutPadding[7:0]; |
6'd26:{Inter_ref_03_06,Inter_ref_02_06,Inter_ref_01_06,Inter_ref_00_06} <= RefFrameOutPadding; |
6'd25:{Inter_ref_07_06,Inter_ref_06_06,Inter_ref_05_06,Inter_ref_04_06} <= RefFrameOutPadding; |
6'd24:{Inter_ref_11_06,Inter_ref_10_06,Inter_ref_09_06,Inter_ref_08_06} <= RefFrameOutPadding; |
6'd23:Inter_ref_12_06 <= RefFrameOutPadding[7:0]; |
6'd22:{Inter_ref_03_07,Inter_ref_02_07,Inter_ref_01_07,Inter_ref_00_07} <= RefFrameOutPadding; |
6'd21:{Inter_ref_07_07,Inter_ref_06_07,Inter_ref_05_07,Inter_ref_04_07} <= RefFrameOutPadding; |
6'd20:{Inter_ref_11_07,Inter_ref_10_07,Inter_ref_09_07,Inter_ref_08_07} <= RefFrameOutPadding; |
6'd19:Inter_ref_12_07 <= RefFrameOutPadding[7:0]; |
6'd18:{Inter_ref_03_08,Inter_ref_02_08,Inter_ref_01_08,Inter_ref_00_08} <= RefFrameOutPadding; |
6'd17:{Inter_ref_07_08,Inter_ref_06_08,Inter_ref_05_08,Inter_ref_04_08} <= RefFrameOutPadding; |
6'd16:{Inter_ref_11_08,Inter_ref_10_08,Inter_ref_09_08,Inter_ref_08_08} <= RefFrameOutPadding; |
6'd15:Inter_ref_12_08 <= RefFrameOutPadding[7:0]; |
6'd14:{Inter_ref_03_09,Inter_ref_02_09,Inter_ref_01_09,Inter_ref_00_09} <= RefFrameOutPadding; |
6'd13:{Inter_ref_07_09,Inter_ref_06_09,Inter_ref_05_09,Inter_ref_04_09} <= RefFrameOutPadding; |
6'd12:{Inter_ref_11_09,Inter_ref_10_09,Inter_ref_09_09,Inter_ref_08_09} <= RefFrameOutPadding; |
6'd11:Inter_ref_12_09 <= RefFrameOutPadding[7:0]; |
6'd10:{Inter_ref_03_10,Inter_ref_02_10,Inter_ref_01_10,Inter_ref_00_10} <= RefFrameOutPadding; |
6'd9 :{Inter_ref_07_10,Inter_ref_06_10,Inter_ref_05_10,Inter_ref_04_10} <= RefFrameOutPadding; |
6'd8 :{Inter_ref_11_10,Inter_ref_10_10,Inter_ref_09_10,Inter_ref_08_10} <= RefFrameOutPadding; |
6'd7 :Inter_ref_12_10 <= RefFrameOutPadding[7:0]; |
|
6'd6 :{Inter_ref_03_11,Inter_ref_02_11} <= RefFrameOutPadding[31:16]; |
6'd5 :{Inter_ref_07_11,Inter_ref_06_11,Inter_ref_05_11,Inter_ref_04_11} <= RefFrameOutPadding; |
6'd4 :{Inter_ref_10_11,Inter_ref_09_11,Inter_ref_08_11} <= RefFrameOutPadding[23:0]; |
6'd3 :{Inter_ref_03_12,Inter_ref_02_12} <= RefFrameOutPadding[31:16]; |
6'd2 :{Inter_ref_07_12,Inter_ref_06_12,Inter_ref_05_12,Inter_ref_04_12} <= RefFrameOutPadding; |
6'd1 :{Inter_ref_10_12,Inter_ref_09_12,Inter_ref_08_12} <= RefFrameOutPadding[23:0]; |
endcase |
2'b11: |
case (blk4x4_inter_preload_counter) |
6'd48:{Inter_ref_02_00} <= RefFrameOutPadding[31:24]; |
6'd47:{Inter_ref_06_00,Inter_ref_05_00,Inter_ref_04_00,Inter_ref_03_00} <= RefFrameOutPadding; |
6'd46:{Inter_ref_10_00,Inter_ref_09_00,Inter_ref_08_00,Inter_ref_07_00} <= RefFrameOutPadding; |
6'd45:{Inter_ref_02_01} <= RefFrameOutPadding[31:24]; |
6'd44:{Inter_ref_06_01,Inter_ref_05_01,Inter_ref_04_01,Inter_ref_03_01} <= RefFrameOutPadding; |
6'd43:{Inter_ref_10_01,Inter_ref_09_01,Inter_ref_08_01,Inter_ref_07_01} <= RefFrameOutPadding; |
|
6'd42:{Inter_ref_02_02,Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding[31:8]; |
6'd41:{Inter_ref_06_02,Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02} <= RefFrameOutPadding; |
6'd40:{Inter_ref_10_02,Inter_ref_09_02,Inter_ref_08_02,Inter_ref_07_02} <= RefFrameOutPadding; |
6'd39:{Inter_ref_12_02,Inter_ref_11_02} <= RefFrameOutPadding[15:0]; |
6'd38:{Inter_ref_02_03,Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding[31:8]; |
6'd37:{Inter_ref_06_03,Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03} <= RefFrameOutPadding; |
6'd36:{Inter_ref_10_03,Inter_ref_09_03,Inter_ref_08_03,Inter_ref_07_03} <= RefFrameOutPadding; |
6'd35:{Inter_ref_12_03,Inter_ref_11_03} <= RefFrameOutPadding[15:0]; |
6'd34:{Inter_ref_02_04,Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding[31:8]; |
6'd33:{Inter_ref_06_04,Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04} <= RefFrameOutPadding; |
6'd32:{Inter_ref_10_04,Inter_ref_09_04,Inter_ref_08_04,Inter_ref_07_04} <= RefFrameOutPadding; |
6'd31:{Inter_ref_12_04,Inter_ref_11_04} <= RefFrameOutPadding[15:0]; |
6'd30:{Inter_ref_02_05,Inter_ref_01_05,Inter_ref_00_05} <= RefFrameOutPadding[31:8]; |
6'd29:{Inter_ref_06_05,Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05} <= RefFrameOutPadding; |
6'd28:{Inter_ref_10_05,Inter_ref_09_05,Inter_ref_08_05,Inter_ref_07_05} <= RefFrameOutPadding; |
6'd27:{Inter_ref_12_05,Inter_ref_11_05} <= RefFrameOutPadding[15:0]; |
6'd26:{Inter_ref_02_06,Inter_ref_01_06,Inter_ref_00_06} <= RefFrameOutPadding[31:8]; |
6'd25:{Inter_ref_06_06,Inter_ref_05_06,Inter_ref_04_06,Inter_ref_03_06} <= RefFrameOutPadding; |
6'd24:{Inter_ref_10_06,Inter_ref_09_06,Inter_ref_08_06,Inter_ref_07_06} <= RefFrameOutPadding; |
6'd23:{Inter_ref_12_06,Inter_ref_11_06} <= RefFrameOutPadding[15:0]; |
6'd22:{Inter_ref_02_07,Inter_ref_01_07,Inter_ref_00_07} <= RefFrameOutPadding[31:8]; |
6'd21:{Inter_ref_06_07,Inter_ref_05_07,Inter_ref_04_07,Inter_ref_03_07} <= RefFrameOutPadding; |
6'd20:{Inter_ref_10_07,Inter_ref_09_07,Inter_ref_08_07,Inter_ref_07_07} <= RefFrameOutPadding; |
6'd19:{Inter_ref_12_07,Inter_ref_11_07} <= RefFrameOutPadding[15:0]; |
6'd18:{Inter_ref_02_08,Inter_ref_01_08,Inter_ref_00_08} <= RefFrameOutPadding[31:8]; |
6'd17:{Inter_ref_06_08,Inter_ref_05_08,Inter_ref_04_08,Inter_ref_03_08} <= RefFrameOutPadding; |
6'd16:{Inter_ref_10_08,Inter_ref_09_08,Inter_ref_08_08,Inter_ref_07_08} <= RefFrameOutPadding; |
6'd15:{Inter_ref_12_08,Inter_ref_11_08} <= RefFrameOutPadding[15:0]; |
6'd14:{Inter_ref_02_09,Inter_ref_01_09,Inter_ref_00_09} <= RefFrameOutPadding[31:8]; |
6'd13:{Inter_ref_06_09,Inter_ref_05_09,Inter_ref_04_09,Inter_ref_03_09} <= RefFrameOutPadding; |
6'd12:{Inter_ref_10_09,Inter_ref_09_09,Inter_ref_08_09,Inter_ref_07_09} <= RefFrameOutPadding; |
6'd11:{Inter_ref_12_09,Inter_ref_11_09} <= RefFrameOutPadding[15:0]; |
6'd10:{Inter_ref_02_10,Inter_ref_01_10,Inter_ref_00_10} <= RefFrameOutPadding[31:8]; |
6'd9 :{Inter_ref_06_10,Inter_ref_05_10,Inter_ref_04_10,Inter_ref_03_10} <= RefFrameOutPadding; |
6'd8 :{Inter_ref_10_10,Inter_ref_09_10,Inter_ref_08_10,Inter_ref_07_10} <= RefFrameOutPadding; |
6'd7 :{Inter_ref_12_10,Inter_ref_11_10} <= RefFrameOutPadding[15:0]; |
|
6'd6 :{Inter_ref_02_11} <= RefFrameOutPadding[31:24]; |
6'd5 :{Inter_ref_06_11,Inter_ref_05_11,Inter_ref_04_11,Inter_ref_03_11} <= RefFrameOutPadding; |
6'd4 :{Inter_ref_10_11,Inter_ref_09_11,Inter_ref_08_11,Inter_ref_07_11} <= RefFrameOutPadding; |
6'd3 :{Inter_ref_02_12} <= RefFrameOutPadding[31:24]; |
6'd2 :{Inter_ref_06_12,Inter_ref_05_12,Inter_ref_04_12,Inter_ref_03_12} <= RefFrameOutPadding; |
6'd1 :{Inter_ref_10_12,Inter_ref_09_12,Inter_ref_08_12,Inter_ref_07_12} <= RefFrameOutPadding; |
endcase |
endcase |
endcase |
1'b1: //mv_below8x8_curr == 1'b1 |
case (pos_FracL) |
`pos_f,`pos_q,`pos_i,`pos_k,`pos_j: |
case (xInt_org_unclip_1to0) |
2'b00: |
case (blk4x4_inter_preload_counter) |
6'd27:{Inter_ref_01_00,Inter_ref_00_00} <= RefFrameOutPadding[31:16]; |
6'd26:{Inter_ref_05_00,Inter_ref_04_00,Inter_ref_03_00,Inter_ref_02_00} <= RefFrameOutPadding; |
6'd25:{Inter_ref_08_00,Inter_ref_07_00,Inter_ref_06_00} <= RefFrameOutPadding[23:0]; |
6'd24:{Inter_ref_01_01,Inter_ref_00_01} <= RefFrameOutPadding[31:16]; |
6'd23:{Inter_ref_05_01,Inter_ref_04_01,Inter_ref_03_01,Inter_ref_02_01} <= RefFrameOutPadding; |
6'd22:{Inter_ref_08_01,Inter_ref_07_01,Inter_ref_06_01} <= RefFrameOutPadding[23:0]; |
6'd21:{Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding[31:16]; |
6'd20:{Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding; |
6'd19:{Inter_ref_08_02,Inter_ref_07_02,Inter_ref_06_02} <= RefFrameOutPadding[23:0]; |
6'd18:{Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding[31:16]; |
6'd17:{Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding; |
6'd16:{Inter_ref_08_03,Inter_ref_07_03,Inter_ref_06_03} <= RefFrameOutPadding[23:0]; |
6'd15:{Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding[31:16]; |
6'd14:{Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04} <= RefFrameOutPadding; |
6'd13:{Inter_ref_08_04,Inter_ref_07_04,Inter_ref_06_04} <= RefFrameOutPadding[23:0]; |
6'd12:{Inter_ref_01_05,Inter_ref_00_05} <= RefFrameOutPadding[31:16]; |
6'd11:{Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05} <= RefFrameOutPadding; |
6'd10:{Inter_ref_08_05,Inter_ref_07_05,Inter_ref_06_05} <= RefFrameOutPadding[23:0]; |
6'd9 :{Inter_ref_01_06,Inter_ref_00_06} <= RefFrameOutPadding[31:16]; |
6'd8 :{Inter_ref_05_06,Inter_ref_04_06,Inter_ref_03_06,Inter_ref_02_06} <= RefFrameOutPadding; |
6'd7 :{Inter_ref_08_06,Inter_ref_07_06,Inter_ref_06_06} <= RefFrameOutPadding[23:0]; |
6'd6 :{Inter_ref_01_07,Inter_ref_00_07} <= RefFrameOutPadding[31:16]; |
6'd5 :{Inter_ref_05_07,Inter_ref_04_07,Inter_ref_03_07,Inter_ref_02_07} <= RefFrameOutPadding; |
6'd4 :{Inter_ref_08_07,Inter_ref_07_07,Inter_ref_06_07} <= RefFrameOutPadding[23:0]; |
6'd3 :{Inter_ref_01_08,Inter_ref_00_08} <= RefFrameOutPadding[31:16]; |
6'd2 :{Inter_ref_05_08,Inter_ref_04_08,Inter_ref_03_08,Inter_ref_02_08} <= RefFrameOutPadding; |
6'd1 :{Inter_ref_08_08,Inter_ref_07_08,Inter_ref_06_08} <= RefFrameOutPadding[23:0]; |
endcase |
2'b01: |
case (blk4x4_inter_preload_counter) |
6'd27:Inter_ref_00_00 <= RefFrameOutPadding[31:24]; |
6'd26:{Inter_ref_04_00,Inter_ref_03_00,Inter_ref_02_00,Inter_ref_01_00} <= RefFrameOutPadding; |
6'd25:{Inter_ref_08_00,Inter_ref_07_00,Inter_ref_06_00,Inter_ref_05_00} <= RefFrameOutPadding; |
6'd24:Inter_ref_00_01 <= RefFrameOutPadding[31:24]; |
6'd23:{Inter_ref_04_01,Inter_ref_03_01,Inter_ref_02_01,Inter_ref_01_01} <= RefFrameOutPadding; |
6'd22:{Inter_ref_08_01,Inter_ref_07_01,Inter_ref_06_01,Inter_ref_05_01} <= RefFrameOutPadding; |
6'd21:Inter_ref_00_02 <= RefFrameOutPadding[31:24]; |
6'd20:{Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02,Inter_ref_01_02} <= RefFrameOutPadding; |
6'd19:{Inter_ref_08_02,Inter_ref_07_02,Inter_ref_06_02,Inter_ref_05_02} <= RefFrameOutPadding; |
6'd18:Inter_ref_00_03 <= RefFrameOutPadding[31:24]; |
6'd17:{Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03,Inter_ref_01_03} <= RefFrameOutPadding; |
6'd16:{Inter_ref_08_03,Inter_ref_07_03,Inter_ref_06_03,Inter_ref_05_03} <= RefFrameOutPadding; |
6'd15:Inter_ref_00_04 <= RefFrameOutPadding[31:24]; |
6'd14:{Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04,Inter_ref_01_04} <= RefFrameOutPadding; |
6'd13:{Inter_ref_08_04,Inter_ref_07_04,Inter_ref_06_04,Inter_ref_05_04} <= RefFrameOutPadding; |
6'd12:Inter_ref_00_05 <= RefFrameOutPadding[31:24]; |
6'd11:{Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05,Inter_ref_01_05} <= RefFrameOutPadding; |
6'd10:{Inter_ref_08_05,Inter_ref_07_05,Inter_ref_06_05,Inter_ref_05_05} <= RefFrameOutPadding; |
6'd9 :Inter_ref_00_06 <= RefFrameOutPadding[31:24]; |
6'd8 :{Inter_ref_04_06,Inter_ref_03_06,Inter_ref_02_06,Inter_ref_01_06} <= RefFrameOutPadding; |
6'd7 :{Inter_ref_08_06,Inter_ref_07_06,Inter_ref_06_06,Inter_ref_05_06} <= RefFrameOutPadding; |
6'd6 :Inter_ref_00_07 <= RefFrameOutPadding[31:24]; |
6'd5 :{Inter_ref_04_07,Inter_ref_03_07,Inter_ref_02_07,Inter_ref_01_07} <= RefFrameOutPadding; |
6'd4 :{Inter_ref_08_07,Inter_ref_07_07,Inter_ref_06_07,Inter_ref_05_07} <= RefFrameOutPadding; |
6'd3 :Inter_ref_00_08 <= RefFrameOutPadding[31:24]; |
6'd2 :{Inter_ref_04_08,Inter_ref_03_08,Inter_ref_02_08,Inter_ref_01_08} <= RefFrameOutPadding; |
6'd1 :{Inter_ref_08_08,Inter_ref_07_08,Inter_ref_06_08,Inter_ref_05_08} <= RefFrameOutPadding; |
endcase |
2'b10: |
case (blk4x4_inter_preload_counter) |
6'd27:{Inter_ref_03_00,Inter_ref_02_00,Inter_ref_01_00,Inter_ref_00_00} <= RefFrameOutPadding; |
6'd26:{Inter_ref_07_00,Inter_ref_06_00,Inter_ref_05_00,Inter_ref_04_00} <= RefFrameOutPadding; |
6'd25:Inter_ref_08_00 <= RefFrameOutPadding[7:0]; |
6'd24:{Inter_ref_03_01,Inter_ref_02_01,Inter_ref_01_01,Inter_ref_00_01} <= RefFrameOutPadding; |
6'd23:{Inter_ref_07_01,Inter_ref_06_01,Inter_ref_05_01,Inter_ref_04_01} <= RefFrameOutPadding; |
6'd22:Inter_ref_08_01 <= RefFrameOutPadding[7:0]; |
6'd21:{Inter_ref_03_02,Inter_ref_02_02,Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding; |
6'd20:{Inter_ref_07_02,Inter_ref_06_02,Inter_ref_05_02,Inter_ref_04_02} <= RefFrameOutPadding; |
6'd19:Inter_ref_08_02 <= RefFrameOutPadding[7:0]; |
6'd18:{Inter_ref_03_03,Inter_ref_02_03,Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding; |
6'd17:{Inter_ref_07_03,Inter_ref_06_03,Inter_ref_05_03,Inter_ref_04_03} <= RefFrameOutPadding; |
6'd16:Inter_ref_08_03 <= RefFrameOutPadding[7:0]; |
6'd15:{Inter_ref_03_04,Inter_ref_02_04,Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding; |
6'd14:{Inter_ref_07_04,Inter_ref_06_04,Inter_ref_05_04,Inter_ref_04_04} <= RefFrameOutPadding; |
6'd13:Inter_ref_08_04 <= RefFrameOutPadding[7:0]; |
6'd12:{Inter_ref_03_05,Inter_ref_02_05,Inter_ref_01_05,Inter_ref_00_05} <= RefFrameOutPadding; |
6'd11:{Inter_ref_07_05,Inter_ref_06_05,Inter_ref_05_05,Inter_ref_04_05} <= RefFrameOutPadding; |
6'd10:Inter_ref_08_05 <= RefFrameOutPadding[7:0]; |
6'd9 :{Inter_ref_03_06,Inter_ref_02_06,Inter_ref_01_06,Inter_ref_00_06} <= RefFrameOutPadding; |
6'd8 :{Inter_ref_07_06,Inter_ref_06_06,Inter_ref_05_06,Inter_ref_04_06} <= RefFrameOutPadding; |
6'd7 :Inter_ref_08_06 <= RefFrameOutPadding[7:0]; |
6'd6 :{Inter_ref_03_07,Inter_ref_02_07,Inter_ref_01_07,Inter_ref_00_07} <= RefFrameOutPadding; |
6'd5 :{Inter_ref_07_07,Inter_ref_06_07,Inter_ref_05_07,Inter_ref_04_07} <= RefFrameOutPadding; |
6'd4 :Inter_ref_08_07 <= RefFrameOutPadding[7:0]; |
6'd3 :{Inter_ref_03_08,Inter_ref_02_08,Inter_ref_01_08,Inter_ref_00_08} <= RefFrameOutPadding; |
6'd2 :{Inter_ref_07_08,Inter_ref_06_08,Inter_ref_05_08,Inter_ref_04_08} <= RefFrameOutPadding; |
6'd1 :Inter_ref_08_08 <= RefFrameOutPadding[7:0]; |
endcase |
2'b11: |
case (blk4x4_inter_preload_counter) |
6'd27:{Inter_ref_02_00,Inter_ref_01_00,Inter_ref_00_00} <= RefFrameOutPadding[31:8]; |
6'd26:{Inter_ref_06_00,Inter_ref_05_00,Inter_ref_04_00,Inter_ref_03_00} <= RefFrameOutPadding; |
6'd25:{Inter_ref_08_00,Inter_ref_07_00} <= RefFrameOutPadding[15:0]; |
|
6'd24:{Inter_ref_02_01,Inter_ref_01_01,Inter_ref_00_01} <= RefFrameOutPadding[31:8]; |
6'd23:{Inter_ref_06_01,Inter_ref_05_01,Inter_ref_04_01,Inter_ref_03_01} <= RefFrameOutPadding; |
6'd22:{Inter_ref_08_01,Inter_ref_07_01} <= RefFrameOutPadding[15:0]; |
|
6'd21:{Inter_ref_02_02,Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding[31:8]; |
6'd20:{Inter_ref_06_02,Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02} <= RefFrameOutPadding; |
6'd19:{Inter_ref_08_02,Inter_ref_07_02} <= RefFrameOutPadding[15:0]; |
|
6'd18:{Inter_ref_02_03,Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding[31:8]; |
6'd17:{Inter_ref_06_03,Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03} <= RefFrameOutPadding; |
6'd16:{Inter_ref_08_03,Inter_ref_07_03} <= RefFrameOutPadding[15:0]; |
|
6'd15:{Inter_ref_02_04,Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding[31:8]; |
6'd14:{Inter_ref_06_04,Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04} <= RefFrameOutPadding; |
6'd13:{Inter_ref_08_04,Inter_ref_07_04} <= RefFrameOutPadding[15:0]; |
|
6'd12:{Inter_ref_02_05,Inter_ref_01_05,Inter_ref_00_05} <= RefFrameOutPadding[31:8]; |
6'd11:{Inter_ref_06_05,Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05} <= RefFrameOutPadding; |
6'd10:{Inter_ref_08_05,Inter_ref_07_05} <= RefFrameOutPadding[15:0]; |
|
6'd9 :{Inter_ref_02_06,Inter_ref_01_06,Inter_ref_00_06} <= RefFrameOutPadding[31:8]; |
6'd8 :{Inter_ref_06_06,Inter_ref_05_06,Inter_ref_04_06,Inter_ref_03_06} <= RefFrameOutPadding; |
6'd7 :{Inter_ref_08_06,Inter_ref_07_06} <= RefFrameOutPadding[15:0]; |
|
6'd6 :{Inter_ref_02_07,Inter_ref_01_07,Inter_ref_00_07} <= RefFrameOutPadding[31:8]; |
6'd5 :{Inter_ref_06_07,Inter_ref_05_07,Inter_ref_04_07,Inter_ref_03_07} <= RefFrameOutPadding; |
6'd4 :{Inter_ref_08_07,Inter_ref_07_07} <= RefFrameOutPadding[15:0]; |
|
6'd3 :{Inter_ref_02_08,Inter_ref_01_08,Inter_ref_00_08} <= RefFrameOutPadding[31:8]; |
6'd2 :{Inter_ref_06_08,Inter_ref_05_08,Inter_ref_04_08,Inter_ref_03_08} <= RefFrameOutPadding; |
6'd1 :{Inter_ref_08_08,Inter_ref_07_08} <= RefFrameOutPadding[15:0]; |
endcase |
endcase |
`pos_d,`pos_h,`pos_n: |
case (xInt_org_unclip_1to0) |
2'b00: |
case (blk4x4_inter_preload_counter) |
6'd9:{Inter_ref_05_00,Inter_ref_04_00,Inter_ref_03_00,Inter_ref_02_00} <= RefFrameOutPadding; |
6'd8:{Inter_ref_05_01,Inter_ref_04_01,Inter_ref_03_01,Inter_ref_02_01} <= RefFrameOutPadding; |
6'd7:{Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding; |
6'd6:{Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding; |
6'd5:{Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04} <= RefFrameOutPadding; |
6'd4:{Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05} <= RefFrameOutPadding; |
6'd3:{Inter_ref_05_06,Inter_ref_04_06,Inter_ref_03_06,Inter_ref_02_06} <= RefFrameOutPadding; |
6'd2:{Inter_ref_05_07,Inter_ref_04_07,Inter_ref_03_07,Inter_ref_02_07} <= RefFrameOutPadding; |
6'd1:{Inter_ref_05_08,Inter_ref_04_08,Inter_ref_03_08,Inter_ref_02_08} <= RefFrameOutPadding; |
endcase |
2'b01: |
case (blk4x4_inter_preload_counter) |
6'd18:{Inter_ref_04_00,Inter_ref_03_00,Inter_ref_02_00} <= RefFrameOutPadding[31:8]; |
6'd17:Inter_ref_05_00 <= RefFrameOutPadding[7:0]; |
|
6'd16:{Inter_ref_04_01,Inter_ref_03_01,Inter_ref_02_01} <= RefFrameOutPadding[31:8]; |
6'd15:Inter_ref_05_01 <= RefFrameOutPadding[7:0]; |
|
6'd14:{Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding[31:8]; |
6'd13:Inter_ref_05_02 <= RefFrameOutPadding[7:0]; |
|
6'd12:{Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding[31:8]; |
6'd11:Inter_ref_05_03 <= RefFrameOutPadding[7:0]; |
|
6'd10:{Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04} <= RefFrameOutPadding[31:8]; |
6'd9 :Inter_ref_05_04 <= RefFrameOutPadding[7:0]; |
|
6'd8 :{Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05} <= RefFrameOutPadding[31:8]; |
6'd7 :Inter_ref_05_05 <= RefFrameOutPadding[7:0]; |
|
6'd6 :{Inter_ref_04_06,Inter_ref_03_06,Inter_ref_02_06} <= RefFrameOutPadding[31:8]; |
6'd5 :Inter_ref_05_06 <= RefFrameOutPadding[7:0]; |
|
6'd4 :{Inter_ref_04_07,Inter_ref_03_07,Inter_ref_02_07} <= RefFrameOutPadding[31:8]; |
6'd3 :Inter_ref_05_07 <= RefFrameOutPadding[7:0]; |
|
6'd2 :{Inter_ref_04_08,Inter_ref_03_08,Inter_ref_02_08} <= RefFrameOutPadding[31:8]; |
6'd1 :Inter_ref_05_08 <= RefFrameOutPadding[7:0]; |
endcase |
2'b10: |
case (blk4x4_inter_preload_counter) |
6'd18:{Inter_ref_03_00,Inter_ref_02_00} <= RefFrameOutPadding[31:16]; |
6'd17:{Inter_ref_05_00,Inter_ref_04_00} <= RefFrameOutPadding[15:0]; |
|
6'd16:{Inter_ref_03_01,Inter_ref_02_01} <= RefFrameOutPadding[31:16]; |
6'd15:{Inter_ref_05_01,Inter_ref_04_01} <= RefFrameOutPadding[15:0]; |
|
6'd14:{Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding[31:16]; |
6'd13:{Inter_ref_05_02,Inter_ref_04_02} <= RefFrameOutPadding[15:0]; |
|
6'd12:{Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding[31:16]; |
6'd11:{Inter_ref_05_03,Inter_ref_04_03} <= RefFrameOutPadding[15:0]; |
|
6'd10:{Inter_ref_03_04,Inter_ref_02_04} <= RefFrameOutPadding[31:16]; |
6'd9 :{Inter_ref_05_04,Inter_ref_04_04} <= RefFrameOutPadding[15:0]; |
|
6'd8 :{Inter_ref_03_05,Inter_ref_02_05} <= RefFrameOutPadding[31:16]; |
6'd7 :{Inter_ref_05_05,Inter_ref_04_05} <= RefFrameOutPadding[15:0]; |
|
6'd6 :{Inter_ref_03_06,Inter_ref_02_06} <= RefFrameOutPadding[31:16]; |
6'd5 :{Inter_ref_05_06,Inter_ref_04_06} <= RefFrameOutPadding[15:0]; |
|
6'd4 :{Inter_ref_03_07,Inter_ref_02_07} <= RefFrameOutPadding[31:16]; |
6'd3 :{Inter_ref_05_07,Inter_ref_04_07} <= RefFrameOutPadding[15:0]; |
|
6'd2 :{Inter_ref_03_08,Inter_ref_02_08} <= RefFrameOutPadding[31:16]; |
6'd1 :{Inter_ref_05_08,Inter_ref_04_08} <= RefFrameOutPadding[15:0]; |
endcase |
2'b11: |
case (blk4x4_inter_preload_counter) |
6'd18:Inter_ref_02_00 <= RefFrameOutPadding[31:24]; |
6'd17:{Inter_ref_05_00,Inter_ref_04_00,Inter_ref_03_00} <= RefFrameOutPadding[23:0]; |
|
6'd16:Inter_ref_02_01 <= RefFrameOutPadding[31:24]; |
6'd15:{Inter_ref_05_01,Inter_ref_04_01,Inter_ref_03_01} <= RefFrameOutPadding[23:0]; |
|
6'd14:Inter_ref_02_02 <= RefFrameOutPadding[31:24]; |
6'd13:{Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02} <= RefFrameOutPadding[23:0]; |
|
6'd12:Inter_ref_02_03 <= RefFrameOutPadding[31:24]; |
6'd11:{Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03} <= RefFrameOutPadding[23:0]; |
|
6'd10:Inter_ref_02_04 <= RefFrameOutPadding[31:24]; |
6'd9 :{Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04} <= RefFrameOutPadding[23:0]; |
|
6'd8 :Inter_ref_02_05 <= RefFrameOutPadding[31:24]; |
6'd7 :{Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05} <= RefFrameOutPadding[23:0]; |
|
6'd6 :Inter_ref_02_06 <= RefFrameOutPadding[31:24]; |
6'd5 :{Inter_ref_05_06,Inter_ref_04_06,Inter_ref_03_06} <= RefFrameOutPadding[23:0]; |
|
6'd4 :Inter_ref_02_07 <= RefFrameOutPadding[31:24]; |
6'd3 :{Inter_ref_05_07,Inter_ref_04_07,Inter_ref_03_07} <= RefFrameOutPadding[23:0]; |
|
6'd2 :Inter_ref_02_08 <= RefFrameOutPadding[31:24]; |
6'd1 :{Inter_ref_05_08,Inter_ref_04_08,Inter_ref_03_08} <= RefFrameOutPadding[23:0]; |
endcase |
endcase |
`pos_a,`pos_b,`pos_c: |
case (xInt_org_unclip_1to0) |
2'b00: |
case (blk4x4_inter_preload_counter) |
6'd12:{Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding[31:16]; |
6'd11:{Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding; |
6'd10:{Inter_ref_08_02,Inter_ref_07_02,Inter_ref_06_02} <= RefFrameOutPadding[23:0]; |
|
6'd9 :{Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding[31:16]; |
6'd8 :{Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding; |
6'd7 :{Inter_ref_08_03,Inter_ref_07_03,Inter_ref_06_03} <= RefFrameOutPadding[23:0]; |
|
6'd6 :{Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding[31:16]; |
6'd5 :{Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04} <= RefFrameOutPadding; |
6'd4 :{Inter_ref_08_04,Inter_ref_07_04,Inter_ref_06_04} <= RefFrameOutPadding[23:0]; |
|
6'd3 :{Inter_ref_01_05,Inter_ref_00_05} <= RefFrameOutPadding[31:16]; |
6'd2 :{Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05} <= RefFrameOutPadding; |
6'd1 :{Inter_ref_08_05,Inter_ref_07_05,Inter_ref_06_05} <= RefFrameOutPadding[23:0]; |
endcase |
2'b01: |
case (blk4x4_inter_preload_counter) |
6'd12:Inter_ref_00_02 <= RefFrameOutPadding[31:24]; |
6'd11:{Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02,Inter_ref_01_02} <= RefFrameOutPadding; |
6'd10:{Inter_ref_08_02,Inter_ref_07_02,Inter_ref_06_02,Inter_ref_05_02} <= RefFrameOutPadding; |
|
6'd9 :Inter_ref_00_03 <= RefFrameOutPadding[31:24]; |
6'd8 :{Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03,Inter_ref_01_03} <= RefFrameOutPadding; |
6'd7 :{Inter_ref_08_03,Inter_ref_07_03,Inter_ref_06_03,Inter_ref_05_03} <= RefFrameOutPadding; |
|
6'd6 :Inter_ref_00_04 <= RefFrameOutPadding[31:24]; |
6'd5 :{Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04,Inter_ref_01_04} <= RefFrameOutPadding; |
6'd4 :{Inter_ref_08_04,Inter_ref_07_04,Inter_ref_06_04,Inter_ref_05_04} <= RefFrameOutPadding; |
|
6'd3 :Inter_ref_00_05 <= RefFrameOutPadding[31:24]; |
6'd2 :{Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05,Inter_ref_01_05} <= RefFrameOutPadding; |
6'd1 :{Inter_ref_08_05,Inter_ref_07_05,Inter_ref_06_05,Inter_ref_05_05} <= RefFrameOutPadding; |
endcase |
2'b10: |
case (blk4x4_inter_preload_counter) |
6'd12:{Inter_ref_03_02,Inter_ref_02_02,Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding; |
6'd11:{Inter_ref_07_02,Inter_ref_06_02,Inter_ref_05_02,Inter_ref_04_02} <= RefFrameOutPadding; |
6'd10:Inter_ref_08_02 <= RefFrameOutPadding[7:0]; |
|
6'd9 :{Inter_ref_03_03,Inter_ref_02_03,Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding; |
6'd8 :{Inter_ref_07_03,Inter_ref_06_03,Inter_ref_05_03,Inter_ref_04_03} <= RefFrameOutPadding; |
6'd7 :Inter_ref_08_03 <= RefFrameOutPadding[7:0]; |
|
6'd6 :{Inter_ref_03_04,Inter_ref_02_04,Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding; |
6'd5 :{Inter_ref_07_04,Inter_ref_06_04,Inter_ref_05_04,Inter_ref_04_04} <= RefFrameOutPadding; |
6'd4 :Inter_ref_08_04 <= RefFrameOutPadding[7:0]; |
|
6'd3 :{Inter_ref_03_05,Inter_ref_02_05,Inter_ref_01_05,Inter_ref_00_05} <= RefFrameOutPadding; |
6'd2 :{Inter_ref_07_05,Inter_ref_06_05,Inter_ref_05_05,Inter_ref_04_05} <= RefFrameOutPadding; |
6'd1 :Inter_ref_08_05 <= RefFrameOutPadding[7:0]; |
endcase |
2'b11: |
case (blk4x4_inter_preload_counter) |
6'd12:{Inter_ref_02_02,Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding[31:8]; |
6'd11:{Inter_ref_06_02,Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02} <= RefFrameOutPadding; |
6'd10:{Inter_ref_08_02,Inter_ref_07_02} <= RefFrameOutPadding[15:0]; |
|
6'd9 :{Inter_ref_02_03,Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding[31:8]; |
6'd8 :{Inter_ref_06_03,Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03} <= RefFrameOutPadding; |
6'd7 :{Inter_ref_08_03,Inter_ref_07_03} <= RefFrameOutPadding[15:0]; |
|
6'd6 :{Inter_ref_02_04,Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding[31:8]; |
6'd5 :{Inter_ref_06_04,Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04} <= RefFrameOutPadding; |
6'd4 :{Inter_ref_08_04,Inter_ref_07_04} <= RefFrameOutPadding[15:0]; |
|
6'd3 :{Inter_ref_02_05,Inter_ref_01_05,Inter_ref_00_05} <= RefFrameOutPadding[31:8]; |
6'd2 :{Inter_ref_06_05,Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05} <= RefFrameOutPadding; |
6'd1 :{Inter_ref_08_05,Inter_ref_07_05} <= RefFrameOutPadding[15:0]; |
endcase |
endcase |
`pos_Int: |
case (xInt_org_unclip_1to0) |
2'b00: |
case (blk4x4_inter_preload_counter) |
6'd4:{Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding; |
6'd3:{Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding; |
6'd2:{Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04} <= RefFrameOutPadding; |
6'd1:{Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05} <= RefFrameOutPadding; |
endcase |
2'b01: |
case (blk4x4_inter_preload_counter) |
6'd8:{Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding[31:8]; |
6'd7:Inter_ref_05_02 <= RefFrameOutPadding[7:0]; |
|
6'd6:{Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding[31:8]; |
6'd5:Inter_ref_05_03 <= RefFrameOutPadding[7:0]; |
|
6'd4:{Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04} <= RefFrameOutPadding[31:8]; |
6'd3:Inter_ref_05_04 <= RefFrameOutPadding[7:0]; |
|
6'd2:{Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05} <= RefFrameOutPadding[31:8]; |
6'd1:Inter_ref_05_05 <= RefFrameOutPadding[7:0]; |
endcase |
2'b10: |
case (blk4x4_inter_preload_counter) |
6'd8:{Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding[31:16]; |
6'd7:{Inter_ref_05_02,Inter_ref_04_02} <= RefFrameOutPadding[15:0]; |
|
6'd6:{Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding[31:16]; |
6'd5:{Inter_ref_05_03,Inter_ref_04_03} <= RefFrameOutPadding[15:0]; |
|
6'd4:{Inter_ref_03_04,Inter_ref_02_04} <= RefFrameOutPadding[31:16]; |
6'd3:{Inter_ref_05_04,Inter_ref_04_04} <= RefFrameOutPadding[15:0]; |
|
6'd2:{Inter_ref_03_05,Inter_ref_02_05} <= RefFrameOutPadding[31:16]; |
6'd1:{Inter_ref_05_05,Inter_ref_04_05} <= RefFrameOutPadding[15:0]; |
endcase |
2'b11: |
case (blk4x4_inter_preload_counter) |
6'd8:Inter_ref_02_02 <= RefFrameOutPadding[31:24]; |
6'd7:{Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02} <= RefFrameOutPadding[23:0]; |
|
6'd6:Inter_ref_02_03 <= RefFrameOutPadding[31:24]; |
6'd5:{Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03} <= RefFrameOutPadding[23:0]; |
|
6'd4:Inter_ref_02_04 <= RefFrameOutPadding[31:24]; |
6'd3:{Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04} <= RefFrameOutPadding[23:0]; |
|
6'd2:Inter_ref_02_05 <= RefFrameOutPadding[31:24]; |
6'd1:{Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05} <= RefFrameOutPadding[23:0]; |
endcase |
endcase |
`pos_e,`pos_g,`pos_p,`pos_r: |
case (xInt_org_unclip_1to0) |
2'b00: |
case (blk4x4_inter_preload_counter) |
6'd23:{Inter_ref_05_00,Inter_ref_04_00,Inter_ref_03_00,Inter_ref_02_00} <= RefFrameOutPadding; |
6'd22:Inter_ref_06_00 <= RefFrameOutPadding[7:0]; |
6'd21:{Inter_ref_05_01,Inter_ref_04_01,Inter_ref_03_01,Inter_ref_02_01} <= RefFrameOutPadding; |
6'd20:Inter_ref_06_01 <= RefFrameOutPadding[7:0]; |
|
6'd19:{Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding[31:16]; |
6'd18:{Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding; |
6'd17:{Inter_ref_08_02,Inter_ref_07_02,Inter_ref_06_02} <= RefFrameOutPadding[23:0]; |
6'd16:{Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding[31:16]; |
6'd15:{Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding; |
6'd14:{Inter_ref_08_03,Inter_ref_07_03,Inter_ref_06_03} <= RefFrameOutPadding[23:0]; |
6'd13:{Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding[31:16]; |
6'd12:{Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04} <= RefFrameOutPadding; |
6'd11:{Inter_ref_08_04,Inter_ref_07_04,Inter_ref_06_04} <= RefFrameOutPadding[23:0]; |
6'd10:{Inter_ref_01_05,Inter_ref_00_05} <= RefFrameOutPadding[31:16]; |
6'd9 :{Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05} <= RefFrameOutPadding; |
6'd8 :{Inter_ref_08_05,Inter_ref_07_05,Inter_ref_06_05} <= RefFrameOutPadding[23:0]; |
6'd7 :{Inter_ref_01_06,Inter_ref_00_06} <= RefFrameOutPadding[31:16]; |
6'd6 :{Inter_ref_05_06,Inter_ref_04_06,Inter_ref_03_06,Inter_ref_02_06} <= RefFrameOutPadding; |
6'd5 :{Inter_ref_08_06,Inter_ref_07_06,Inter_ref_06_06} <= RefFrameOutPadding[23:0]; |
|
6'd4 :{Inter_ref_05_07,Inter_ref_04_07,Inter_ref_03_07,Inter_ref_02_07} <= RefFrameOutPadding; |
6'd3 :Inter_ref_06_07 <= RefFrameOutPadding[7:0]; |
6'd2 :{Inter_ref_05_08,Inter_ref_04_08,Inter_ref_03_08,Inter_ref_02_08} <= RefFrameOutPadding; |
6'd1 :Inter_ref_06_08 <= RefFrameOutPadding[7:0]; |
endcase |
2'b01: |
case (blk4x4_inter_preload_counter) |
6'd23:{Inter_ref_04_00,Inter_ref_03_00,Inter_ref_02_00} <= RefFrameOutPadding[31:8]; |
6'd22:{Inter_ref_06_00,Inter_ref_05_00} <= RefFrameOutPadding[15:0]; |
6'd21:{Inter_ref_04_01,Inter_ref_03_01,Inter_ref_02_01} <= RefFrameOutPadding[31:8]; |
6'd20:{Inter_ref_06_01,Inter_ref_05_01} <= RefFrameOutPadding[15:0]; |
|
6'd19:Inter_ref_00_02 <= RefFrameOutPadding[31:24]; |
6'd18:{Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02,Inter_ref_01_02} <= RefFrameOutPadding; |
6'd17:{Inter_ref_08_02,Inter_ref_07_02,Inter_ref_06_02,Inter_ref_05_02} <= RefFrameOutPadding; |
6'd16:Inter_ref_00_03 <= RefFrameOutPadding[31:24]; |
6'd15:{Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03,Inter_ref_01_03} <= RefFrameOutPadding; |
6'd14:{Inter_ref_08_03,Inter_ref_07_03,Inter_ref_06_03,Inter_ref_05_03} <= RefFrameOutPadding; |
6'd13:Inter_ref_00_04 <= RefFrameOutPadding[31:24]; |
6'd12:{Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04,Inter_ref_01_04} <= RefFrameOutPadding; |
6'd11:{Inter_ref_08_04,Inter_ref_07_04,Inter_ref_06_04,Inter_ref_05_04} <= RefFrameOutPadding; |
6'd10:Inter_ref_00_05 <= RefFrameOutPadding[31:24]; |
6'd9 :{Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05,Inter_ref_01_05} <= RefFrameOutPadding; |
6'd8 :{Inter_ref_08_05,Inter_ref_07_05,Inter_ref_06_05,Inter_ref_05_05} <= RefFrameOutPadding; |
6'd7 :Inter_ref_00_06 <= RefFrameOutPadding[31:24]; |
6'd6 :{Inter_ref_04_06,Inter_ref_03_06,Inter_ref_02_06,Inter_ref_01_06} <= RefFrameOutPadding; |
6'd5 :{Inter_ref_08_06,Inter_ref_07_06,Inter_ref_06_06,Inter_ref_05_06} <= RefFrameOutPadding; |
|
6'd4 :{Inter_ref_04_07,Inter_ref_03_07,Inter_ref_02_07} <= RefFrameOutPadding[31:8]; |
6'd3 :{Inter_ref_06_07,Inter_ref_05_07} <= RefFrameOutPadding[15:0]; |
6'd2 :{Inter_ref_04_08,Inter_ref_03_08,Inter_ref_02_08} <= RefFrameOutPadding[31:8]; |
6'd1 :{Inter_ref_06_08,Inter_ref_05_08} <= RefFrameOutPadding[15:0]; |
endcase |
2'b10: |
case (blk4x4_inter_preload_counter) |
6'd23:{Inter_ref_03_00,Inter_ref_02_00} <= RefFrameOutPadding[31:16]; |
6'd22:{Inter_ref_06_00,Inter_ref_05_00,Inter_ref_04_00} <= RefFrameOutPadding[23:0]; |
6'd21:{Inter_ref_03_01,Inter_ref_02_01} <= RefFrameOutPadding[31:16]; |
6'd20:{Inter_ref_06_01,Inter_ref_05_01,Inter_ref_04_01} <= RefFrameOutPadding[23:0]; |
|
6'd19:{Inter_ref_03_02,Inter_ref_02_02,Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding; |
6'd18:{Inter_ref_07_02,Inter_ref_06_02,Inter_ref_05_02,Inter_ref_04_02} <= RefFrameOutPadding; |
6'd17:Inter_ref_08_02 <= RefFrameOutPadding[7:0]; |
6'd16:{Inter_ref_03_03,Inter_ref_02_03,Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding; |
6'd15:{Inter_ref_07_03,Inter_ref_06_03,Inter_ref_05_03,Inter_ref_04_03} <= RefFrameOutPadding; |
6'd14:Inter_ref_08_03 <= RefFrameOutPadding[7:0]; |
6'd13:{Inter_ref_03_04,Inter_ref_02_04,Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding; |
6'd12:{Inter_ref_07_04,Inter_ref_06_04,Inter_ref_05_04,Inter_ref_04_04} <= RefFrameOutPadding; |
6'd11:Inter_ref_08_04 <= RefFrameOutPadding[7:0]; |
6'd10:{Inter_ref_03_05,Inter_ref_02_05,Inter_ref_01_05,Inter_ref_00_05} <= RefFrameOutPadding; |
6'd9 :{Inter_ref_07_05,Inter_ref_06_05,Inter_ref_05_05,Inter_ref_04_05} <= RefFrameOutPadding; |
6'd8 :Inter_ref_08_05 <= RefFrameOutPadding[7:0]; |
6'd7 :{Inter_ref_03_06,Inter_ref_02_06,Inter_ref_01_06,Inter_ref_00_06} <= RefFrameOutPadding; |
6'd6 :{Inter_ref_07_06,Inter_ref_06_06,Inter_ref_05_06,Inter_ref_04_06} <= RefFrameOutPadding; |
6'd5 :Inter_ref_08_06 <= RefFrameOutPadding[7:0]; |
|
6'd4 :{Inter_ref_03_07,Inter_ref_02_07} <= RefFrameOutPadding[31:16]; |
6'd3 :{Inter_ref_06_07,Inter_ref_05_07,Inter_ref_04_07} <= RefFrameOutPadding[23:0]; |
6'd2 :{Inter_ref_03_08,Inter_ref_02_08} <= RefFrameOutPadding[31:16]; |
6'd1 :{Inter_ref_06_08,Inter_ref_05_08,Inter_ref_04_08} <= RefFrameOutPadding[23:0]; |
endcase |
2'b11: |
case (blk4x4_inter_preload_counter) |
6'd23:Inter_ref_02_00 <= RefFrameOutPadding[31:24]; |
6'd22:{Inter_ref_06_00,Inter_ref_05_00,Inter_ref_04_00,Inter_ref_03_00} <= RefFrameOutPadding; |
6'd21:Inter_ref_02_01 <= RefFrameOutPadding[31:24]; |
6'd20:{Inter_ref_06_01,Inter_ref_05_01,Inter_ref_04_01,Inter_ref_03_01} <= RefFrameOutPadding; |
|
6'd19:{Inter_ref_02_02,Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding[31:8]; |
6'd18:{Inter_ref_06_02,Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02} <= RefFrameOutPadding; |
6'd17:{Inter_ref_08_02,Inter_ref_07_02} <= RefFrameOutPadding[15:0]; |
6'd16:{Inter_ref_02_03,Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding[31:8]; |
6'd15:{Inter_ref_06_03,Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03} <= RefFrameOutPadding; |
6'd14:{Inter_ref_08_03,Inter_ref_07_03} <= RefFrameOutPadding[15:0]; |
6'd13:{Inter_ref_02_04,Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding[31:8]; |
6'd12:{Inter_ref_06_04,Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04} <= RefFrameOutPadding; |
6'd11:{Inter_ref_08_04,Inter_ref_07_04} <= RefFrameOutPadding[15:0]; |
6'd10:{Inter_ref_02_05,Inter_ref_01_05,Inter_ref_00_05} <= RefFrameOutPadding[31:8]; |
6'd9 :{Inter_ref_06_05,Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05} <= RefFrameOutPadding; |
6'd8 :{Inter_ref_08_05,Inter_ref_07_05} <= RefFrameOutPadding[15:0]; |
6'd7 :{Inter_ref_02_06,Inter_ref_01_06,Inter_ref_00_06} <= RefFrameOutPadding[31:8]; |
6'd6 :{Inter_ref_06_06,Inter_ref_05_06,Inter_ref_04_06,Inter_ref_03_06} <= RefFrameOutPadding; |
6'd5 :{Inter_ref_08_06,Inter_ref_07_06} <= RefFrameOutPadding[15:0]; |
|
6'd4 :Inter_ref_02_07 <= RefFrameOutPadding[31:24]; |
6'd3 :{Inter_ref_06_07,Inter_ref_05_07,Inter_ref_04_07,Inter_ref_03_07} <= RefFrameOutPadding; |
6'd2 :Inter_ref_02_08 <= RefFrameOutPadding[31:24]; |
6'd1 :{Inter_ref_06_08,Inter_ref_05_08,Inter_ref_04_08,Inter_ref_03_08} <= RefFrameOutPadding; |
endcase |
endcase |
endcase |
endcase |
else if (IsInterChroma && blk4x4_inter_preload_counter != 0) |
begin |
if (mv_below8x8_curr == 1'b0) |
begin |
if (xFracC == 0 && yFracC == 0) // 8 or 4 cycles |
case (xInt_org_unclip_1to0) |
2'b00: |
case (blk4x4_inter_preload_counter) |
6'd4:{Inter_ref_03_00,Inter_ref_02_00,Inter_ref_01_00,Inter_ref_00_00} <= RefFrameOutPadding; |
6'd3:{Inter_ref_03_01,Inter_ref_02_01,Inter_ref_01_01,Inter_ref_00_01} <= RefFrameOutPadding; |
6'd2:{Inter_ref_03_02,Inter_ref_02_02,Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding; |
6'd1:{Inter_ref_03_03,Inter_ref_02_03,Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding; |
endcase |
2'b01: |
case (blk4x4_inter_preload_counter) |
6'd8:{Inter_ref_02_00,Inter_ref_01_00,Inter_ref_00_00} <= RefFrameOutPadding[31:8]; |
6'd7:Inter_ref_03_00 <= RefFrameOutPadding[7:0]; |
6'd6:{Inter_ref_02_01,Inter_ref_01_01,Inter_ref_00_01} <= RefFrameOutPadding[31:8]; |
6'd5:Inter_ref_03_01 <= RefFrameOutPadding[7:0]; |
6'd4:{Inter_ref_02_02,Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding[31:8]; |
6'd3:Inter_ref_03_02 <= RefFrameOutPadding[7:0]; |
6'd2:{Inter_ref_02_03,Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding[31:8]; |
6'd1:Inter_ref_03_03 <= RefFrameOutPadding[7:0]; |
endcase |
2'b10: |
case (blk4x4_inter_preload_counter) |
6'd8:{Inter_ref_01_00,Inter_ref_00_00} <= RefFrameOutPadding[31:16]; |
6'd7:{Inter_ref_03_00,Inter_ref_02_00} <= RefFrameOutPadding[15:0]; |
6'd6:{Inter_ref_01_01,Inter_ref_00_01} <= RefFrameOutPadding[31:16]; |
6'd5:{Inter_ref_03_01,Inter_ref_02_01} <= RefFrameOutPadding[15:0]; |
6'd4:{Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding[31:16]; |
6'd3:{Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding[15:0]; |
6'd2:{Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding[31:16]; |
6'd1:{Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding[15:0]; |
endcase |
2'b11: |
case (blk4x4_inter_preload_counter) |
6'd8:Inter_ref_00_00 <= RefFrameOutPadding[31:24]; |
6'd7:{Inter_ref_03_00,Inter_ref_02_00,Inter_ref_01_00} <= RefFrameOutPadding[23:0]; |
6'd6:Inter_ref_00_01 <= RefFrameOutPadding[31:24]; |
6'd5:{Inter_ref_03_01,Inter_ref_02_01,Inter_ref_01_01} <= RefFrameOutPadding[23:0]; |
6'd4:Inter_ref_00_02 <= RefFrameOutPadding[31:24]; |
6'd3:{Inter_ref_03_02,Inter_ref_02_02,Inter_ref_01_02} <= RefFrameOutPadding[23:0]; |
6'd2:Inter_ref_00_03 <= RefFrameOutPadding[31:24]; |
6'd1:{Inter_ref_03_03,Inter_ref_02_03,Inter_ref_01_03} <= RefFrameOutPadding[23:0]; |
endcase |
endcase |
else |
case (xInt_org_unclip_1to0) |
2'b00: |
case(blk4x4_inter_preload_counter) |
6'd10:{Inter_ref_03_00,Inter_ref_02_00,Inter_ref_01_00,Inter_ref_00_00} <= RefFrameOutPadding; |
6'd9 :Inter_ref_04_00 <= RefFrameOutPadding[7:0]; |
6'd8 :{Inter_ref_03_01,Inter_ref_02_01,Inter_ref_01_01,Inter_ref_00_01} <= RefFrameOutPadding; |
6'd7 :Inter_ref_04_01 <= RefFrameOutPadding[7:0]; |
6'd6 :{Inter_ref_03_02,Inter_ref_02_02,Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding; |
6'd5 :Inter_ref_04_02 <= RefFrameOutPadding[7:0]; |
6'd4 :{Inter_ref_03_03,Inter_ref_02_03,Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding; |
6'd3 :Inter_ref_04_03 <= RefFrameOutPadding[7:0]; |
6'd2 :{Inter_ref_03_04,Inter_ref_02_04,Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding; |
6'd1 :Inter_ref_04_04 <= RefFrameOutPadding[7:0]; |
endcase |
2'b01: |
case (blk4x4_inter_preload_counter) |
6'd10:{Inter_ref_02_00,Inter_ref_01_00,Inter_ref_00_00} <= RefFrameOutPadding[31:8]; |
6'd9 :{Inter_ref_04_00,Inter_ref_03_00} <= RefFrameOutPadding[15:0]; |
6'd8 :{Inter_ref_02_01,Inter_ref_01_01,Inter_ref_00_01} <= RefFrameOutPadding[31:8]; |
6'd7 :{Inter_ref_04_01,Inter_ref_03_01} <= RefFrameOutPadding[15:0]; |
6'd6 :{Inter_ref_02_02,Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding[31:8]; |
6'd5 :{Inter_ref_04_02,Inter_ref_03_02} <= RefFrameOutPadding[15:0]; |
6'd4 :{Inter_ref_02_03,Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding[31:8]; |
6'd3 :{Inter_ref_04_03,Inter_ref_03_03} <= RefFrameOutPadding[15:0]; |
6'd2 :{Inter_ref_02_04,Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding[31:8]; |
6'd1 :{Inter_ref_04_04,Inter_ref_03_04} <= RefFrameOutPadding[15:0]; |
endcase |
2'b10: |
case (blk4x4_inter_preload_counter) |
6'd10:{Inter_ref_01_00,Inter_ref_00_00} <= RefFrameOutPadding[31:16]; |
6'd9 :{Inter_ref_04_00,Inter_ref_03_00,Inter_ref_02_00} <= RefFrameOutPadding[23:0]; |
6'd8 :{Inter_ref_01_01,Inter_ref_00_01} <= RefFrameOutPadding[31:16]; |
6'd7 :{Inter_ref_04_01,Inter_ref_03_01,Inter_ref_02_01} <= RefFrameOutPadding[23:0]; |
6'd6 :{Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding[31:16]; |
6'd5 :{Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding[23:0]; |
6'd4 :{Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding[31:16]; |
6'd3 :{Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding[23:0]; |
6'd2 :{Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding[31:16]; |
6'd1 :{Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04} <= RefFrameOutPadding[23:0]; |
endcase |
2'b11: |
case (blk4x4_inter_preload_counter) |
6'd10:Inter_ref_00_00 <= RefFrameOutPadding[31:24]; |
6'd9 :{Inter_ref_04_00,Inter_ref_03_00,Inter_ref_02_00,Inter_ref_01_00} <= RefFrameOutPadding; |
6'd8 :Inter_ref_00_01 <= RefFrameOutPadding[31:24]; |
6'd7 :{Inter_ref_04_01,Inter_ref_03_01,Inter_ref_02_01,Inter_ref_01_01} <= RefFrameOutPadding; |
6'd6 :Inter_ref_00_02 <= RefFrameOutPadding[31:24]; |
6'd5 :{Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02,Inter_ref_01_02} <= RefFrameOutPadding; |
6'd4 :Inter_ref_00_03 <= RefFrameOutPadding[31:24]; |
6'd3 :{Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03,Inter_ref_01_03} <= RefFrameOutPadding; |
6'd2 :Inter_ref_00_04 <= RefFrameOutPadding[31:24]; |
6'd1 :{Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04,Inter_ref_01_04} <= RefFrameOutPadding; |
endcase |
endcase |
end |
else // mv_below8x8_curr == 1'b1 |
begin |
if (xFracC == 0 && yFracC == 0) // 4 or 2 cycles |
case (xInt_org_unclip_1to0) |
2'b00: |
case (blk4x4_inter_preload_counter) |
6'd2:{Inter_ref_01_00,Inter_ref_00_00} <= RefFrameOutPadding[15:0]; |
6'd1:{Inter_ref_01_01,Inter_ref_00_01} <= RefFrameOutPadding[15:0]; |
endcase |
2'b01: |
case (blk4x4_inter_preload_counter) |
6'd2:{Inter_ref_01_00,Inter_ref_00_00} <= RefFrameOutPadding[23:8]; |
6'd1:{Inter_ref_01_01,Inter_ref_00_01} <= RefFrameOutPadding[23:8]; |
endcase |
2'b10: |
case (blk4x4_inter_preload_counter) |
6'd2:{Inter_ref_01_00,Inter_ref_00_00} <= RefFrameOutPadding[31:16]; |
6'd1:{Inter_ref_01_01,Inter_ref_00_01} <= RefFrameOutPadding[31:16]; |
endcase |
2'b11: |
case (blk4x4_inter_preload_counter) |
6'd4:Inter_ref_00_00 <= RefFrameOutPadding[31:24]; |
6'd3:Inter_ref_01_00 <= RefFrameOutPadding[7:0]; |
6'd2:Inter_ref_00_01 <= RefFrameOutPadding[31:24]; |
6'd1:Inter_ref_01_01 <= RefFrameOutPadding[7:0]; |
endcase |
endcase |
else // 6 or 3 cycles |
case (xInt_org_unclip_1to0) |
2'b00: |
case (blk4x4_inter_preload_counter) |
6'd3:{Inter_ref_02_00,Inter_ref_01_00,Inter_ref_00_00} <= RefFrameOutPadding[23:0]; |
6'd2:{Inter_ref_02_01,Inter_ref_01_01,Inter_ref_00_01} <= RefFrameOutPadding[23:0]; |
6'd1:{Inter_ref_02_02,Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding[23:0]; |
endcase |
2'b01: |
case (blk4x4_inter_preload_counter) |
6'd3:{Inter_ref_02_00,Inter_ref_01_00,Inter_ref_00_00} <= RefFrameOutPadding[31:8]; |
6'd2:{Inter_ref_02_01,Inter_ref_01_01,Inter_ref_00_01} <= RefFrameOutPadding[31:8]; |
6'd1:{Inter_ref_02_02,Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding[31:8]; |
endcase |
2'b10: |
case (blk4x4_inter_preload_counter) |
6'd6:{Inter_ref_01_00,Inter_ref_00_00} <= RefFrameOutPadding[31:16]; |
6'd5:Inter_ref_02_00 <= RefFrameOutPadding[7:0]; |
6'd4:{Inter_ref_01_01,Inter_ref_00_01} <= RefFrameOutPadding[31:16]; |
6'd3:Inter_ref_02_01 <= RefFrameOutPadding[7:0]; |
6'd2:{Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding[31:16]; |
6'd1:Inter_ref_02_02 <= RefFrameOutPadding[7:0]; |
endcase |
2'b11: |
case (blk4x4_inter_preload_counter) |
6'd6:Inter_ref_00_00 <= RefFrameOutPadding[31:24]; |
6'd5:{Inter_ref_02_00,Inter_ref_01_00} <= RefFrameOutPadding[15:0]; |
6'd4:Inter_ref_00_01 <= RefFrameOutPadding[31:24]; |
6'd3:{Inter_ref_02_01,Inter_ref_01_01} <= RefFrameOutPadding[15:0]; |
6'd2:Inter_ref_00_02 <= RefFrameOutPadding[31:24]; |
6'd1:{Inter_ref_02_02,Inter_ref_01_02} <= RefFrameOutPadding[15:0]; |
endcase |
endcase |
end |
end |
|
endmodule |
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/trunk/src/Inter_pred_top.v
0,0 → 1,703
//-------------------------------------------------------------------------------------------------- |
// Design : nova |
// Author(s) : Ke Xu |
// Email : eexuke@yahoo.com |
// File : Inter_pred_top.v |
// Generated : Oct 28, 2005 |
// Copyright (C) 2008 Ke Xu |
//------------------------------------------------------------------------------------------------- |
// Description |
// Top module of Inter prediction, including |
// Inter_pred_pipeline.v |
// Inter_pred_reg_control.v |
// Inter_pred_sliding_window.v |
// Inter_pred_LPE.v |
// Inter_pred_CPE.v |
//------------------------------------------------------------------------------------------------- |
|
// synopsys translate_off |
`include "timescale.v" |
// synopsys translate_on |
`include "nova_defines.v" |
|
module Inter_pred_top (clk,gclk_Inter_ref_rf,reset_n,mb_num_h,mb_num_v,trigger_blk4x4_inter_pred,blk4x4_rec_counter, |
mb_type_general_bit3,mv_is16x16,mv_below8x8,mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3, |
mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3,ref_frame_RAM_dout, |
|
Inter_pred_out0,Inter_pred_out1,Inter_pred_out2,Inter_pred_out3, |
blk4x4_inter_preload_counter,blk4x4_inter_calculate_counter,Inter_chroma2x2_counter, |
mv_below8x8_curr,pos_FracL,end_of_one_blk4x4_inter,Inter_blk4x4_pred_output_valid, |
ref_frame_RAM_rd,ref_frame_RAM_rd_addr); |
input clk; |
input gclk_Inter_ref_rf; |
input reset_n; |
input [3:0] mb_num_h,mb_num_v; |
input trigger_blk4x4_inter_pred; |
input [4:0] blk4x4_rec_counter; |
input mb_type_general_bit3; |
input mv_is16x16; |
input [3:0] mv_below8x8; |
input [31:0] mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3; |
input [31:0] mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3; |
input [31:0] ref_frame_RAM_dout; |
|
output [7:0] Inter_pred_out0,Inter_pred_out1,Inter_pred_out2,Inter_pred_out3; |
output [5:0] blk4x4_inter_preload_counter; |
output [3:0] blk4x4_inter_calculate_counter; |
output [1:0] Inter_chroma2x2_counter; |
output mv_below8x8_curr; |
output [3:0] pos_FracL; |
output end_of_one_blk4x4_inter; |
output [1:0] Inter_blk4x4_pred_output_valid; |
output ref_frame_RAM_rd; |
output [13:0] ref_frame_RAM_rd_addr; |
|
wire [7:0] LPE0_out,LPE1_out,LPE2_out,LPE3_out; |
wire [7:0] CPE0_out,CPE1_out,CPE2_out,CPE3_out; |
wire [5:0] blk4x4_inter_preload_counter; |
wire mv_below8x8_curr; |
wire IsInterLuma,IsInterChroma; |
wire Is_InterChromaCopy; |
wire [8:0] xInt_addr_unclip; |
wire [1:0] xInt_org_unclip_1to0; |
wire [2:0] xFracC,yFracC; |
|
wire [7:0] Inter_ref_00_00,Inter_ref_01_00,Inter_ref_02_00,Inter_ref_03_00,Inter_ref_04_00,Inter_ref_05_00; |
wire [7:0] Inter_ref_06_00,Inter_ref_07_00,Inter_ref_08_00,Inter_ref_09_00,Inter_ref_10_00,Inter_ref_11_00,Inter_ref_12_00; |
wire [7:0] Inter_ref_00_01,Inter_ref_01_01,Inter_ref_02_01,Inter_ref_03_01,Inter_ref_04_01,Inter_ref_05_01; |
wire [7:0] Inter_ref_06_01,Inter_ref_07_01,Inter_ref_08_01,Inter_ref_09_01,Inter_ref_10_01,Inter_ref_11_01,Inter_ref_12_01; |
wire [7:0] Inter_ref_00_02,Inter_ref_01_02,Inter_ref_02_02,Inter_ref_03_02,Inter_ref_04_02,Inter_ref_05_02; |
wire [7:0] Inter_ref_06_02,Inter_ref_07_02,Inter_ref_08_02,Inter_ref_09_02,Inter_ref_10_02,Inter_ref_11_02,Inter_ref_12_02; |
wire [7:0] Inter_ref_00_03,Inter_ref_01_03,Inter_ref_02_03,Inter_ref_03_03,Inter_ref_04_03,Inter_ref_05_03; |
wire [7:0] Inter_ref_06_03,Inter_ref_07_03,Inter_ref_08_03,Inter_ref_09_03,Inter_ref_10_03,Inter_ref_11_03,Inter_ref_12_03; |
wire [7:0] Inter_ref_00_04,Inter_ref_01_04,Inter_ref_02_04,Inter_ref_03_04,Inter_ref_04_04,Inter_ref_05_04; |
wire [7:0] Inter_ref_06_04,Inter_ref_07_04,Inter_ref_08_04,Inter_ref_09_04,Inter_ref_10_04,Inter_ref_11_04,Inter_ref_12_04; |
wire [7:0] Inter_ref_00_05,Inter_ref_01_05,Inter_ref_02_05,Inter_ref_03_05,Inter_ref_04_05,Inter_ref_05_05; |
wire [7:0] Inter_ref_06_05,Inter_ref_07_05,Inter_ref_08_05,Inter_ref_09_05,Inter_ref_10_05,Inter_ref_11_05,Inter_ref_12_05; |
wire [7:0] Inter_ref_00_06,Inter_ref_01_06,Inter_ref_02_06,Inter_ref_03_06,Inter_ref_04_06,Inter_ref_05_06; |
wire [7:0] Inter_ref_06_06,Inter_ref_07_06,Inter_ref_08_06,Inter_ref_09_06,Inter_ref_10_06,Inter_ref_11_06,Inter_ref_12_06; |
wire [7:0] Inter_ref_00_07,Inter_ref_01_07,Inter_ref_02_07,Inter_ref_03_07,Inter_ref_04_07,Inter_ref_05_07; |
wire [7:0] Inter_ref_06_07,Inter_ref_07_07,Inter_ref_08_07,Inter_ref_09_07,Inter_ref_10_07,Inter_ref_11_07,Inter_ref_12_07; |
wire [7:0] Inter_ref_00_08,Inter_ref_01_08,Inter_ref_02_08,Inter_ref_03_08,Inter_ref_04_08,Inter_ref_05_08; |
wire [7:0] Inter_ref_06_08,Inter_ref_07_08,Inter_ref_08_08,Inter_ref_09_08,Inter_ref_10_08,Inter_ref_11_08,Inter_ref_12_08; |
wire [7:0] Inter_ref_00_09,Inter_ref_01_09,Inter_ref_02_09,Inter_ref_03_09,Inter_ref_04_09,Inter_ref_05_09; |
wire [7:0] Inter_ref_06_09,Inter_ref_07_09,Inter_ref_08_09,Inter_ref_09_09,Inter_ref_10_09,Inter_ref_11_09,Inter_ref_12_09; |
wire [7:0] Inter_ref_00_10,Inter_ref_01_10,Inter_ref_02_10,Inter_ref_03_10,Inter_ref_04_10,Inter_ref_05_10; |
wire [7:0] Inter_ref_06_10,Inter_ref_07_10,Inter_ref_08_10,Inter_ref_09_10,Inter_ref_10_10,Inter_ref_11_10,Inter_ref_12_10; |
wire [7:0] Inter_ref_00_11,Inter_ref_01_11,Inter_ref_02_11,Inter_ref_03_11,Inter_ref_04_11,Inter_ref_05_11; |
wire [7:0] Inter_ref_06_11,Inter_ref_07_11,Inter_ref_08_11,Inter_ref_09_11,Inter_ref_10_11,Inter_ref_11_11,Inter_ref_12_11; |
wire [7:0] Inter_ref_00_12,Inter_ref_01_12,Inter_ref_02_12,Inter_ref_03_12,Inter_ref_04_12,Inter_ref_05_12; |
wire [7:0] Inter_ref_06_12,Inter_ref_07_12,Inter_ref_08_12,Inter_ref_09_12,Inter_ref_10_12,Inter_ref_11_12,Inter_ref_12_12; |
|
wire [7:0] Inter_pix_copy0,Inter_pix_copy1,Inter_pix_copy2,Inter_pix_copy3; |
wire [7:0] Inter_H_window_0_0,Inter_H_window_1_0,Inter_H_window_2_0,Inter_H_window_3_0,Inter_H_window_4_0,Inter_H_window_5_0; |
wire [7:0] Inter_H_window_0_1,Inter_H_window_1_1,Inter_H_window_2_1,Inter_H_window_3_1,Inter_H_window_4_1,Inter_H_window_5_1; |
wire [7:0] Inter_H_window_0_2,Inter_H_window_1_2,Inter_H_window_2_2,Inter_H_window_3_2,Inter_H_window_4_2,Inter_H_window_5_2; |
wire [7:0] Inter_H_window_0_3,Inter_H_window_1_3,Inter_H_window_2_3,Inter_H_window_3_3,Inter_H_window_4_3,Inter_H_window_5_3; |
wire [7:0] Inter_H_window_0_4,Inter_H_window_1_4,Inter_H_window_2_4,Inter_H_window_3_4,Inter_H_window_4_4,Inter_H_window_5_4; |
wire [7:0] Inter_H_window_0_5,Inter_H_window_1_5,Inter_H_window_2_5,Inter_H_window_3_5,Inter_H_window_4_5,Inter_H_window_5_5; |
wire [7:0] Inter_H_window_0_6,Inter_H_window_1_6,Inter_H_window_2_6,Inter_H_window_3_6,Inter_H_window_4_6,Inter_H_window_5_6; |
wire [7:0] Inter_H_window_0_7,Inter_H_window_1_7,Inter_H_window_2_7,Inter_H_window_3_7,Inter_H_window_4_7,Inter_H_window_5_7; |
wire [7:0] Inter_H_window_0_8,Inter_H_window_1_8,Inter_H_window_2_8,Inter_H_window_3_8,Inter_H_window_4_8,Inter_H_window_5_8; |
wire [7:0] Inter_V_window_0,Inter_V_window_1,Inter_V_window_2,Inter_V_window_3,Inter_V_window_4; |
wire [7:0] Inter_V_window_5,Inter_V_window_6,Inter_V_window_7,Inter_V_window_8; |
wire [7:0] Inter_C_window_0_0,Inter_C_window_1_0,Inter_C_window_2_0; |
wire [7:0] Inter_C_window_0_1,Inter_C_window_1_1,Inter_C_window_2_1; |
wire [7:0] Inter_C_window_0_2,Inter_C_window_1_2,Inter_C_window_2_2; |
wire [7:0] Inter_bi_window_0,Inter_bi_window_1,Inter_bi_window_2,Inter_bi_window_3; |
|
Inter_pred_pipeline Inter_pred_pipeline( |
.clk(clk), |
.reset_n(reset_n), |
.mb_num_h(mb_num_h), |
.mb_num_v(mb_num_v), |
.trigger_blk4x4_inter_pred(trigger_blk4x4_inter_pred), |
.blk4x4_rec_counter(blk4x4_rec_counter), |
.mb_type_general_bit3(mb_type_general_bit3), |
.mv_is16x16(mv_is16x16), |
.mv_below8x8(mv_below8x8), |
.mvx_CurrMb0(mvx_CurrMb0), |
.mvx_CurrMb1(mvx_CurrMb1), |
.mvx_CurrMb2(mvx_CurrMb2), |
.mvx_CurrMb3(mvx_CurrMb3), |
.mvy_CurrMb0(mvy_CurrMb0), |
.mvy_CurrMb1(mvy_CurrMb1), |
.mvy_CurrMb2(mvy_CurrMb2), |
.mvy_CurrMb3(mvy_CurrMb3), |
.Inter_pix_copy0(Inter_pix_copy0), |
.Inter_pix_copy1(Inter_pix_copy1), |
.Inter_pix_copy2(Inter_pix_copy2), |
.Inter_pix_copy3(Inter_pix_copy3), |
.LPE0_out(LPE0_out), |
.LPE1_out(LPE1_out), |
.LPE2_out(LPE2_out), |
.LPE3_out(LPE3_out), |
.CPE0_out(CPE0_out), |
.CPE1_out(CPE1_out), |
.CPE2_out(CPE2_out), |
.CPE3_out(CPE3_out), |
|
.mv_below8x8_curr(mv_below8x8_curr), |
.blk4x4_inter_preload_counter(blk4x4_inter_preload_counter), |
.blk4x4_inter_calculate_counter(blk4x4_inter_calculate_counter), |
.Inter_chroma2x2_counter(Inter_chroma2x2_counter), |
.end_of_one_blk4x4_inter(end_of_one_blk4x4_inter), |
.IsInterLuma(IsInterLuma), |
.IsInterChroma(IsInterChroma), |
.Is_InterChromaCopy(Is_InterChromaCopy), |
.xInt_addr_unclip(xInt_addr_unclip), |
.xInt_org_unclip_1to0(xInt_org_unclip_1to0), |
.pos_FracL(pos_FracL), |
.xFracC(xFracC), |
.yFracC(yFracC), |
.Inter_pred_out0(Inter_pred_out0), |
.Inter_pred_out1(Inter_pred_out1), |
.Inter_pred_out2(Inter_pred_out2), |
.Inter_pred_out3(Inter_pred_out3), |
.Inter_blk4x4_pred_output_valid(Inter_blk4x4_pred_output_valid), |
.ref_frame_RAM_rd(ref_frame_RAM_rd), |
.ref_frame_RAM_rd_addr(ref_frame_RAM_rd_addr) |
); |
|
Inter_pred_reg_ctrl Inter_pred_reg_ctrl ( |
.gclk_Inter_ref_rf(gclk_Inter_ref_rf), |
.reset_n(reset_n), |
.blk4x4_inter_preload_counter(blk4x4_inter_preload_counter), |
.ref_frame_RAM_dout(ref_frame_RAM_dout), |
.IsInterLuma(IsInterLuma), |
.IsInterChroma(IsInterChroma), |
.xInt_addr_unclip(xInt_addr_unclip), |
.xInt_org_unclip_1to0(xInt_org_unclip_1to0), |
.pos_FracL(pos_FracL), |
.xFracC(xFracC), |
.yFracC(yFracC), |
.mv_below8x8_curr(mv_below8x8_curr), |
|
.Inter_ref_00_00(Inter_ref_00_00), |
.Inter_ref_01_00(Inter_ref_01_00), |
.Inter_ref_02_00(Inter_ref_02_00), |
.Inter_ref_03_00(Inter_ref_03_00), |
.Inter_ref_04_00(Inter_ref_04_00), |
.Inter_ref_05_00(Inter_ref_05_00), |
.Inter_ref_06_00(Inter_ref_06_00), |
.Inter_ref_07_00(Inter_ref_07_00), |
.Inter_ref_08_00(Inter_ref_08_00), |
.Inter_ref_09_00(Inter_ref_09_00), |
.Inter_ref_10_00(Inter_ref_10_00), |
.Inter_ref_11_00(Inter_ref_11_00), |
.Inter_ref_12_00(Inter_ref_12_00), |
.Inter_ref_00_01(Inter_ref_00_01), |
.Inter_ref_01_01(Inter_ref_01_01), |
.Inter_ref_02_01(Inter_ref_02_01), |
.Inter_ref_03_01(Inter_ref_03_01), |
.Inter_ref_04_01(Inter_ref_04_01), |
.Inter_ref_05_01(Inter_ref_05_01), |
.Inter_ref_06_01(Inter_ref_06_01), |
.Inter_ref_07_01(Inter_ref_07_01), |
.Inter_ref_08_01(Inter_ref_08_01), |
.Inter_ref_09_01(Inter_ref_09_01), |
.Inter_ref_10_01(Inter_ref_10_01), |
.Inter_ref_11_01(Inter_ref_11_01), |
.Inter_ref_12_01(Inter_ref_12_01), |
.Inter_ref_00_02(Inter_ref_00_02), |
.Inter_ref_01_02(Inter_ref_01_02), |
.Inter_ref_02_02(Inter_ref_02_02), |
.Inter_ref_03_02(Inter_ref_03_02), |
.Inter_ref_04_02(Inter_ref_04_02), |
.Inter_ref_05_02(Inter_ref_05_02), |
.Inter_ref_06_02(Inter_ref_06_02), |
.Inter_ref_07_02(Inter_ref_07_02), |
.Inter_ref_08_02(Inter_ref_08_02), |
.Inter_ref_09_02(Inter_ref_09_02), |
.Inter_ref_10_02(Inter_ref_10_02), |
.Inter_ref_11_02(Inter_ref_11_02), |
.Inter_ref_12_02(Inter_ref_12_02), |
.Inter_ref_00_03(Inter_ref_00_03), |
.Inter_ref_01_03(Inter_ref_01_03), |
.Inter_ref_02_03(Inter_ref_02_03), |
.Inter_ref_03_03(Inter_ref_03_03), |
.Inter_ref_04_03(Inter_ref_04_03), |
.Inter_ref_05_03(Inter_ref_05_03), |
.Inter_ref_06_03(Inter_ref_06_03), |
.Inter_ref_07_03(Inter_ref_07_03), |
.Inter_ref_08_03(Inter_ref_08_03), |
.Inter_ref_09_03(Inter_ref_09_03), |
.Inter_ref_10_03(Inter_ref_10_03), |
.Inter_ref_11_03(Inter_ref_11_03), |
.Inter_ref_12_03(Inter_ref_12_03), |
.Inter_ref_00_04(Inter_ref_00_04), |
.Inter_ref_01_04(Inter_ref_01_04), |
.Inter_ref_02_04(Inter_ref_02_04), |
.Inter_ref_03_04(Inter_ref_03_04), |
.Inter_ref_04_04(Inter_ref_04_04), |
.Inter_ref_05_04(Inter_ref_05_04), |
.Inter_ref_06_04(Inter_ref_06_04), |
.Inter_ref_07_04(Inter_ref_07_04), |
.Inter_ref_08_04(Inter_ref_08_04), |
.Inter_ref_09_04(Inter_ref_09_04), |
.Inter_ref_10_04(Inter_ref_10_04), |
.Inter_ref_11_04(Inter_ref_11_04), |
.Inter_ref_12_04(Inter_ref_12_04), |
.Inter_ref_00_05(Inter_ref_00_05), |
.Inter_ref_01_05(Inter_ref_01_05), |
.Inter_ref_02_05(Inter_ref_02_05), |
.Inter_ref_03_05(Inter_ref_03_05), |
.Inter_ref_04_05(Inter_ref_04_05), |
.Inter_ref_05_05(Inter_ref_05_05), |
.Inter_ref_06_05(Inter_ref_06_05), |
.Inter_ref_07_05(Inter_ref_07_05), |
.Inter_ref_08_05(Inter_ref_08_05), |
.Inter_ref_09_05(Inter_ref_09_05), |
.Inter_ref_10_05(Inter_ref_10_05), |
.Inter_ref_11_05(Inter_ref_11_05), |
.Inter_ref_12_05(Inter_ref_12_05), |
.Inter_ref_00_06(Inter_ref_00_06), |
.Inter_ref_01_06(Inter_ref_01_06), |
.Inter_ref_02_06(Inter_ref_02_06), |
.Inter_ref_03_06(Inter_ref_03_06), |
.Inter_ref_04_06(Inter_ref_04_06), |
.Inter_ref_05_06(Inter_ref_05_06), |
.Inter_ref_06_06(Inter_ref_06_06), |
.Inter_ref_07_06(Inter_ref_07_06), |
.Inter_ref_08_06(Inter_ref_08_06), |
.Inter_ref_09_06(Inter_ref_09_06), |
.Inter_ref_10_06(Inter_ref_10_06), |
.Inter_ref_11_06(Inter_ref_11_06), |
.Inter_ref_12_06(Inter_ref_12_06), |
.Inter_ref_00_07(Inter_ref_00_07), |
.Inter_ref_01_07(Inter_ref_01_07), |
.Inter_ref_02_07(Inter_ref_02_07), |
.Inter_ref_03_07(Inter_ref_03_07), |
.Inter_ref_04_07(Inter_ref_04_07), |
.Inter_ref_05_07(Inter_ref_05_07), |
.Inter_ref_06_07(Inter_ref_06_07), |
.Inter_ref_07_07(Inter_ref_07_07), |
.Inter_ref_08_07(Inter_ref_08_07), |
.Inter_ref_09_07(Inter_ref_09_07), |
.Inter_ref_10_07(Inter_ref_10_07), |
.Inter_ref_11_07(Inter_ref_11_07), |
.Inter_ref_12_07(Inter_ref_12_07), |
.Inter_ref_00_08(Inter_ref_00_08), |
.Inter_ref_01_08(Inter_ref_01_08), |
.Inter_ref_02_08(Inter_ref_02_08), |
.Inter_ref_03_08(Inter_ref_03_08), |
.Inter_ref_04_08(Inter_ref_04_08), |
.Inter_ref_05_08(Inter_ref_05_08), |
.Inter_ref_06_08(Inter_ref_06_08), |
.Inter_ref_07_08(Inter_ref_07_08), |
.Inter_ref_08_08(Inter_ref_08_08), |
.Inter_ref_09_08(Inter_ref_09_08), |
.Inter_ref_10_08(Inter_ref_10_08), |
.Inter_ref_11_08(Inter_ref_11_08), |
.Inter_ref_12_08(Inter_ref_12_08), |
.Inter_ref_00_09(Inter_ref_00_09), |
.Inter_ref_01_09(Inter_ref_01_09), |
.Inter_ref_02_09(Inter_ref_02_09), |
.Inter_ref_03_09(Inter_ref_03_09), |
.Inter_ref_04_09(Inter_ref_04_09), |
.Inter_ref_05_09(Inter_ref_05_09), |
.Inter_ref_06_09(Inter_ref_06_09), |
.Inter_ref_07_09(Inter_ref_07_09), |
.Inter_ref_08_09(Inter_ref_08_09), |
.Inter_ref_09_09(Inter_ref_09_09), |
.Inter_ref_10_09(Inter_ref_10_09), |
.Inter_ref_11_09(Inter_ref_11_09), |
.Inter_ref_12_09(Inter_ref_12_09), |
.Inter_ref_00_10(Inter_ref_00_10), |
.Inter_ref_01_10(Inter_ref_01_10), |
.Inter_ref_02_10(Inter_ref_02_10), |
.Inter_ref_03_10(Inter_ref_03_10), |
.Inter_ref_04_10(Inter_ref_04_10), |
.Inter_ref_05_10(Inter_ref_05_10), |
.Inter_ref_06_10(Inter_ref_06_10), |
.Inter_ref_07_10(Inter_ref_07_10), |
.Inter_ref_08_10(Inter_ref_08_10), |
.Inter_ref_09_10(Inter_ref_09_10), |
.Inter_ref_10_10(Inter_ref_10_10), |
.Inter_ref_11_10(Inter_ref_11_10), |
.Inter_ref_12_10(Inter_ref_12_10), |
.Inter_ref_00_11(Inter_ref_00_11), |
.Inter_ref_01_11(Inter_ref_01_11), |
.Inter_ref_02_11(Inter_ref_02_11), |
.Inter_ref_03_11(Inter_ref_03_11), |
.Inter_ref_04_11(Inter_ref_04_11), |
.Inter_ref_05_11(Inter_ref_05_11), |
.Inter_ref_06_11(Inter_ref_06_11), |
.Inter_ref_07_11(Inter_ref_07_11), |
.Inter_ref_08_11(Inter_ref_08_11), |
.Inter_ref_09_11(Inter_ref_09_11), |
.Inter_ref_10_11(Inter_ref_10_11), |
.Inter_ref_11_11(Inter_ref_11_11), |
.Inter_ref_12_11(Inter_ref_12_11), |
.Inter_ref_00_12(Inter_ref_00_12), |
.Inter_ref_01_12(Inter_ref_01_12), |
.Inter_ref_02_12(Inter_ref_02_12), |
.Inter_ref_03_12(Inter_ref_03_12), |
.Inter_ref_04_12(Inter_ref_04_12), |
.Inter_ref_05_12(Inter_ref_05_12), |
.Inter_ref_06_12(Inter_ref_06_12), |
.Inter_ref_07_12(Inter_ref_07_12), |
.Inter_ref_08_12(Inter_ref_08_12), |
.Inter_ref_09_12(Inter_ref_09_12), |
.Inter_ref_10_12(Inter_ref_10_12), |
.Inter_ref_11_12(Inter_ref_11_12), |
.Inter_ref_12_12(Inter_ref_12_12) |
); |
Inter_pred_sliding_window Inter_pred_sliding_window ( |
.IsInterLuma(IsInterLuma), |
.IsInterChroma(IsInterChroma), |
.Is_InterChromaCopy(Is_InterChromaCopy), |
.mv_below8x8_curr(mv_below8x8_curr), |
.pos_FracL(pos_FracL), |
.blk4x4_rec_counter_1to0(blk4x4_rec_counter[1:0]), |
.blk4x4_inter_calculate_counter(blk4x4_inter_calculate_counter), |
.Inter_ref_00_00(Inter_ref_00_00), |
.Inter_ref_01_00(Inter_ref_01_00), |
.Inter_ref_02_00(Inter_ref_02_00), |
.Inter_ref_03_00(Inter_ref_03_00), |
.Inter_ref_04_00(Inter_ref_04_00), |
.Inter_ref_05_00(Inter_ref_05_00), |
.Inter_ref_06_00(Inter_ref_06_00), |
.Inter_ref_07_00(Inter_ref_07_00), |
.Inter_ref_08_00(Inter_ref_08_00), |
.Inter_ref_09_00(Inter_ref_09_00), |
.Inter_ref_10_00(Inter_ref_10_00), |
.Inter_ref_11_00(Inter_ref_11_00), |
.Inter_ref_12_00(Inter_ref_12_00), |
.Inter_ref_00_01(Inter_ref_00_01), |
.Inter_ref_01_01(Inter_ref_01_01), |
.Inter_ref_02_01(Inter_ref_02_01), |
.Inter_ref_03_01(Inter_ref_03_01), |
.Inter_ref_04_01(Inter_ref_04_01), |
.Inter_ref_05_01(Inter_ref_05_01), |
.Inter_ref_06_01(Inter_ref_06_01), |
.Inter_ref_07_01(Inter_ref_07_01), |
.Inter_ref_08_01(Inter_ref_08_01), |
.Inter_ref_09_01(Inter_ref_09_01), |
.Inter_ref_10_01(Inter_ref_10_01), |
.Inter_ref_11_01(Inter_ref_11_01), |
.Inter_ref_12_01(Inter_ref_12_01), |
.Inter_ref_00_02(Inter_ref_00_02), |
.Inter_ref_01_02(Inter_ref_01_02), |
.Inter_ref_02_02(Inter_ref_02_02), |
.Inter_ref_03_02(Inter_ref_03_02), |
.Inter_ref_04_02(Inter_ref_04_02), |
.Inter_ref_05_02(Inter_ref_05_02), |
.Inter_ref_06_02(Inter_ref_06_02), |
.Inter_ref_07_02(Inter_ref_07_02), |
.Inter_ref_08_02(Inter_ref_08_02), |
.Inter_ref_09_02(Inter_ref_09_02), |
.Inter_ref_10_02(Inter_ref_10_02), |
.Inter_ref_11_02(Inter_ref_11_02), |
.Inter_ref_12_02(Inter_ref_12_02), |
.Inter_ref_00_03(Inter_ref_00_03), |
.Inter_ref_01_03(Inter_ref_01_03), |
.Inter_ref_02_03(Inter_ref_02_03), |
.Inter_ref_03_03(Inter_ref_03_03), |
.Inter_ref_04_03(Inter_ref_04_03), |
.Inter_ref_05_03(Inter_ref_05_03), |
.Inter_ref_06_03(Inter_ref_06_03), |
.Inter_ref_07_03(Inter_ref_07_03), |
.Inter_ref_08_03(Inter_ref_08_03), |
.Inter_ref_09_03(Inter_ref_09_03), |
.Inter_ref_10_03(Inter_ref_10_03), |
.Inter_ref_11_03(Inter_ref_11_03), |
.Inter_ref_12_03(Inter_ref_12_03), |
.Inter_ref_00_04(Inter_ref_00_04), |
.Inter_ref_01_04(Inter_ref_01_04), |
.Inter_ref_02_04(Inter_ref_02_04), |
.Inter_ref_03_04(Inter_ref_03_04), |
.Inter_ref_04_04(Inter_ref_04_04), |
.Inter_ref_05_04(Inter_ref_05_04), |
.Inter_ref_06_04(Inter_ref_06_04), |
.Inter_ref_07_04(Inter_ref_07_04), |
.Inter_ref_08_04(Inter_ref_08_04), |
.Inter_ref_09_04(Inter_ref_09_04), |
.Inter_ref_10_04(Inter_ref_10_04), |
.Inter_ref_11_04(Inter_ref_11_04), |
.Inter_ref_12_04(Inter_ref_12_04), |
.Inter_ref_00_05(Inter_ref_00_05), |
.Inter_ref_01_05(Inter_ref_01_05), |
.Inter_ref_02_05(Inter_ref_02_05), |
.Inter_ref_03_05(Inter_ref_03_05), |
.Inter_ref_04_05(Inter_ref_04_05), |
.Inter_ref_05_05(Inter_ref_05_05), |
.Inter_ref_06_05(Inter_ref_06_05), |
.Inter_ref_07_05(Inter_ref_07_05), |
.Inter_ref_08_05(Inter_ref_08_05), |
.Inter_ref_09_05(Inter_ref_09_05), |
.Inter_ref_10_05(Inter_ref_10_05), |
.Inter_ref_11_05(Inter_ref_11_05), |
.Inter_ref_12_05(Inter_ref_12_05), |
.Inter_ref_00_06(Inter_ref_00_06), |
.Inter_ref_01_06(Inter_ref_01_06), |
.Inter_ref_02_06(Inter_ref_02_06), |
.Inter_ref_03_06(Inter_ref_03_06), |
.Inter_ref_04_06(Inter_ref_04_06), |
.Inter_ref_05_06(Inter_ref_05_06), |
.Inter_ref_06_06(Inter_ref_06_06), |
.Inter_ref_07_06(Inter_ref_07_06), |
.Inter_ref_08_06(Inter_ref_08_06), |
.Inter_ref_09_06(Inter_ref_09_06), |
.Inter_ref_10_06(Inter_ref_10_06), |
.Inter_ref_11_06(Inter_ref_11_06), |
.Inter_ref_12_06(Inter_ref_12_06), |
.Inter_ref_00_07(Inter_ref_00_07), |
.Inter_ref_01_07(Inter_ref_01_07), |
.Inter_ref_02_07(Inter_ref_02_07), |
.Inter_ref_03_07(Inter_ref_03_07), |
.Inter_ref_04_07(Inter_ref_04_07), |
.Inter_ref_05_07(Inter_ref_05_07), |
.Inter_ref_06_07(Inter_ref_06_07), |
.Inter_ref_07_07(Inter_ref_07_07), |
.Inter_ref_08_07(Inter_ref_08_07), |
.Inter_ref_09_07(Inter_ref_09_07), |
.Inter_ref_10_07(Inter_ref_10_07), |
.Inter_ref_11_07(Inter_ref_11_07), |
.Inter_ref_12_07(Inter_ref_12_07), |
.Inter_ref_00_08(Inter_ref_00_08), |
.Inter_ref_01_08(Inter_ref_01_08), |
.Inter_ref_02_08(Inter_ref_02_08), |
.Inter_ref_03_08(Inter_ref_03_08), |
.Inter_ref_04_08(Inter_ref_04_08), |
.Inter_ref_05_08(Inter_ref_05_08), |
.Inter_ref_06_08(Inter_ref_06_08), |
.Inter_ref_07_08(Inter_ref_07_08), |
.Inter_ref_08_08(Inter_ref_08_08), |
.Inter_ref_09_08(Inter_ref_09_08), |
.Inter_ref_10_08(Inter_ref_10_08), |
.Inter_ref_11_08(Inter_ref_11_08), |
.Inter_ref_12_08(Inter_ref_12_08), |
.Inter_ref_00_09(Inter_ref_00_09), |
.Inter_ref_01_09(Inter_ref_01_09), |
.Inter_ref_02_09(Inter_ref_02_09), |
.Inter_ref_03_09(Inter_ref_03_09), |
.Inter_ref_04_09(Inter_ref_04_09), |
.Inter_ref_05_09(Inter_ref_05_09), |
.Inter_ref_06_09(Inter_ref_06_09), |
.Inter_ref_07_09(Inter_ref_07_09), |
.Inter_ref_08_09(Inter_ref_08_09), |
.Inter_ref_09_09(Inter_ref_09_09), |
.Inter_ref_10_09(Inter_ref_10_09), |
.Inter_ref_11_09(Inter_ref_11_09), |
.Inter_ref_12_09(Inter_ref_12_09), |
.Inter_ref_00_10(Inter_ref_00_10), |
.Inter_ref_01_10(Inter_ref_01_10), |
.Inter_ref_02_10(Inter_ref_02_10), |
.Inter_ref_03_10(Inter_ref_03_10), |
.Inter_ref_04_10(Inter_ref_04_10), |
.Inter_ref_05_10(Inter_ref_05_10), |
.Inter_ref_06_10(Inter_ref_06_10), |
.Inter_ref_07_10(Inter_ref_07_10), |
.Inter_ref_08_10(Inter_ref_08_10), |
.Inter_ref_09_10(Inter_ref_09_10), |
.Inter_ref_10_10(Inter_ref_10_10), |
.Inter_ref_11_10(Inter_ref_11_10), |
.Inter_ref_12_10(Inter_ref_12_10), |
.Inter_ref_00_11(Inter_ref_00_11), |
.Inter_ref_01_11(Inter_ref_01_11), |
.Inter_ref_02_11(Inter_ref_02_11), |
.Inter_ref_03_11(Inter_ref_03_11), |
.Inter_ref_04_11(Inter_ref_04_11), |
.Inter_ref_05_11(Inter_ref_05_11), |
.Inter_ref_06_11(Inter_ref_06_11), |
.Inter_ref_07_11(Inter_ref_07_11), |
.Inter_ref_08_11(Inter_ref_08_11), |
.Inter_ref_09_11(Inter_ref_09_11), |
.Inter_ref_10_11(Inter_ref_10_11), |
.Inter_ref_11_11(Inter_ref_11_11), |
.Inter_ref_12_11(Inter_ref_12_11), |
.Inter_ref_00_12(Inter_ref_00_12), |
.Inter_ref_01_12(Inter_ref_01_12), |
.Inter_ref_02_12(Inter_ref_02_12), |
.Inter_ref_03_12(Inter_ref_03_12), |
.Inter_ref_04_12(Inter_ref_04_12), |
.Inter_ref_05_12(Inter_ref_05_12), |
.Inter_ref_06_12(Inter_ref_06_12), |
.Inter_ref_07_12(Inter_ref_07_12), |
.Inter_ref_08_12(Inter_ref_08_12), |
.Inter_ref_09_12(Inter_ref_09_12), |
.Inter_ref_10_12(Inter_ref_10_12), |
.Inter_ref_11_12(Inter_ref_11_12), |
.Inter_ref_12_12(Inter_ref_12_12), |
|
.Inter_pix_copy0(Inter_pix_copy0), |
.Inter_pix_copy1(Inter_pix_copy1), |
.Inter_pix_copy2(Inter_pix_copy2), |
.Inter_pix_copy3(Inter_pix_copy3), |
.Inter_H_window_0_0(Inter_H_window_0_0), |
.Inter_H_window_1_0(Inter_H_window_1_0), |
.Inter_H_window_2_0(Inter_H_window_2_0), |
.Inter_H_window_3_0(Inter_H_window_3_0), |
.Inter_H_window_4_0(Inter_H_window_4_0), |
.Inter_H_window_5_0(Inter_H_window_5_0), |
.Inter_H_window_0_1(Inter_H_window_0_1), |
.Inter_H_window_1_1(Inter_H_window_1_1), |
.Inter_H_window_2_1(Inter_H_window_2_1), |
.Inter_H_window_3_1(Inter_H_window_3_1), |
.Inter_H_window_4_1(Inter_H_window_4_1), |
.Inter_H_window_5_1(Inter_H_window_5_1), |
.Inter_H_window_0_2(Inter_H_window_0_2), |
.Inter_H_window_1_2(Inter_H_window_1_2), |
.Inter_H_window_2_2(Inter_H_window_2_2), |
.Inter_H_window_3_2(Inter_H_window_3_2), |
.Inter_H_window_4_2(Inter_H_window_4_2), |
.Inter_H_window_5_2(Inter_H_window_5_2), |
.Inter_H_window_0_3(Inter_H_window_0_3), |
.Inter_H_window_1_3(Inter_H_window_1_3), |
.Inter_H_window_2_3(Inter_H_window_2_3), |
.Inter_H_window_3_3(Inter_H_window_3_3), |
.Inter_H_window_4_3(Inter_H_window_4_3), |
.Inter_H_window_5_3(Inter_H_window_5_3), |
.Inter_H_window_0_4(Inter_H_window_0_4), |
.Inter_H_window_1_4(Inter_H_window_1_4), |
.Inter_H_window_2_4(Inter_H_window_2_4), |
.Inter_H_window_3_4(Inter_H_window_3_4), |
.Inter_H_window_4_4(Inter_H_window_4_4), |
.Inter_H_window_5_4(Inter_H_window_5_4), |
.Inter_H_window_0_5(Inter_H_window_0_5), |
.Inter_H_window_1_5(Inter_H_window_1_5), |
.Inter_H_window_2_5(Inter_H_window_2_5), |
.Inter_H_window_3_5(Inter_H_window_3_5), |
.Inter_H_window_4_5(Inter_H_window_4_5), |
.Inter_H_window_5_5(Inter_H_window_5_5), |
.Inter_H_window_0_6(Inter_H_window_0_6), |
.Inter_H_window_1_6(Inter_H_window_1_6), |
.Inter_H_window_2_6(Inter_H_window_2_6), |
.Inter_H_window_3_6(Inter_H_window_3_6), |
.Inter_H_window_4_6(Inter_H_window_4_6), |
.Inter_H_window_5_6(Inter_H_window_5_6), |
.Inter_H_window_0_7(Inter_H_window_0_7), |
.Inter_H_window_1_7(Inter_H_window_1_7), |
.Inter_H_window_2_7(Inter_H_window_2_7), |
.Inter_H_window_3_7(Inter_H_window_3_7), |
.Inter_H_window_4_7(Inter_H_window_4_7), |
.Inter_H_window_5_7(Inter_H_window_5_7), |
.Inter_H_window_0_8(Inter_H_window_0_8), |
.Inter_H_window_1_8(Inter_H_window_1_8), |
.Inter_H_window_2_8(Inter_H_window_2_8), |
.Inter_H_window_3_8(Inter_H_window_3_8), |
.Inter_H_window_4_8(Inter_H_window_4_8), |
.Inter_H_window_5_8(Inter_H_window_5_8), |
.Inter_V_window_0(Inter_V_window_0), |
.Inter_V_window_1(Inter_V_window_1), |
.Inter_V_window_2(Inter_V_window_2), |
.Inter_V_window_3(Inter_V_window_3), |
.Inter_V_window_4(Inter_V_window_4), |
.Inter_V_window_5(Inter_V_window_5), |
.Inter_V_window_6(Inter_V_window_6), |
.Inter_V_window_7(Inter_V_window_7), |
.Inter_V_window_8(Inter_V_window_8), |
.Inter_C_window_0_0(Inter_C_window_0_0), |
.Inter_C_window_1_0(Inter_C_window_1_0), |
.Inter_C_window_2_0(Inter_C_window_2_0), |
.Inter_C_window_0_1(Inter_C_window_0_1), |
.Inter_C_window_1_1(Inter_C_window_1_1), |
.Inter_C_window_2_1(Inter_C_window_2_1), |
.Inter_C_window_0_2(Inter_C_window_0_2), |
.Inter_C_window_1_2(Inter_C_window_1_2), |
.Inter_C_window_2_2(Inter_C_window_2_2), |
.Inter_bi_window_0(Inter_bi_window_0), |
.Inter_bi_window_1(Inter_bi_window_1), |
.Inter_bi_window_2(Inter_bi_window_2), |
.Inter_bi_window_3(Inter_bi_window_3) |
); |
|
Inter_pred_LPE Inter_pred_LPE ( |
.clk(clk), |
.reset_n(reset_n), |
.pos_FracL(pos_FracL), |
.IsInterLuma(IsInterLuma), |
.blk4x4_inter_calculate_counter(blk4x4_inter_calculate_counter), |
.Inter_H_window_0_0(Inter_H_window_0_0), |
.Inter_H_window_1_0(Inter_H_window_1_0), |
.Inter_H_window_2_0(Inter_H_window_2_0), |
.Inter_H_window_3_0(Inter_H_window_3_0), |
.Inter_H_window_4_0(Inter_H_window_4_0), |
.Inter_H_window_5_0(Inter_H_window_5_0), |
.Inter_H_window_0_1(Inter_H_window_0_1), |
.Inter_H_window_1_1(Inter_H_window_1_1), |
.Inter_H_window_2_1(Inter_H_window_2_1), |
.Inter_H_window_3_1(Inter_H_window_3_1), |
.Inter_H_window_4_1(Inter_H_window_4_1), |
.Inter_H_window_5_1(Inter_H_window_5_1), |
.Inter_H_window_0_2(Inter_H_window_0_2), |
.Inter_H_window_1_2(Inter_H_window_1_2), |
.Inter_H_window_2_2(Inter_H_window_2_2), |
.Inter_H_window_3_2(Inter_H_window_3_2), |
.Inter_H_window_4_2(Inter_H_window_4_2), |
.Inter_H_window_5_2(Inter_H_window_5_2), |
.Inter_H_window_0_3(Inter_H_window_0_3), |
.Inter_H_window_1_3(Inter_H_window_1_3), |
.Inter_H_window_2_3(Inter_H_window_2_3), |
.Inter_H_window_3_3(Inter_H_window_3_3), |
.Inter_H_window_4_3(Inter_H_window_4_3), |
.Inter_H_window_5_3(Inter_H_window_5_3), |
.Inter_H_window_0_4(Inter_H_window_0_4), |
.Inter_H_window_1_4(Inter_H_window_1_4), |
.Inter_H_window_2_4(Inter_H_window_2_4), |
.Inter_H_window_3_4(Inter_H_window_3_4), |
.Inter_H_window_4_4(Inter_H_window_4_4), |
.Inter_H_window_5_4(Inter_H_window_5_4), |
.Inter_H_window_0_5(Inter_H_window_0_5), |
.Inter_H_window_1_5(Inter_H_window_1_5), |
.Inter_H_window_2_5(Inter_H_window_2_5), |
.Inter_H_window_3_5(Inter_H_window_3_5), |
.Inter_H_window_4_5(Inter_H_window_4_5), |
.Inter_H_window_5_5(Inter_H_window_5_5), |
.Inter_H_window_0_6(Inter_H_window_0_6), |
.Inter_H_window_1_6(Inter_H_window_1_6), |
.Inter_H_window_2_6(Inter_H_window_2_6), |
.Inter_H_window_3_6(Inter_H_window_3_6), |
.Inter_H_window_4_6(Inter_H_window_4_6), |
.Inter_H_window_5_6(Inter_H_window_5_6), |
.Inter_H_window_0_7(Inter_H_window_0_7), |
.Inter_H_window_1_7(Inter_H_window_1_7), |
.Inter_H_window_2_7(Inter_H_window_2_7), |
.Inter_H_window_3_7(Inter_H_window_3_7), |
.Inter_H_window_4_7(Inter_H_window_4_7), |
.Inter_H_window_5_7(Inter_H_window_5_7), |
.Inter_H_window_0_8(Inter_H_window_0_8), |
.Inter_H_window_1_8(Inter_H_window_1_8), |
.Inter_H_window_2_8(Inter_H_window_2_8), |
.Inter_H_window_3_8(Inter_H_window_3_8), |
.Inter_H_window_4_8(Inter_H_window_4_8), |
.Inter_H_window_5_8(Inter_H_window_5_8), |
.Inter_V_window_0(Inter_V_window_0), |
.Inter_V_window_1(Inter_V_window_1), |
.Inter_V_window_2(Inter_V_window_2), |
.Inter_V_window_3(Inter_V_window_3), |
.Inter_V_window_4(Inter_V_window_4), |
.Inter_V_window_5(Inter_V_window_5), |
.Inter_V_window_6(Inter_V_window_6), |
.Inter_V_window_7(Inter_V_window_7), |
.Inter_V_window_8(Inter_V_window_8), |
.Inter_bi_window_0(Inter_bi_window_0), |
.Inter_bi_window_1(Inter_bi_window_1), |
.Inter_bi_window_2(Inter_bi_window_2), |
.Inter_bi_window_3(Inter_bi_window_3), |
|
.LPE0_out(LPE0_out), |
.LPE1_out(LPE1_out), |
.LPE2_out(LPE2_out), |
.LPE3_out(LPE3_out) |
); |
Inter_pred_CPE Inter_pred_CPE ( |
.xFracC(xFracC), |
.yFracC(yFracC), |
.Inter_C_window_0_0(Inter_C_window_0_0), |
.Inter_C_window_1_0(Inter_C_window_1_0), |
.Inter_C_window_2_0(Inter_C_window_2_0), |
.Inter_C_window_0_1(Inter_C_window_0_1), |
.Inter_C_window_1_1(Inter_C_window_1_1), |
.Inter_C_window_2_1(Inter_C_window_2_1), |
.Inter_C_window_0_2(Inter_C_window_0_2), |
.Inter_C_window_1_2(Inter_C_window_1_2), |
.Inter_C_window_2_2(Inter_C_window_2_2), |
.CPE0_out(CPE0_out), |
.CPE1_out(CPE1_out), |
.CPE2_out(CPE2_out), |
.CPE3_out(CPE3_out) |
); |
endmodule |
|
/trunk/src/DF_pipeline.v
0,0 → 1,861
//----------------------------------------------------------------------- |
// Design : nova |
// Author(s) : Ke Xu |
// Email : eexuke@yahoo.com |
// File : DF_pipeline.v |
// Generated : Dec 2, 2005 |
// Copyright (C) 2008 Ke Xu |
//------------------------------------------------------------------------------------------------- |
// Description |
// 5-stage pipeline control for deblocking filter |
//------------------------------------------------------------------------------------------------- |
|
// synopsys translate_off |
`include "timescale.v" |
// synopsys translate_on |
`include "nova_defines.v" |
|
module DF_pipeline (clk,gclk_DF,gclk_end_of_MB_DEC,reset_n,disable_DF,end_of_BS_DEC, |
end_of_MB_DF,end_of_lastMB_DF, |
bs_V0,bs_V1,bs_V2,bs_V3,bs_H0,bs_H1,bs_H2,bs_H3, |
QPy,QPc,slice_alpha_c0_offset_div2,slice_beta_offset_div2, |
DF_mbAddrA_RF_dout,DF_mbAddrB_RAM_dout,rec_DF_RAM_dout, |
buf0_0,buf0_1,buf0_2,buf0_3,buf1_0,buf1_1,buf1_2,buf1_3, |
buf2_0,buf2_1,buf2_2,buf2_3,buf3_0,buf3_1,buf3_2,buf3_3, |
|
DF_duration, |
DF_edge_counter_MR,DF_edge_counter_MW, |
one_edge_counter_MR,one_edge_counter_MW, |
bs_curr_MR,bs_curr_MW, |
p0_MW,p1_MW,p2_MW,p3_MW,q0_MW,q1_MW,q2_MW,q3_MW); |
input clk; |
input gclk_DF; |
input gclk_end_of_MB_DEC; |
input reset_n; |
input disable_DF; |
input end_of_BS_DEC; |
input end_of_MB_DF; |
input end_of_lastMB_DF; |
input [11:0] bs_V0,bs_V1,bs_V2,bs_V3; |
input [11:0] bs_H0,bs_H1,bs_H2,bs_H3; |
input [5:0] QPy,QPc; |
input [3:0] slice_alpha_c0_offset_div2,slice_beta_offset_div2; |
input [31:0] DF_mbAddrA_RF_dout,DF_mbAddrB_RAM_dout,rec_DF_RAM_dout; |
input [31:0] buf0_0,buf0_1,buf0_2,buf0_3,buf1_0,buf1_1,buf1_2,buf1_3; |
input [31:0] buf2_0,buf2_1,buf2_2,buf2_3,buf3_0,buf3_1,buf3_2,buf3_3; |
|
output DF_duration; |
output [5:0] DF_edge_counter_MR,DF_edge_counter_MW; |
output [1:0] one_edge_counter_MR,one_edge_counter_MW; |
output [2:0] bs_curr_MR; |
output [2:0] bs_curr_MW; |
output [7:0] p0_MW,p1_MW,p2_MW,p3_MW; |
output [7:0] q0_MW,q1_MW,q2_MW,q3_MW; |
|
reg DF_duration; |
always @ (posedge clk or negedge reset_n) |
if (reset_n == 1'b0) |
DF_duration <= 1'b0; |
else if (end_of_BS_DEC) |
DF_duration <= 1'b1; |
else if (end_of_MB_DF || end_of_lastMB_DF) |
DF_duration <= 1'b0; |
|
//--------------------------------------------------------------------- |
//1.MR: Memory Read |
//--------------------------------------------------------------------- |
//DF_edge_counter_MR & one_edge_counter_MR |
reg [5:0] DF_edge_counter_MR; |
reg [1:0] one_edge_counter_MR; |
always @ (posedge gclk_DF or negedge reset_n) |
if (reset_n == 1'b0) |
DF_edge_counter_MR <= 6'd48; |
else if (end_of_BS_DEC == 1'b1) |
DF_edge_counter_MR <= 0; |
else if (one_edge_counter_MR == 2'd3 && DF_edge_counter_MR != 6'd48) |
DF_edge_counter_MR <= DF_edge_counter_MR + 1; |
|
always @ (posedge gclk_DF or negedge reset_n) |
if (reset_n == 0) |
one_edge_counter_MR <= 2'd3; |
else if (end_of_BS_DEC == 1'b1) |
one_edge_counter_MR <= 2'd0; |
else |
begin |
if (one_edge_counter_MR == 2'd3 && DF_edge_counter_MR != 6'd47 && DF_edge_counter_MR[5:4] != 2'b11) //!47,!48 |
one_edge_counter_MR <= 2'd0; |
else if (one_edge_counter_MR != 2'd3) |
one_edge_counter_MR <= one_edge_counter_MR + 1; |
end |
|
//lumaEdgeFlag_MR,chromaEdgeFlag_MR |
wire lumaEdgeFlag_MR,chromaEdgeFlag_MR; |
assign lumaEdgeFlag_MR = !DF_edge_counter_MR[5]; |
assign chromaEdgeFlag_MR = DF_edge_counter_MR[5] && (DF_edge_counter_MR != 6'd48); |
|
//bs_curr_MR |
reg [2:0] bs_curr_MR; |
always @ (disable_DF or lumaEdgeFlag_MR or chromaEdgeFlag_MR or |
DF_edge_counter_MR[4:0] or one_edge_counter_MR[1] or |
bs_V0 or bs_V1 or bs_V2 or bs_V3 or bs_H0 or bs_H1 or bs_H2 or bs_H3) |
if (!disable_DF && lumaEdgeFlag_MR) |
case (DF_edge_counter_MR[4:0]) |
5'd0 :bs_curr_MR <= bs_V0[2:0]; |
5'd1 :bs_curr_MR <= bs_V1[2:0]; |
5'd2 :bs_curr_MR <= bs_V0[5:3]; |
5'd3 :bs_curr_MR <= bs_V1[5:3]; |
5'd4 :bs_curr_MR <= bs_H0[2:0]; |
5'd5 :bs_curr_MR <= bs_H1[2:0]; |
5'd6 :bs_curr_MR <= bs_V2[2:0]; |
5'd7 :bs_curr_MR <= bs_V2[5:3]; |
5'd8 :bs_curr_MR <= bs_H0[5:3]; |
5'd9 :bs_curr_MR <= bs_H1[5:3]; |
5'd10:bs_curr_MR <= bs_V3[2:0]; |
5'd11:bs_curr_MR <= bs_V3[5:3]; |
5'd12:bs_curr_MR <= bs_H0[8:6]; |
5'd13:bs_curr_MR <= bs_H0[11:9]; |
5'd14:bs_curr_MR <= bs_H1[8:6]; |
5'd15:bs_curr_MR <= bs_H1[11:9]; |
5'd16:bs_curr_MR <= bs_V0[8:6]; |
5'd17:bs_curr_MR <= bs_V1[8:6]; |
5'd18:bs_curr_MR <= bs_V0[11:9]; |
5'd19:bs_curr_MR <= bs_V1[11:9]; |
5'd20:bs_curr_MR <= bs_H2[2:0]; |
5'd21:bs_curr_MR <= bs_H3[2:0]; |
5'd22:bs_curr_MR <= bs_V2[8:6]; |
5'd23:bs_curr_MR <= bs_V2[11:9]; |
5'd24:bs_curr_MR <= bs_H2[5:3]; |
5'd25:bs_curr_MR <= bs_H3[5:3]; |
5'd26:bs_curr_MR <= bs_V3[8:6]; |
5'd27:bs_curr_MR <= bs_V3[11:9]; |
5'd28:bs_curr_MR <= bs_H2[8:6]; |
5'd29:bs_curr_MR <= bs_H2[11:9]; |
5'd30:bs_curr_MR <= bs_H3[8:6]; |
5'd31:bs_curr_MR <= bs_H3[11:9]; |
endcase |
else if (!disable_DF && chromaEdgeFlag_MR) |
case (DF_edge_counter_MR[3:0]) |
4'd0,4'd8: //32,40 |
case (one_edge_counter_MR[1]) |
1'b0:bs_curr_MR <= bs_V0[2:0]; |
1'b1:bs_curr_MR <= bs_V0[5:3]; |
endcase |
4'd2,4'd10: //34,42 |
case (one_edge_counter_MR[1]) |
1'b0:bs_curr_MR <= bs_V0[8:6]; |
1'b1:bs_curr_MR <= bs_V0[11:9]; |
endcase |
4'd1,4'd9: //33,41 |
case (one_edge_counter_MR[1]) |
1'b0:bs_curr_MR <= bs_V2[2:0]; |
1'b1:bs_curr_MR <= bs_V2[5:3]; |
endcase |
4'd3,4'd11: //35,43 |
case (one_edge_counter_MR[1]) |
1'b0:bs_curr_MR <= bs_V2[8:6]; |
1'b1:bs_curr_MR <= bs_V2[11:9]; |
endcase |
4'd4,4'd12: //36,44 |
case (one_edge_counter_MR[1]) |
1'b0:bs_curr_MR <= bs_H0[2:0]; |
1'b1:bs_curr_MR <= bs_H0[5:3]; |
endcase |
4'd5,4'd13: //37,45 |
case (one_edge_counter_MR[1]) |
1'b0:bs_curr_MR <= bs_H0[8:6]; |
1'b1:bs_curr_MR <= bs_H0[11:9]; |
endcase |
4'd6,4'd14: //38,46 |
case (one_edge_counter_MR[1]) |
1'b0:bs_curr_MR <= bs_H2[2:0]; |
1'b1:bs_curr_MR <= bs_H2[5:3]; |
endcase |
4'd7,4'd15: //39,47 |
case (one_edge_counter_MR[1]) |
1'b0:bs_curr_MR <= bs_H2[8:6]; |
1'b1:bs_curr_MR <= bs_H2[11:9]; |
endcase |
endcase |
else |
bs_curr_MR <= 0; |
|
// Pipelined parameters |
reg [2:0] bs_curr_TD; |
reg lumaEdgeFlag_TD,chromaEdgeFlag_TD; |
reg [5:0] DF_edge_counter_TD; |
reg [1:0] one_edge_counter_TD; |
always @ (posedge gclk_DF or negedge reset_n) |
if (reset_n == 1'b0) |
begin |
bs_curr_TD <= 0; |
lumaEdgeFlag_TD <= 0; |
chromaEdgeFlag_TD <= 0; |
DF_edge_counter_TD <= 6'd48; |
one_edge_counter_TD <= 2'd3; |
end |
else |
begin |
bs_curr_TD <= bs_curr_MR; |
lumaEdgeFlag_TD <= lumaEdgeFlag_MR; |
chromaEdgeFlag_TD <= chromaEdgeFlag_MR; |
DF_edge_counter_TD <= DF_edge_counter_MR; |
one_edge_counter_TD <= one_edge_counter_MR; |
end |
//--------------------------------------------------------------------- |
//2.TD: Threshold Decider |
//--------------------------------------------------------------------- |
wire [6:0] indexA_y_unclipped,indexA_c_unclipped; |
wire [6:0] indexB_y_unclipped,indexB_c_unclipped; |
assign indexA_y_unclipped = QPy + {{2{slice_alpha_c0_offset_div2[3]}},slice_alpha_c0_offset_div2,1'b0}; |
assign indexA_c_unclipped = QPc + {{2{slice_alpha_c0_offset_div2[3]}},slice_alpha_c0_offset_div2,1'b0}; |
assign indexB_y_unclipped = QPy + {{2{slice_beta_offset_div2[3]}},slice_beta_offset_div2,1'b0}; |
assign indexB_c_unclipped = QPc + {{2{slice_beta_offset_div2[3]}},slice_beta_offset_div2,1'b0}; |
|
wire [5:0] indexA_y,indexA_c; |
wire [5:0] indexB_y,indexB_c; |
assign indexA_y = (indexA_y_unclipped[6] == 1)? 0:((indexA_y_unclipped[5:0] > 6'd51)? 6'd51:indexA_y_unclipped[5:0]); |
assign indexA_c = (indexA_c_unclipped[6] == 1)? 0:((indexA_c_unclipped[5:0] > 6'd51)? 6'd51:indexA_c_unclipped[5:0]); |
assign indexB_y = (indexB_y_unclipped[6] == 1)? 0:((indexB_y_unclipped[5:0] > 6'd51)? 6'd51:indexB_y_unclipped[5:0]); |
assign indexB_c = (indexB_c_unclipped[6] == 1)? 0:((indexB_c_unclipped[5:0] > 6'd51)? 6'd51:indexB_c_unclipped[5:0]); |
|
reg [5:0] indexA_y_reg,indexA_c_reg; |
reg [5:0] indexB_y_reg,indexB_c_reg; |
always @ (posedge gclk_end_of_MB_DEC or negedge reset_n) |
if (reset_n == 1'b0) |
begin indexA_y_reg <= 0; indexA_c_reg <= 0; indexB_y_reg <= 0; indexB_c_reg <= 0; end |
else if (!disable_DF) |
begin |
indexA_y_reg <= indexA_y; indexA_c_reg <= indexA_c; |
indexB_y_reg <= indexB_y; indexB_c_reg <= indexB_c; |
end |
|
wire [5:0] indexA,indexB; |
assign indexA = (lumaEdgeFlag_TD)? indexA_y_reg:((chromaEdgeFlag_TD)? indexA_c_reg:0); |
assign indexB = (lumaEdgeFlag_TD)? indexB_y_reg:((chromaEdgeFlag_TD)? indexB_c_reg:0); |
|
reg [7:0] alpha,beta; |
//alpha |
always @ (indexA) |
if (indexA < 16) |
alpha <= 0; |
else |
case (indexA) |
6'd16,6'd17:alpha <= 8'd4; |
6'd18:alpha <= 8'd5; 6'd19:alpha <= 8'd6; 6'd20:alpha <= 8'd7; 6'd21:alpha <= 8'd8; |
6'd22:alpha <= 8'd9; 6'd23:alpha <= 8'd10; 6'd24:alpha <= 8'd12; 6'd25:alpha <= 8'd13; |
6'd26:alpha <= 8'd15; 6'd27:alpha <= 8'd17; 6'd28:alpha <= 8'd20; 6'd29:alpha <= 8'd22; |
6'd30:alpha <= 8'd25; 6'd31:alpha <= 8'd28; 6'd32:alpha <= 8'd32; 6'd33:alpha <= 8'd36; |
6'd34:alpha <= 8'd40; 6'd35:alpha <= 8'd45; 6'd36:alpha <= 8'd50; 6'd37:alpha <= 8'd56; |
6'd38:alpha <= 8'd63; 6'd39:alpha <= 8'd71; 6'd40:alpha <= 8'd80; 6'd41:alpha <= 8'd90; |
6'd42:alpha <= 8'd101; 6'd43:alpha <= 8'd113; 6'd44:alpha <= 8'd127; 6'd45:alpha <= 8'd144; |
6'd46:alpha <= 8'd162; 6'd47:alpha <= 8'd182; 6'd48:alpha <= 8'd203; 6'd49:alpha <= 8'd226; |
default:alpha <= 8'd255; |
endcase |
//beta |
always @ (indexB) |
if (indexB < 16) |
beta <= 0; |
else if (indexB > 15 && indexB < 26) |
case (indexB) |
6'd16,6'd17,6'd18 :beta <= 8'd2; |
6'd19,6'd20,6'd21,6'd22 :beta <= 8'd3; |
6'd23,6'd24,6'd25 :beta <= 8'd4; |
default:beta <= 0; |
endcase |
else |
beta <= indexB[5:1] - 3'd7; |
|
wire [7:0] absolute_TD0_a,absolute_TD0_b; |
wire [7:0] absolute_TD1_a,absolute_TD1_b; |
wire [7:0] absolute_TD2_a,absolute_TD2_b; |
wire [7:0] absolute_TD0_out,absolute_TD1_out,absolute_TD2_out; |
absolute absolute_TD0 (.a(absolute_TD0_a),.b(absolute_TD0_b),.out(absolute_TD0_out)); |
absolute absolute_TD1 (.a(absolute_TD1_a),.b(absolute_TD1_b),.out(absolute_TD1_out)); |
absolute absolute_TD2 (.a(absolute_TD2_a),.b(absolute_TD2_b),.out(absolute_TD2_out)); |
|
//p0 ~ p3 |
wire Is_p_from_mbAddrA; |
wire Is_p_from_mbAddrB; |
wire Is_p_from_buf0; |
wire Is_p_from_buf1; |
wire Is_p_from_buf2; |
wire Is_p_from_buf3; |
assign Is_p_from_mbAddrA = (DF_edge_counter_TD == 6'd0 || DF_edge_counter_TD == 6'd2 || |
DF_edge_counter_TD == 6'd16 || DF_edge_counter_TD == 6'd18 || DF_edge_counter_TD == 6'd32 || |
DF_edge_counter_TD == 6'd34 || DF_edge_counter_TD == 6'd40 || DF_edge_counter_TD == 6'd42); |
|
assign Is_p_from_mbAddrB = (DF_edge_counter_TD == 6'd4 || DF_edge_counter_TD == 6'd8 || |
DF_edge_counter_TD == 6'd12 || DF_edge_counter_TD == 6'd13 || DF_edge_counter_TD == 6'd20 || |
DF_edge_counter_TD == 6'd24 || DF_edge_counter_TD == 6'd28 || DF_edge_counter_TD == 6'd29 || |
DF_edge_counter_TD == 6'd36 || DF_edge_counter_TD == 6'd37 || DF_edge_counter_TD == 6'd44 || |
DF_edge_counter_TD == 6'd45); |
|
assign Is_p_from_buf0 = (DF_edge_counter_TD == 6'd1 || DF_edge_counter_TD == 6'd5 || |
DF_edge_counter_TD == 6'd10 || DF_edge_counter_TD == 6'd14 || DF_edge_counter_TD == 6'd17 || |
DF_edge_counter_TD == 6'd21 || DF_edge_counter_TD == 6'd26 || DF_edge_counter_TD == 6'd30 || |
DF_edge_counter_TD == 6'd33 || DF_edge_counter_TD == 6'd38 || DF_edge_counter_TD == 6'd41 || |
DF_edge_counter_TD == 6'd46); |
|
assign Is_p_from_buf1 = (DF_edge_counter_TD == 6'd6 || DF_edge_counter_TD == 6'd9 || |
DF_edge_counter_TD == 6'd15 || DF_edge_counter_TD == 6'd22 || DF_edge_counter_TD == 6'd25 || |
DF_edge_counter_TD == 6'd31 || DF_edge_counter_TD == 6'd39 || DF_edge_counter_TD == 6'd47); |
|
assign Is_p_from_buf2 = (DF_edge_counter_TD == 6'd3 || DF_edge_counter_TD == 6'd11 || |
DF_edge_counter_TD == 6'd19 || DF_edge_counter_TD == 6'd27 || DF_edge_counter_TD == 6'd35 || |
DF_edge_counter_TD == 6'd43); |
|
assign Is_p_from_buf3 = (DF_edge_counter_TD == 6'd7 || DF_edge_counter_TD == 6'd23); |
|
reg [7:0] p0,p1,p2,p3; |
always @ (Is_p_from_mbAddrA or Is_p_from_mbAddrB or Is_p_from_buf0 or Is_p_from_buf1 or |
Is_p_from_buf2 or Is_p_from_buf3 or one_edge_counter_TD or |
DF_mbAddrA_RF_dout or DF_mbAddrB_RAM_dout or |
buf0_0 or buf0_1 or buf0_2 or buf0_3 or buf1_0 or buf1_1 or buf1_2 or buf1_3 or |
buf2_0 or buf2_1 or buf2_2 or buf2_3 or buf3_0 or buf3_1 or buf3_2 or buf3_3) |
case ({Is_p_from_mbAddrA,Is_p_from_mbAddrB,Is_p_from_buf0,Is_p_from_buf1,Is_p_from_buf2,Is_p_from_buf3}) |
6'b100000:{p0,p1,p2,p3} <= DF_mbAddrA_RF_dout; |
6'b010000:{p0,p1,p2,p3} <= DF_mbAddrB_RAM_dout; |
6'b001000: case (one_edge_counter_TD) |
2'b00:{p0,p1,p2,p3} <= buf0_0; |
2'b01:{p0,p1,p2,p3} <= buf0_1; |
2'b10:{p0,p1,p2,p3} <= buf0_2; |
2'b11:{p0,p1,p2,p3} <= buf0_3; |
endcase |
6'b000100: case (one_edge_counter_TD) |
2'b00:{p0,p1,p2,p3} <= buf1_0; |
2'b01:{p0,p1,p2,p3} <= buf1_1; |
2'b10:{p0,p1,p2,p3} <= buf1_2; |
2'b11:{p0,p1,p2,p3} <= buf1_3; |
endcase |
6'b000010: case (one_edge_counter_TD) |
2'b00:{p0,p1,p2,p3} <= buf2_0; |
2'b01:{p0,p1,p2,p3} <= buf2_1; |
2'b10:{p0,p1,p2,p3} <= buf2_2; |
2'b11:{p0,p1,p2,p3} <= buf2_3; |
endcase |
6'b000001: case (one_edge_counter_TD) |
2'b00:{p0,p1,p2,p3} <= buf3_0; |
2'b01:{p0,p1,p2,p3} <= buf3_1; |
2'b10:{p0,p1,p2,p3} <= buf3_2; |
2'b11:{p0,p1,p2,p3} <= buf3_3; |
endcase |
default:{p0,p1,p2,p3} <= 0; |
endcase |
|
//q0 ~ q3 |
wire Is_q_from_buf0; |
wire Is_q_from_buf1; |
wire Is_q_from_buf2; |
wire Is_q_from_buf3; |
|
assign Is_q_from_buf0 = (DF_edge_counter_TD == 6'd4 || DF_edge_counter_TD == 6'd12 || |
DF_edge_counter_TD == 6'd20 || DF_edge_counter_TD == 6'd28 || DF_edge_counter_TD == 6'd36 || |
DF_edge_counter_TD == 6'd44); |
|
assign Is_q_from_buf1 = (DF_edge_counter_TD == 6'd8 || DF_edge_counter_TD == 6'd13 || |
DF_edge_counter_TD == 6'd24 || DF_edge_counter_TD == 6'd29 || DF_edge_counter_TD == 6'd37 || |
DF_edge_counter_TD == 6'd45); |
|
assign Is_q_from_buf2 = (DF_edge_counter_TD == 6'd5 || DF_edge_counter_TD == 6'd14 || |
DF_edge_counter_TD == 6'd21 || DF_edge_counter_TD == 6'd30 || DF_edge_counter_TD == 6'd38 || |
DF_edge_counter_TD == 6'd46); |
|
assign Is_q_from_buf3 = (DF_edge_counter_TD == 6'd9 || DF_edge_counter_TD == 6'd15 || |
DF_edge_counter_TD == 6'd25 || DF_edge_counter_TD == 6'd31 || DF_edge_counter_TD == 6'd39 || |
DF_edge_counter_TD == 6'd47); |
|
reg [7:0] q0,q1,q2,q3; |
always @ (Is_q_from_buf0 or Is_q_from_buf1 or Is_q_from_buf2 or Is_q_from_buf3 or |
rec_DF_RAM_dout or one_edge_counter_TD or DF_edge_counter_TD or |
buf0_0 or buf0_1 or buf0_2 or buf0_3 or buf1_0 or buf1_1 or buf1_2 or buf1_3 or |
buf2_0 or buf2_1 or buf2_2 or buf2_3 or buf3_0 or buf3_1 or buf3_2 or buf3_3) |
case ({Is_q_from_buf0,Is_q_from_buf1,Is_q_from_buf2,Is_q_from_buf3}) |
4'b1000:case (one_edge_counter_TD) |
2'b00:{q3,q2,q1,q0} <= buf0_0; |
2'b01:{q3,q2,q1,q0} <= buf0_1; |
2'b10:{q3,q2,q1,q0} <= buf0_2; |
2'b11:{q3,q2,q1,q0} <= buf0_3; |
endcase |
4'b0100:case (one_edge_counter_TD) |
2'b00:{q3,q2,q1,q0} <= buf1_0; |
2'b01:{q3,q2,q1,q0} <= buf1_1; |
2'b10:{q3,q2,q1,q0} <= buf1_2; |
2'b11:{q3,q2,q1,q0} <= buf1_3; |
endcase |
4'b0010:case (one_edge_counter_TD) |
2'b00:{q3,q2,q1,q0} <= buf2_0; |
2'b01:{q3,q2,q1,q0} <= buf2_1; |
2'b10:{q3,q2,q1,q0} <= buf2_2; |
2'b11:{q3,q2,q1,q0} <= buf2_3; |
endcase |
4'b0001:case (one_edge_counter_TD) |
2'b00:{q3,q2,q1,q0} <= buf3_0; |
2'b01:{q3,q2,q1,q0} <= buf3_1; |
2'b10:{q3,q2,q1,q0} <= buf3_2; |
2'b11:{q3,q2,q1,q0} <= buf3_3; |
endcase |
default:if (DF_edge_counter_TD != 6'd48) {q3,q2,q1,q0} <= rec_DF_RAM_dout; |
else {q3,q2,q1,q0} <= 0; |
endcase |
|
// |p0 - q0| < alpha |
assign absolute_TD0_a = (!disable_DF && bs_curr_TD != 0)? p0:0; |
assign absolute_TD0_b = (!disable_DF && bs_curr_TD != 0)? q0:0; |
|
// |p1 - p0| < beta |
assign absolute_TD1_a = (!disable_DF && bs_curr_TD != 0)? p0:0; |
assign absolute_TD1_b = (!disable_DF && bs_curr_TD != 0)? p1:0; |
|
// |q1 - q0| < beta |
assign absolute_TD2_a = (!disable_DF && bs_curr_TD != 0)? q0:0; |
assign absolute_TD2_b = (!disable_DF && bs_curr_TD != 0)? q1:0; |
|
// Threshold |
wire threshold; |
assign threshold = ((absolute_TD0_out < alpha) && (absolute_TD1_out < beta) && |
(absolute_TD2_out < beta))? 1'b1:1'b0; |
|
// Pipelined parameters |
reg [2:0] bs_curr_PRE; |
reg [5:0] DF_edge_counter_PRE; |
reg [1:0] one_edge_counter_PRE; |
reg lumaEdgeFlag_PRE,chromaEdgeFlag_PRE; |
reg [7:0] p0_PRE,p1_PRE,p2_PRE,p3_PRE; |
reg [7:0] q0_PRE,q1_PRE,q2_PRE,q3_PRE; |
reg [5:0] indexA_PRE; |
reg [7:0] alpha_PRE,beta_PRE; |
always @ (posedge gclk_DF or negedge reset_n) |
if (reset_n == 1'b0) |
begin |
bs_curr_PRE <= 0; |
DF_edge_counter_PRE <= 6'd48; |
one_edge_counter_PRE <= 2'd3; |
lumaEdgeFlag_PRE <= 0; |
chromaEdgeFlag_PRE <= 0; |
indexA_PRE <= 0; |
alpha_PRE <= 0; |
beta_PRE <= 0; |
p0_PRE <= 0; p1_PRE <= 0; p2_PRE <= 0; p3_PRE <= 0; |
q0_PRE <= 0; q1_PRE <= 0; q2_PRE <= 0; q3_PRE <= 0; |
end |
else |
begin |
bs_curr_PRE <= (threshold)? bs_curr_TD:0; |
DF_edge_counter_PRE <= DF_edge_counter_TD; |
one_edge_counter_PRE<= one_edge_counter_TD; |
lumaEdgeFlag_PRE <= (threshold)? lumaEdgeFlag_TD:0; |
chromaEdgeFlag_PRE <= (threshold)? chromaEdgeFlag_TD:0; |
indexA_PRE <= (threshold)? indexA:0; |
alpha_PRE <= (threshold)? alpha:0; |
beta_PRE <= (threshold)? beta:0; |
p0_PRE <= p0; p1_PRE <= p1; p2_PRE <= p2; p3_PRE <= p3; |
q0_PRE <= q0; q1_PRE <= q1; q2_PRE <= q2; q3_PRE <= q3; |
end |
//--------------------------------------------------------------------- |
//3.PRE: Precomputation |
//--------------------------------------------------------------------- |
wire [7:0] absolute_PRE0_a,absolute_PRE0_b; |
wire [7:0] absolute_PRE1_a,absolute_PRE1_b; |
wire [7:0] absolute_PRE2_a,absolute_PRE2_b; |
wire [7:0] absolute_PRE0_out,absolute_PRE1_out,absolute_PRE2_out; |
|
absolute absolute_PRE0 (.a(absolute_PRE0_a),.b(absolute_PRE0_b),.out(absolute_PRE0_out)); |
absolute absolute_PRE1 (.a(absolute_PRE1_a),.b(absolute_PRE1_b),.out(absolute_PRE1_out)); |
absolute absolute_PRE2 (.a(absolute_PRE2_a),.b(absolute_PRE2_b),.out(absolute_PRE2_out)); |
|
// |p2 - p0| < beta |
assign absolute_PRE0_a = (bs_curr_PRE != 0 && lumaEdgeFlag_PRE)? p2_PRE:0; |
assign absolute_PRE0_b = (bs_curr_PRE != 0 && lumaEdgeFlag_PRE)? p0_PRE:0; |
|
// |q2 - q0| < beta |
assign absolute_PRE1_a = (bs_curr_PRE != 0 && lumaEdgeFlag_PRE)? q2_PRE:0; |
assign absolute_PRE1_b = (bs_curr_PRE != 0 && lumaEdgeFlag_PRE)? q0_PRE:0; |
|
// |p0 - q0| < alpha >> 2 + 2 |
assign absolute_PRE2_a = (lumaEdgeFlag_PRE && bs_curr_PRE == 3'd4)? p0_PRE:0; |
assign absolute_PRE2_b = (lumaEdgeFlag_PRE && bs_curr_PRE == 3'd4)? q0_PRE:0; |
|
wire p2_m_p0_less_beta,q2_m_q0_less_beta,p0_m_q0_less_alpha_shift; |
assign p2_m_p0_less_beta = (bs_curr_PRE == 0 || !lumaEdgeFlag_PRE)? 1'b0: |
((absolute_PRE0_out < beta_PRE)? 1'b1:1'b0); |
assign q2_m_q0_less_beta = (bs_curr_PRE == 0 || !lumaEdgeFlag_PRE)? 1'b0: |
((absolute_PRE1_out < beta_PRE)? 1'b1:1'b0); |
assign p0_m_q0_less_alpha_shift = (!lumaEdgeFlag_PRE || bs_curr_PRE != 4)? 1'b0: |
((absolute_PRE2_out < ((alpha_PRE >> 2) + 2))? 1'b1:1'b0); |
// bs = 1 ~ 3 |
reg [4:0] c1; |
always @ (bs_curr_PRE or indexA_PRE) |
if (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4) |
case (bs_curr_PRE) |
3'd1: |
if (indexA_PRE < 23) c1 <= 5'd0; |
else if (indexA_PRE < 33) c1 <= 5'd1; |
else if (indexA_PRE < 37) c1 <= 5'd2; |
else if (indexA_PRE < 40) c1 <= 5'd3; |
else if (indexA_PRE < 43) c1 <= 5'd4; |
else |
case (indexA_PRE) |
6'd43:c1 <= 5'd5; 6'd44,6'd45:c1 <= 5'd6; |
6'd46:c1 <= 5'd7; 6'd47:c1 <= 5'd8; 6'd48:c1 <= 5'd9; |
6'd49:c1 <= 5'd10; 6'd50:c1 <= 5'd11; 6'd51:c1 <= 5'd13; |
default:c1 <= 0; |
endcase |
3'd2: |
if (indexA_PRE < 21) c1 <= 5'd0; |
else if (indexA_PRE < 31) c1 <= 5'd1; |
else if (indexA_PRE < 35) c1 <= 5'd2; |
else if (indexA_PRE < 38) c1 <= 5'd3; |
else |
case (indexA_PRE) |
6'd38,6'd39:c1 <= 5'd4; |
6'd40,6'd41:c1 <= 5'd5; |
6'd42:c1 <= 5'd6; 6'd43:c1 <= 5'd7; 6'd44,6'd45:c1 <= 5'd8; |
6'd46:c1 <= 5'd10; 6'd47:c1 <= 5'd11; 6'd48:c1 <= 5'd12; |
6'd49:c1 <= 5'd13; 6'd50:c1 <= 5'd15; 6'd51:c1 <= 5'd17; |
default:c1 <= 5'd0; |
endcase |
3'd3: |
if (indexA_PRE < 17) c1 <= 5'd0; |
else if (indexA_PRE < 27) c1 <= 5'd1; |
else if (indexA_PRE < 31) c1 <= 5'd2; |
else if (indexA_PRE < 34) c1 <= 5'd3; |
else if (indexA_PRE < 37) c1 <= 5'd4; |
else |
case (indexA_PRE) |
6'd37:c1 <= 5'd5; 6'd38,6'd39:c1 <= 5'd6; |
6'd40:c1 <= 5'd7; 6'd41:c1 <= 5'd8; 6'd42:c1 <= 5'd9; 6'd43:c1 <= 5'd10; |
6'd44:c1 <= 5'd11; 6'd45:c1 <= 5'd13; 6'd46:c1 <= 5'd14; 6'd47:c1 <= 5'd16; |
6'd48:c1 <= 5'd18; 6'd49:c1 <= 5'd20; 6'd50:c1 <= 5'd23; 6'd51:c1 <= 5'd25; |
default:c1 <= 5'd0; |
endcase |
default:c1 <= 0; |
endcase |
else |
c1 <= 0; |
|
reg [4:0] c0; |
always @ (bs_curr_PRE or lumaEdgeFlag_PRE or c1 or p2_m_p0_less_beta or q2_m_q0_less_beta) |
if (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4) |
begin |
if (lumaEdgeFlag_PRE) //filter luma edge |
c0 <= ( p2_m_p0_less_beta && q2_m_q0_less_beta)? (c1 + 2): |
((!p2_m_p0_less_beta && !q2_m_q0_less_beta)? c1:(c1+1)); |
else //filter chroma edge |
c0 <= c1 + 1; |
end |
else |
c0 <= 0; |
|
//delta_0i = [(q0 - p0) << 2 + (p1 - q1) + 4] >> 3 : P151 (8-334) of H.264/AVC standard 2003 |
wire [8:0] delta_0i; |
wire need_delta_0i; |
wire [8:0] q0_m_p0; //p0 - q0 |
wire [11:0] delta_0i_tmp; //[(p0 - q0) << 2 + (p1 - q1) + 4] |
assign need_delta_0i = (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4); |
assign q0_m_p0 = (need_delta_0i)? ({1'b0,q0_PRE} + {1'b1,~p0_PRE} + 1):0; |
assign delta_0i_tmp = (need_delta_0i)? ({q0_m_p0[8],q0_m_p0,2'b0} + p1_PRE + {4'b1111,~q1_PRE} + 5):0; |
assign delta_0i = delta_0i_tmp[11:3]; |
|
|
//delta p1i = [(p2 + ((p0 + q0 + 1) >> 1) - (p1 << 1)] >> 1 : P152 (8-341) of H.264/AVC standard 2003 |
//delta q1i = [(q2 + ((p0 + q0 + 1) >> 1) - (q1 << 1)] >> 1 : P152 (8-343) of H.264/AVC standard 2003 |
wire [8:0] delta_p1i,delta_q1i; |
wire need_p1i; |
wire need_q1i; |
wire [8:0] p0_q0_sum; //p0+q0+1 |
wire [9:0] neg_p1_shift; //-(p1 << 1) |
wire [9:0] neg_q1_shift; //-(q1 << 1) |
wire [9:0] delta_p1i_tmp;// (p2 + ((p0 + q0 + 1) >> 1) - (p1 << 1) |
wire [9:0] delta_q1i_tmp;// (q2 + ((p0 + q0 + 1) >> 1) - (q1 << 1) |
assign need_p1i = (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4 && p2_m_p0_less_beta); |
assign need_q1i = (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4 && q2_m_q0_less_beta); |
assign p0_q0_sum = (need_p1i || need_q1i)? ({1'b0,p0_PRE} + {1'b0,q0_PRE} + 1):0; |
assign neg_p1_shift = (need_p1i)? ({1'b1,~p1_PRE,1'b1} + 1):0; |
assign neg_q1_shift = (need_q1i)? ({1'b1,~q1_PRE,1'b1} + 1):0; |
assign delta_p1i_tmp = (need_p1i)? (p2_PRE + p0_q0_sum[8:1] + neg_p1_shift):0; |
assign delta_q1i_tmp = (need_q1i)? (q2_PRE + p0_q0_sum[8:1] + neg_q1_shift):0; |
assign delta_p1i = delta_p1i_tmp[9:1]; |
assign delta_q1i = delta_q1i_tmp[9:1]; |
|
wire [8:0] clip_to_c_0_delta,clip_to_c_p1_delta,clip_to_c_q1_delta; |
wire [4:0] clip_to_c_0_c,clip_to_c_p1_c,clip_to_c_q1_c; |
wire [5:0] clip_to_c_0_out,clip_to_c_p1_out,clip_to_c_q1_out; |
clip_to_c clip_to_c_0 (.delta(clip_to_c_0_delta),.c(clip_to_c_0_c),.out(clip_to_c_0_out)); |
clip_to_c clip_to_c_p1 (.delta(clip_to_c_p1_delta),.c(clip_to_c_p1_c),.out(clip_to_c_p1_out)); |
clip_to_c clip_to_c_q1 (.delta(clip_to_c_q1_delta),.c(clip_to_c_q1_c),.out(clip_to_c_q1_out)); |
|
assign clip_to_c_0_delta = (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4)? delta_0i:0; |
assign clip_to_c_0_c = (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4)? c0:0; |
assign clip_to_c_p1_delta = (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4 && p2_m_p0_less_beta)? delta_p1i:0; |
assign clip_to_c_p1_c = (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4 && p2_m_p0_less_beta)? c1:0; |
assign clip_to_c_q1_delta = (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4 && q2_m_q0_less_beta)? delta_q1i:0; |
assign clip_to_c_q1_c = (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4 && q2_m_q0_less_beta)? c1:0; |
|
// Pipelined parameters |
reg [5:0] delta_0,delta_p1,delta_q1; |
always @ (posedge gclk_DF or negedge reset_n) |
if (reset_n == 1'b0) |
begin delta_0 <= 0; delta_p1 <= 0; delta_q1 <= 0; end |
else if (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4) |
begin |
delta_0 <= clip_to_c_0_out; |
delta_p1 <= (p2_m_p0_less_beta)? clip_to_c_p1_out:0; |
delta_q1 <= (q2_m_q0_less_beta)? clip_to_c_q1_out:0; |
end |
|
reg p2_m_p0_less_beta_FIR,q2_m_q0_less_beta_FIR,p0_m_q0_less_alpha_shift_FIR; |
reg lumaEdgeFlag_FIR,chromaEdgeFlag_FIR; |
reg [2:0] bs_curr_FIR; |
reg [5:0] DF_edge_counter_FIR; |
reg [1:0] one_edge_counter_FIR; |
reg [7:0] p0_FIR,p1_FIR,p2_FIR,p3_FIR; |
reg [7:0] q0_FIR,q1_FIR,q2_FIR,q3_FIR; |
always @ (posedge gclk_DF or negedge reset_n) |
if (reset_n == 1'b0) |
begin |
p2_m_p0_less_beta_FIR <= 0; q2_m_q0_less_beta_FIR <= 0; |
p0_m_q0_less_alpha_shift_FIR <= 0; |
bs_curr_FIR <= 0; |
lumaEdgeFlag_FIR <= 0; chromaEdgeFlag_FIR <= 0; |
DF_edge_counter_FIR <= 6'd48; one_edge_counter_FIR <= 2'd3; |
p0_FIR <= 0; p1_FIR <= 0; p2_FIR <= 0; p3_FIR <= 0; |
q0_FIR <= 0; q1_FIR <= 0; q2_FIR <= 0; q3_FIR <= 0; |
end |
else |
begin |
p2_m_p0_less_beta_FIR <= p2_m_p0_less_beta; |
q2_m_q0_less_beta_FIR <= q2_m_q0_less_beta; |
p0_m_q0_less_alpha_shift_FIR <= p0_m_q0_less_alpha_shift; |
bs_curr_FIR <= bs_curr_PRE; |
lumaEdgeFlag_FIR <= lumaEdgeFlag_PRE; chromaEdgeFlag_FIR <= chromaEdgeFlag_PRE; |
DF_edge_counter_FIR <= DF_edge_counter_PRE; one_edge_counter_FIR <= one_edge_counter_PRE; |
p0_FIR <= p0_PRE; p1_FIR <= p1_PRE; p2_FIR <= p2_PRE; p3_FIR <= p3_PRE; |
q0_FIR <= q0_PRE; q1_FIR <= q1_PRE; q2_FIR <= q2_PRE; q3_FIR <= q3_PRE; |
end |
//--------------------------------------------------------------------- |
//4.FIR: filtering |
//--------------------------------------------------------------------- |
reg [7:0] bs4_strong_FIR_p0,bs4_strong_FIR_p1,bs4_strong_FIR_p2,bs4_strong_FIR_p3; |
reg [7:0] bs4_strong_FIR_q0,bs4_strong_FIR_q1,bs4_strong_FIR_q2,bs4_strong_FIR_q3; |
wire [7:0] bs4_strong_FIR_p0_out,bs4_strong_FIR_p1_out,bs4_strong_FIR_p2_out; |
wire [7:0] bs4_strong_FIR_q0_out,bs4_strong_FIR_q1_out,bs4_strong_FIR_q2_out; |
bs4_strong_FIR bs4_strong_FIR ( |
.p0(bs4_strong_FIR_p0),.p1(bs4_strong_FIR_p1),.p2(bs4_strong_FIR_p2),.p3(bs4_strong_FIR_p3), |
.q0(bs4_strong_FIR_q0),.q1(bs4_strong_FIR_q1),.q2(bs4_strong_FIR_q2),.q3(bs4_strong_FIR_q3), |
.p0_out(bs4_strong_FIR_p0_out),.p1_out(bs4_strong_FIR_p1_out),.p2_out(bs4_strong_FIR_p2_out), |
.q0_out(bs4_strong_FIR_q0_out),.q1_out(bs4_strong_FIR_q1_out),.q2_out(bs4_strong_FIR_q2_out) |
); |
reg [7:0] bs4_weak_FIR0_a,bs4_weak_FIR0_b,bs4_weak_FIR0_c; |
reg [7:0] bs4_weak_FIR1_a,bs4_weak_FIR1_b,bs4_weak_FIR1_c; |
wire [7:0] bs4_weak_FIR0_out,bs4_weak_FIR1_out; |
bs4_weak_FIR bs4_weak_FIR0 (.a(bs4_weak_FIR0_a),.b(bs4_weak_FIR0_b),.c(bs4_weak_FIR0_c),.out(bs4_weak_FIR0_out)); |
bs4_weak_FIR bs4_weak_FIR1 (.a(bs4_weak_FIR1_a),.b(bs4_weak_FIR1_b),.c(bs4_weak_FIR1_c),.out(bs4_weak_FIR1_out)); |
// bs = 4 |
always @ (bs_curr_FIR or lumaEdgeFlag_FIR or p0_m_q0_less_alpha_shift_FIR |
or p2_m_p0_less_beta_FIR or q2_m_q0_less_beta_FIR |
or p0_FIR or p1_FIR or p2_FIR or p3_FIR or q0_FIR or q1_FIR or q2_FIR or q3_FIR) |
if (bs_curr_FIR == 3'd4 && lumaEdgeFlag_FIR == 1'b1 && p0_m_q0_less_alpha_shift_FIR |
&& (p2_m_p0_less_beta_FIR || q2_m_q0_less_beta_FIR)) |
begin |
bs4_strong_FIR_p0 <= p0_FIR; bs4_strong_FIR_p1 <= p1_FIR; |
bs4_strong_FIR_p2 <= p2_FIR; bs4_strong_FIR_p3 <= p3_FIR; |
bs4_strong_FIR_q0 <= q0_FIR; bs4_strong_FIR_q1 <= q1_FIR; |
bs4_strong_FIR_q2 <= q2_FIR; bs4_strong_FIR_q3 <= q3_FIR; |
end |
else |
begin |
bs4_strong_FIR_p0 <= 0; bs4_strong_FIR_p1 <= 0; bs4_strong_FIR_p2 <= 0; bs4_strong_FIR_p3 <= 0; |
bs4_strong_FIR_q0 <= 0; bs4_strong_FIR_q1 <= 0; bs4_strong_FIR_q2 <= 0; bs4_strong_FIR_q3 <= 0; |
end |
always @ (bs_curr_FIR or lumaEdgeFlag_FIR or chromaEdgeFlag_FIR |
or p2_m_p0_less_beta_FIR or p0_m_q0_less_alpha_shift_FIR |
or p1_FIR or p0_FIR or q1_FIR) |
if (bs_curr_FIR == 3'd4 && lumaEdgeFlag_FIR == 1'b1) |
begin |
if (!p2_m_p0_less_beta_FIR || !p0_m_q0_less_alpha_shift_FIR) |
begin |
bs4_weak_FIR0_a <= p1_FIR; bs4_weak_FIR0_b <= p0_FIR; bs4_weak_FIR0_c <= q1_FIR; |
end |
else |
begin |
bs4_weak_FIR0_a <= 0; bs4_weak_FIR0_b <= 0; bs4_weak_FIR0_c <= 0; |
end |
end |
else if (bs_curr_FIR == 3'd4 && chromaEdgeFlag_FIR == 1'b1) |
begin |
bs4_weak_FIR0_a <= p1_FIR; bs4_weak_FIR0_b <= p0_FIR; bs4_weak_FIR0_c <= q1_FIR; |
end |
else |
begin |
bs4_weak_FIR0_a <= 0; bs4_weak_FIR0_b <= 0; bs4_weak_FIR0_c <= 0; |
end |
always @ (bs_curr_FIR or lumaEdgeFlag_FIR or chromaEdgeFlag_FIR |
or q2_m_q0_less_beta_FIR or p0_m_q0_less_alpha_shift_FIR |
or q1_FIR or q0_FIR or p1_FIR) |
if (bs_curr_FIR == 3'd4 && lumaEdgeFlag_FIR == 1'b1) |
begin |
if (!q2_m_q0_less_beta_FIR || !p0_m_q0_less_alpha_shift_FIR) |
begin |
bs4_weak_FIR1_a <= q1_FIR; bs4_weak_FIR1_b <= q0_FIR; bs4_weak_FIR1_c <= p1_FIR; |
end |
else |
begin |
bs4_weak_FIR1_a <= 0; bs4_weak_FIR1_b <= 0; bs4_weak_FIR1_c <= 0; |
end |
end |
else if (bs_curr_FIR == 3'd4 && chromaEdgeFlag_FIR == 1'b1) |
begin |
bs4_weak_FIR1_a <= q1_FIR; bs4_weak_FIR1_b <= q0_FIR; bs4_weak_FIR1_c <= p1_FIR; |
end |
else |
begin |
bs4_weak_FIR1_a <= 0; bs4_weak_FIR1_b <= 0; bs4_weak_FIR1_c <= 0; |
end |
//bs = 1 ~ 3,for p0 and q0 filtering |
wire [9:0] p0_MW_tmp,q0_MW_tmp; |
wire [7:0] p0_MW_clipped,q0_MW_clipped; |
assign p0_MW_tmp = (bs_curr_FIR != 0 && bs_curr_FIR != 3'd4)? ({2'b0,p0_FIR} + {{4{delta_0[5]}},delta_0}):0; |
assign q0_MW_tmp = (bs_curr_FIR != 0 && bs_curr_FIR != 3'd4)? ({2'b0,q0_FIR} + |
{~delta_0[5],~delta_0[5],~delta_0[5],~delta_0[5],~delta_0} + 1):0; |
assign p0_MW_clipped = (p0_MW_tmp[9] == 1'b1)? 0:((p0_MW_tmp[8] == 1'b1)? 8'd255:p0_MW_tmp[7:0]); |
assign q0_MW_clipped = (q0_MW_tmp[9] == 1'b1)? 0:((q0_MW_tmp[8] == 1'b1)? 8'd255:q0_MW_tmp[7:0]); |
|
// Pipelined parameters |
reg [7:0] p0_MW,p1_MW,p2_MW,p3_MW; |
reg [7:0] q0_MW,q1_MW,q2_MW,q3_MW; |
always @ (posedge gclk_DF or negedge reset_n) |
if (reset_n == 1'b0) |
begin |
p0_MW <= 0; p1_MW <= 0; p2_MW <= 0; |
q0_MW <= 0; q1_MW <= 0; q2_MW <= 0; |
end |
else if (bs_curr_FIR == 3'd4) |
begin |
if (lumaEdgeFlag_FIR) |
begin |
p0_MW <= (p0_m_q0_less_alpha_shift_FIR && p2_m_p0_less_beta_FIR)? |
bs4_strong_FIR_p0_out:bs4_weak_FIR0_out; |
q0_MW <= (p0_m_q0_less_alpha_shift_FIR && q2_m_q0_less_beta_FIR)? |
bs4_strong_FIR_q0_out:bs4_weak_FIR1_out; |
p1_MW <= (p0_m_q0_less_alpha_shift_FIR && p2_m_p0_less_beta_FIR)? |
bs4_strong_FIR_p1_out:p1_FIR; |
q1_MW <= (p0_m_q0_less_alpha_shift_FIR && q2_m_q0_less_beta_FIR)? |
bs4_strong_FIR_q1_out:q1_FIR; |
p2_MW <= (p0_m_q0_less_alpha_shift_FIR && p2_m_p0_less_beta_FIR)? |
bs4_strong_FIR_p2_out:p2_FIR; |
q2_MW <= (p0_m_q0_less_alpha_shift_FIR && q2_m_q0_less_beta_FIR)? |
bs4_strong_FIR_q2_out:q2_FIR; |
end |
else |
begin |
p0_MW <= bs4_weak_FIR0_out; q0_MW <= bs4_weak_FIR1_out; |
p1_MW <= p1_FIR; q1_MW <= q1_FIR; |
p2_MW <= p2_FIR; q2_MW <= q2_FIR; |
end |
end |
else if (bs_curr_FIR != 0 && bs_curr_FIR != 3'd4) |
begin |
p0_MW <= p0_MW_clipped; |
q0_MW <= q0_MW_clipped; |
p1_MW <= (lumaEdgeFlag_FIR)? ((p2_m_p0_less_beta_FIR)? (p1_FIR + {delta_p1[5],delta_p1[5],delta_p1}):p1_FIR):p1_FIR; |
q1_MW <= (lumaEdgeFlag_FIR)? ((q2_m_q0_less_beta_FIR)? (q1_FIR + {delta_q1[5],delta_q1[5],delta_q1}):q1_FIR):q1_FIR; |
p2_MW <= p2_FIR; |
q2_MW <= q2_FIR; |
end |
else |
begin |
p0_MW <= p0_FIR; p1_MW <= p1_FIR; p2_MW <= p2_FIR; |
q0_MW <= q0_FIR; q1_MW <= q1_FIR; q2_MW <= q2_FIR; |
end |
|
reg [2:0] bs_curr_MW; |
reg [5:0] DF_edge_counter_MW; |
reg [1:0] one_edge_counter_MW; |
always @ (posedge gclk_DF or negedge reset_n) |
if (reset_n == 1'b0) |
begin |
DF_edge_counter_MW <= 6'd48; one_edge_counter_MW <= 2'd3; |
p3_MW <= 0; q3_MW <= 0; |
bs_curr_MW <= 0; |
end |
else |
begin |
DF_edge_counter_MW <= DF_edge_counter_FIR; p3_MW <= p3_FIR; |
one_edge_counter_MW <= one_edge_counter_FIR; q3_MW <= q3_FIR; |
bs_curr_MW <= bs_curr_FIR; |
end |
endmodule |
|
module absolute (a,b,out); |
input [7:0] a,b; |
output [7:0] out; |
|
assign out = (a > b)? (a - b):(b - a); |
endmodule |
|
module clip_to_c (delta,c,out); |
input [8:0] delta; |
input [4:0] c; // 0 ~ 25, [4:0] |
output [5:0] out; // -25 ~ 25, [5:0] |
reg [5:0] out; |
|
wire [5:0] neg_c; //-25 ~ 25,[5:0] |
assign neg_c = {1'b1,~c} + 1; |
|
always @ (delta or c or neg_c) |
if (delta[8] == 1'b0) //delta is positive |
out <= (delta[7:0] > {3'b0,c})? {1'b0,c}:delta[5:0]; |
else //delta is negtive |
out <= (delta[7:0] < {2'b11,neg_c})? {1'b1,neg_c}:delta[5:0]; |
endmodule |
|
module bs4_strong_FIR (p0,p1,p2,p3,q0,q1,q2,q3,p0_out,p1_out,p2_out,q0_out,q1_out,q2_out); |
input [7:0] p0,p1,p2,p3,q0,q1,q2,q3; |
output [7:0] p0_out,p1_out,p2_out,q0_out,q1_out,q2_out; |
|
wire [8:0] sum_p2p3,sum_p1p2,sum_p0q0,sum_p1q1,sum_q1q2,sum_q2q3; |
assign sum_p2p3 = p2 + p3; |
assign sum_p1p2 = p1 + p2; |
assign sum_p0q0 = p0 + q0; |
assign sum_p1q1 = p1 + q1; |
assign sum_q1q2 = q1 + q2; |
assign sum_q2q3 = q2 + q3; |
|
wire [9:0] sum_p2p3_x2,sum_q2q3_x2; |
assign sum_p2p3_x2 = {sum_p2p3,1'b0}; |
assign sum_q2q3_x2 = {sum_q2q3,1'b0}; |
|
wire [9:0] sum_0,sum_1,sum_2; |
assign sum_0 = sum_p0q0 + sum_p1p2; |
assign sum_1 = sum_p0q0 + sum_p1q1; |
assign sum_2 = sum_p0q0 + sum_q1q2; |
|
wire [10:0] p0_tmp,p2_tmp,q0_tmp,q2_tmp; |
assign p0_tmp = sum_0 + sum_1; |
assign p2_tmp = sum_p2p3_x2 + sum_0; |
assign q0_tmp = sum_1 + sum_2; |
assign q2_tmp = sum_q2q3_x2 + sum_2; |
|
assign p0_out = (p0_tmp + 4) >> 3; |
assign p1_out = (sum_0 + 2) >> 2; |
assign p2_out = (p2_tmp + 4) >> 3; |
assign q0_out = (q0_tmp + 4) >> 3; |
assign q1_out = (sum_2 + 2) >> 2; |
assign q2_out = (q2_tmp + 4) >> 3; |
endmodule |
|
module bs4_weak_FIR (a,b,c,out); |
input [7:0] a,b,c; |
output [7:0] out; |
|
wire [8:0] a_x2; |
assign a_x2 = {a,1'b0}; |
|
wire [8:0] sum_bc; |
assign sum_bc = b + c; |
|
wire [9:0] out_tmp; |
assign out_tmp = (a_x2 + sum_bc) + 2; |
assign out = out_tmp[9:2]; |
endmodule |
|
/trunk/src/Inter_mv_decoding.v
0,0 → 1,2612
//-------------------------------------------------------------------------------------------------- |
// Design : nova |
// Author(s) : Ke Xu |
// Email : eexuke@yahoo.com |
// File : Inter_mv_decoding.v |
// Generated : May 25, 2005 |
// Copyright (C) 2008 Ke Xu |
//------------------------------------------------------------------------------------------------- |
// Description |
// Decoding the motion vector x and motion vector y for Inter prediction and P_skip |
// SearchRange = 16pix -> 64 -> -64 ~ + 64 -> mvd[7:0], mv[7:0], mvp[7:0] |
//------------------------------------------------------------------------------------------------- |
|
// synopsys translate_off |
`include "timescale.v" |
// synopsys translate_on |
`include "nova_defines.v" |
|
module Inter_mv_decoding (clk,reset_n,Is_skip_run_entry,Is_skip_run_end, |
slice_data_state,mb_pred_state,sub_mb_pred_state,mvd, |
mb_num,mb_num_h,mb_num_v,mb_type_general,sub_mb_type,end_of_MB_DEC,mbPartIdx,subMbPartIdx,compIdx, |
MBTypeGen_mbAddrA,MBTypeGen_mbAddrB_reg,MBTypeGen_mbAddrD, |
mvx_mbAddrB_dout,mvy_mbAddrB_dout,mvx_mbAddrC_dout,mvy_mbAddrC_dout,mv_mbAddrB_rd_for_DF, |
|
skip_mv_calc,Is_skipMB_mv_calc,mvx_mbAddrA,mvy_mbAddrA, |
mvx_mbAddrB_cs_n,mvx_mbAddrB_wr_n,mvx_mbAddrB_rd_addr,mvx_mbAddrB_wr_addr,mvx_mbAddrB_din, |
mvy_mbAddrB_cs_n,mvy_mbAddrB_wr_n,mvy_mbAddrB_rd_addr,mvy_mbAddrB_wr_addr,mvy_mbAddrB_din, |
mvx_mbAddrC_cs_n,mvx_mbAddrC_wr_n,mvx_mbAddrC_rd_addr,mvx_mbAddrC_wr_addr,mvx_mbAddrC_din, |
mvy_mbAddrC_cs_n,mvy_mbAddrC_wr_n,mvy_mbAddrC_rd_addr,mvy_mbAddrC_wr_addr,mvy_mbAddrC_din, |
mv_is16x16, |
mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3, |
mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3); |
input clk,reset_n; |
input Is_skip_run_entry; |
input Is_skip_run_end; |
input [3:0] slice_data_state; |
input [2:0] mb_pred_state; |
input [1:0] sub_mb_pred_state; |
input [7:0] mvd; |
input [6:0] mb_num; |
input [3:0] mb_num_h; |
input [3:0] mb_num_v; |
input [3:0] mb_type_general; |
input [1:0] sub_mb_type; |
input end_of_MB_DEC; |
input [1:0] mbPartIdx,subMbPartIdx; |
input compIdx; |
input [1:0] MBTypeGen_mbAddrA; |
input MBTypeGen_mbAddrD; |
input [21:0] MBTypeGen_mbAddrB_reg; |
input [31:0] mvx_mbAddrB_dout,mvy_mbAddrB_dout; |
input [7:0] mvx_mbAddrC_dout,mvy_mbAddrC_dout; |
input mv_mbAddrB_rd_for_DF; |
|
output skip_mv_calc; |
output Is_skipMB_mv_calc; |
output [31:0] mvx_mbAddrA,mvy_mbAddrA; |
output mvx_mbAddrB_cs_n,mvy_mbAddrB_cs_n,mvx_mbAddrC_cs_n,mvy_mbAddrC_cs_n; |
output mvx_mbAddrB_wr_n,mvy_mbAddrB_wr_n,mvx_mbAddrC_wr_n,mvy_mbAddrC_wr_n; |
output [3:0] mvx_mbAddrB_rd_addr,mvy_mbAddrB_rd_addr,mvx_mbAddrC_rd_addr,mvy_mbAddrC_rd_addr; |
output [3:0] mvx_mbAddrB_wr_addr,mvy_mbAddrB_wr_addr,mvx_mbAddrC_wr_addr,mvy_mbAddrC_wr_addr; |
output [31:0] mvx_mbAddrB_din,mvy_mbAddrB_din; |
output [7:0] mvx_mbAddrC_din,mvy_mbAddrC_din; |
output mv_is16x16; |
output [31:0] mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3; |
output [31:0] mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3; |
reg mvx_mbAddrB_cs_n,mvy_mbAddrB_cs_n,mvx_mbAddrC_cs_n,mvy_mbAddrC_cs_n; |
reg mvx_mbAddrB_wr_n,mvy_mbAddrB_wr_n,mvx_mbAddrC_wr_n,mvy_mbAddrC_wr_n; |
reg [3:0] mvx_mbAddrB_rd_addr,mvy_mbAddrB_rd_addr,mvx_mbAddrC_rd_addr,mvy_mbAddrC_rd_addr; |
reg [3:0] mvx_mbAddrB_wr_addr,mvy_mbAddrB_wr_addr,mvx_mbAddrC_wr_addr,mvy_mbAddrC_wr_addr; |
reg [31:0] mvx_mbAddrB_din,mvy_mbAddrB_din; |
reg [7:0] mvx_mbAddrC_din,mvy_mbAddrC_din; |
reg mv_is16x16; |
reg [31:0] mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3; |
reg [31:0] mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3; |
|
reg [7:0] mvpAx,mvpAy,mvpBx,mvpBy,mvpCx,mvpCy; |
reg [31:0] mvx_mbAddrA,mvy_mbAddrA; |
wire [7:0] mvx_mbAddrD,mvy_mbAddrD; |
reg [7:0] mvpx,mvpy,mvx,mvy; |
|
reg skip_mv_calc; //This signal is of reg type and is active for one cycle after end_of_MB_DEC and before |
//trigger_blk4x4_inter_pred.It is used to direct motion vector prediction for skipped MB |
always @ (posedge clk) |
if (reset_n == 1'b0) |
skip_mv_calc <= 1'b0; |
else if (slice_data_state == `skip_run_duration && end_of_MB_DEC && !Is_skip_run_end) |
skip_mv_calc <= 1'b1; |
else |
skip_mv_calc <= 1'b0; |
|
wire Is_skipMB_mv_calc; |
assign Is_skipMB_mv_calc = Is_skip_run_entry | skip_mv_calc; |
|
reg [1:0] MBTypeGen_mbAddrB; |
reg [1:0] MBTypeGen_mbAddrC; |
always @ (mb_num_h or MBTypeGen_mbAddrB_reg) |
case (mb_num_h) |
0 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[1:0]; |
1 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[3:2]; |
2 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[5:4]; |
3 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[7:6]; |
4 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[9:8]; |
5 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[11:10]; |
6 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[13:12]; |
7 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[15:14]; |
8 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[17:16]; |
9 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[19:18]; |
10:MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[21:20]; |
default:MBTypeGen_mbAddrB <= 0; |
endcase |
always @ (mb_num_h or MBTypeGen_mbAddrB_reg) |
case (mb_num_h) |
0:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[3:2]; |
1:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[5:4]; |
2:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[7:6]; |
3:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[9:8]; |
4:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[11:10]; |
5:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[13:12]; |
6:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[15:14]; |
7:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[17:16]; |
8:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[19:18]; |
9:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[21:20]; |
default:MBTypeGen_mbAddrC <= 0; |
endcase |
|
wire refIdxL0_A; //Here refIdxL0_A == 1'b1 is equal to refIdxL0_A == -1 in Page122 of H.264 2003.5 standard |
wire refIdxL0_B; //Here refIdxL0_B == 1'b1 is equal to refIdxL0_B == -1 in Page122 of H.264 2003.5 standard |
reg refIdxL0_C; //Here refIdxL0_C == 1'b1 is equal to refIdxL0_C == -1 in Page122 of H.264 2003.5 standard |
|
assign refIdxL0_A = ( |
//P_skip |
(Is_skipMB_mv_calc || |
//Inter16x16,Inter16x8,Inter8x16 left blk |
(mb_pred_state == `mvd_l0_s && (mb_type_general == `MB_Inter16x16 || mb_type_general == `MB_Inter16x8 || (mb_type_general == `MB_Inter8x16 && mbPartIdx == 0))) || |
//Inter8x8,left most blk |
(sub_mb_pred_state == `sub_mvd_l0_s && (mbPartIdx == 0 || mbPartIdx == 2) && ( |
sub_mb_type == 0 || |
sub_mb_type == 1 || |
(sub_mb_type == 2 && subMbPartIdx == 0) || |
(sub_mb_type == 3 && (subMbPartIdx == 0 || subMbPartIdx == 2))))) && |
(mb_num_h == 0 || MBTypeGen_mbAddrA[1] == 1))? 1'b1:1'b0; |
|
assign refIdxL0_B = ( |
//P_skip |
(Is_skipMB_mv_calc || |
//Inter16x16,Inter16x8 upper blk,Inter8x16 |
(mb_pred_state == `mvd_l0_s && (mb_type_general == `MB_Inter16x16 || (mb_type_general == `MB_Inter16x8 && mbPartIdx == 0) || mb_type_general == `MB_Inter8x16)) || |
//Inter8x8,left most blk |
(sub_mb_pred_state == `sub_mvd_l0_s && (mbPartIdx == 0 || mbPartIdx == 1) && ( |
sub_mb_type == 0 || |
sub_mb_type == 2 || |
(sub_mb_type == 1 && subMbPartIdx == 0) || |
(sub_mb_type == 3 && (subMbPartIdx == 0 || subMbPartIdx == 1))))) && |
(mb_num_v == 0 || MBTypeGen_mbAddrB[1] == 1))? 1'b1:1'b0; |
|
always @ (Is_skipMB_mv_calc or mb_pred_state or sub_mb_pred_state or mb_type_general or mb_num_v or mb_num_h |
or sub_mb_type or mbPartIdx or subMbPartIdx or MBTypeGen_mbAddrC[1] or MBTypeGen_mbAddrD |
or refIdxL0_A or refIdxL0_B) |
//P_skip,Inter16x16 |
if (Is_skipMB_mv_calc || (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16)) |
begin |
if (mb_num_v == 0) refIdxL0_C <= 1'b1; |
else if (mb_num_h == 10) refIdxL0_C <= (MBTypeGen_mbAddrD == `MB_addrD_Intra)? 1'b1:1'b0; |
else refIdxL0_C <= (MBTypeGen_mbAddrC[1] == 1'b1)? 1'b1:1'b0; |
end |
//Inter16x8 |
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8) |
begin |
if (mbPartIdx == 0) //upper blk |
begin |
if (mb_num_v == 0) refIdxL0_C <= 1'b1; |
else if (mb_num_h == 10) refIdxL0_C <= (MBTypeGen_mbAddrD == `MB_addrD_Intra)? 1'b1:1'b0; |
else refIdxL0_C <= (MBTypeGen_mbAddrC[1] == 1'b1)? 1'b1:1'b0; |
end |
else //bottom blk |
refIdxL0_C <= refIdxL0_A; |
end |
//Inter8x16 |
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16) |
begin |
if (mbPartIdx == 0) //left blk |
refIdxL0_C <= refIdxL0_B; |
else //right blk |
begin |
if (mb_num_v == 0 || mb_num_h == 10) refIdxL0_C <= refIdxL0_B; |
else refIdxL0_C <= (MBTypeGen_mbAddrC[1] == 1'b1)? 1'b1:1'b0; |
end |
end |
//Inter8x8 and below |
else if (sub_mb_pred_state == `sub_mvd_l0_s) |
case (mbPartIdx) |
2'b00: //left-top 8x8 blk |
case (sub_mb_type) |
0:refIdxL0_C <= refIdxL0_B; |
1:refIdxL0_C <= (subMbPartIdx == 0)? refIdxL0_B:refIdxL0_A; |
2:refIdxL0_C <= refIdxL0_B; |
3: |
case (subMbPartIdx) |
0,1:refIdxL0_C <= refIdxL0_B; |
2,3:refIdxL0_C <= 1'b0; |
endcase |
endcase |
2'b01: //right-top 8x8 blk |
case (sub_mb_type) |
0: //8x8 |
if (mb_num_v == 0) refIdxL0_C <= 1'b1; |
else if (mb_num_h == 10) refIdxL0_C <= refIdxL0_B; |
else refIdxL0_C <= (MBTypeGen_mbAddrC[1] == 1'b1)? 1'b1:1'b0; |
1: //8x4 |
if (subMbPartIdx == 0) |
begin |
if (mb_num_v == 0) refIdxL0_C <= 1'b1; |
else if (mb_num_h == 10) refIdxL0_C <= refIdxL0_B; |
else refIdxL0_C <= (MBTypeGen_mbAddrC[1] == 1'b1)? 1'b1:1'b0; |
end |
else |
refIdxL0_C <= 1'b0; |
2: //4x8 |
if (subMbPartIdx == 0) refIdxL0_C <= refIdxL0_B; |
else |
begin |
if (mb_num_v == 0) refIdxL0_C <= 1'b1; |
else if (mb_num_h == 10) refIdxL0_C <= refIdxL0_B; |
else refIdxL0_C <= (MBTypeGen_mbAddrC[1] == 1'b1)? 1'b1:1'b0; |
end |
3: //4x4 |
case (subMbPartIdx) |
0:refIdxL0_C <= refIdxL0_B; |
1: |
begin |
if (mb_num_v == 0) refIdxL0_C <= 1'b1; |
else if (mb_num_h == 10) refIdxL0_C <= refIdxL0_B; |
else refIdxL0_C <= (MBTypeGen_mbAddrC[1] == 1'b1)? 1'b1:1'b0; |
end |
2,3:refIdxL0_C <= 1'b0; |
endcase |
endcase |
2'b10: //left-bottom 8x8 blk |
case (sub_mb_type) |
0:refIdxL0_C <= 1'b0; |
1:refIdxL0_C <= (subMbPartIdx == 0)? 1'b0:refIdxL0_A; |
2:refIdxL0_C <= 1'b0; |
3:refIdxL0_C <= 1'b0; |
endcase |
2'b11: //right-bottom 8x8 blk |
refIdxL0_C <= 1'b0; |
endcase |
else |
refIdxL0_C <= 1'b0; |
|
//------------- |
//mvpAx |
//------------- |
always @ (Is_skipMB_mv_calc or mb_pred_state or sub_mb_pred_state |
or mb_type_general or sub_mb_type or mbPartIdx or subMbPartIdx or compIdx |
or mvx_mbAddrA or mvx_CurrMb0 or mvx_CurrMb1 or mvx_CurrMb2 or mvx_CurrMb3 |
or refIdxL0_A or refIdxL0_B or refIdxL0_C) |
//P_skip or Inter16x16 |
if (Is_skipMB_mv_calc || (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 0)) |
mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[7:0]; |
//Inter16x8 |
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 0) |
begin |
if (mbPartIdx == 0) |
mvpAx <= {8{refIdxL0_B}} & mvx_mbAddrA[7:0]; |
else |
mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[23:16]; |
end |
//Inter8x16 |
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 0) |
begin |
if (mbPartIdx == 0) |
mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[7:0]; |
else |
mvpAx <= {8{refIdxL0_C}} & mvx_CurrMb0[15:8]; |
end |
//Inter8x8 |
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 0) //sub_mb_pred |
case (mbPartIdx) |
0: |
case (sub_mb_type) |
0:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[7:0]; |
1: //8x4 |
case (subMbPartIdx) |
0:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[7:0]; |
1:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[15:8]; |
default:mvpAx <= 0; |
endcase |
2: //4x8 |
case (subMbPartIdx) |
0:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[7:0]; |
1:mvpAx <= mvx_CurrMb0[7:0]; |
default:mvpAx <= 0; |
endcase |
3: //4x4 |
case (subMbPartIdx) |
0:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[7:0]; |
1:mvpAx <= mvx_CurrMb0[7:0]; |
2:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[15:8]; |
3:mvpAx <= mvx_CurrMb0[23:16]; |
endcase |
endcase |
1: |
case (sub_mb_type) |
0:mvpAx <= mvx_CurrMb0[15:8]; |
1: //8x4 |
case (subMbPartIdx) |
0:mvpAx <= mvx_CurrMb0[15:8]; 1:mvpAx <= mvx_CurrMb0[31:24]; |
default:mvpAx <= 0; |
endcase |
2: //4x8 |
case (subMbPartIdx) |
0:mvpAx <= mvx_CurrMb0[15:8]; 1:mvpAx <= mvx_CurrMb1[7:0]; |
default:mvpAx <= 0; |
endcase |
3: //4x4 |
case (subMbPartIdx) |
0:mvpAx <= mvx_CurrMb0[15:8] ; 1:mvpAx <= mvx_CurrMb1[7:0]; |
2:mvpAx <= mvx_CurrMb0[31:24]; 3:mvpAx <= mvx_CurrMb1[23:16]; |
endcase |
endcase |
2: |
case (sub_mb_type) |
0:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[23:16]; |
1: //8x4 |
case (subMbPartIdx) |
0:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[23:16]; |
1:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[31:24]; |
default:mvpAx <= 0; |
endcase |
2: //4x8 |
case (subMbPartIdx) |
0:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[23:16]; |
1:mvpAx <= mvx_CurrMb2[7:0]; |
default:mvpAx <= 0; |
endcase |
3: //4x4 |
case (subMbPartIdx) |
0:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[23:16]; |
1:mvpAx <= mvx_CurrMb2[7:0]; |
2:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[31:24]; |
3:mvpAx <= mvx_CurrMb2[23:16]; |
endcase |
endcase |
3: |
case (sub_mb_type) |
0:mvpAx <= mvx_CurrMb2[15:8]; |
1: //8x4 |
case (subMbPartIdx) |
0:mvpAx <= mvx_CurrMb2[15:8]; 1:mvpAx <= mvx_CurrMb2[31:24]; |
default:mvpAx <= 0; |
endcase |
2: //4x8 |
case (subMbPartIdx) |
0:mvpAx <= mvx_CurrMb2[15:8]; 1:mvpAx <= mvx_CurrMb3[7:0]; |
default:mvpAx <= 0; |
endcase |
3: //4x4 |
case (subMbPartIdx) |
0:mvpAx <= mvx_CurrMb2[15:8]; 1:mvpAx <= mvx_CurrMb3[7:0]; |
2:mvpAx <= mvx_CurrMb2[31:24]; 3:mvpAx <= mvx_CurrMb3[23:16]; |
endcase |
endcase |
endcase |
else |
mvpAx <= 0; |
|
//------------- |
//mvpAy |
//------------- |
always @ (Is_skipMB_mv_calc or mb_pred_state or sub_mb_pred_state |
or mb_type_general or sub_mb_type or mbPartIdx or subMbPartIdx or compIdx |
or mvy_mbAddrA or mvy_CurrMb0 or mvy_CurrMb1 or mvy_CurrMb2 or mvy_CurrMb3 |
or refIdxL0_A or refIdxL0_B or refIdxL0_C) |
//P_skip or Inter16x16 |
if (Is_skipMB_mv_calc || (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 1)) |
mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[7:0]; |
//Inter16x8 |
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 1) |
begin |
if (mbPartIdx == 0) |
mvpAy <= {8{refIdxL0_B}} & mvy_mbAddrA[7:0]; |
else |
mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[23:16]; |
end |
//Inter8x16 |
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 1) |
begin |
if (mbPartIdx == 0) |
mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[7:0]; |
else |
mvpAy <= {8{refIdxL0_C}} & mvy_CurrMb0[15:8]; |
end |
//Inter8x8 |
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 1) //sub_mb_pred |
case (mbPartIdx) |
0: |
case (sub_mb_type) |
0:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[7:0]; |
1: //8x4 |
case (subMbPartIdx) |
0:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[7:0]; |
1:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[15:8]; |
default:mvpAy <= 0; |
endcase |
2: //4x8 |
case (subMbPartIdx) |
0:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[7:0]; |
1:mvpAy <= mvy_CurrMb0[7:0]; |
default:mvpAy <= 0; |
endcase |
3: //4x4 |
case (subMbPartIdx) |
0:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[7:0]; |
1:mvpAy <= mvy_CurrMb0[7:0]; |
2:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[15:8]; |
3:mvpAy <= mvy_CurrMb0[23:16]; |
endcase |
endcase |
1: |
case (sub_mb_type) |
0:mvpAy <= mvy_CurrMb0[15:8]; |
1: //8x4 |
case (subMbPartIdx) |
0:mvpAy <= mvy_CurrMb0[15:8]; 1:mvpAy <= mvy_CurrMb0[31:24]; |
default:mvpAy <= 0; |
endcase |
2: //4x8 |
case (subMbPartIdx) |
0:mvpAy <= mvy_CurrMb0[15:8]; 1:mvpAy <= mvy_CurrMb1[7:0]; |
default:mvpAy <= 0; |
endcase |
3: //4x4 |
case (subMbPartIdx) |
0:mvpAy <= mvy_CurrMb0[15:8] ; 1:mvpAy <= mvy_CurrMb1[7:0]; |
2:mvpAy <= mvy_CurrMb0[31:24]; 3:mvpAy <= mvy_CurrMb1[23:16]; |
endcase |
endcase |
2: |
case (sub_mb_type) |
0:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[23:16]; |
1: //8x4 |
case (subMbPartIdx) |
0:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[23:16]; |
1:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[31:24]; |
default:mvpAy <= 0; |
endcase |
2: //4x8 |
case (subMbPartIdx) |
0:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[23:16]; |
1:mvpAy <= mvy_CurrMb2[7:0]; |
default:mvpAy <= 0; |
endcase |
3: //4x4 |
case (subMbPartIdx) |
0:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[23:16]; |
1:mvpAy <= mvy_CurrMb2[7:0]; |
2:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[31:24]; |
3:mvpAy <= mvy_CurrMb2[23:16]; |
endcase |
endcase |
3: |
case (sub_mb_type) |
0:mvpAy <= mvy_CurrMb2[15:8]; |
1: //8x4 |
case (subMbPartIdx) |
0:mvpAy <= mvy_CurrMb2[15:8]; 1:mvpAy <= mvy_CurrMb2[31:24]; |
default:mvpAy <= 0; |
endcase |
2: //4x8 |
case (subMbPartIdx) |
0:mvpAy <= mvy_CurrMb2[15:8]; 1:mvpAy <= mvy_CurrMb3[7:0]; |
default:mvpAy <= 0; |
endcase |
3: //4x4 |
case (subMbPartIdx) |
0:mvpAy <= mvy_CurrMb2[15:8]; 1:mvpAy <= mvy_CurrMb3[7:0]; |
2:mvpAy <= mvy_CurrMb2[31:24]; 3:mvpAy <= mvy_CurrMb3[23:16]; |
endcase |
endcase |
endcase |
else |
mvpAy <= 0; |
//------------- |
//mvpBx |
//------------- |
//if B is not available,it can be predicted from A when both B and C are not available |
always @ (Is_skipMB_mv_calc or mb_pred_state or sub_mb_pred_state or mb_type_general or sub_mb_type |
or mb_num or mb_num_v or mbPartIdx or subMbPartIdx or compIdx or MBTypeGen_mbAddrA[1] or MBTypeGen_mbAddrB[1] |
or mvx_mbAddrA or mvx_mbAddrB_dout or mvx_CurrMb0 or mvx_CurrMb1 or mvx_CurrMb2 or mvx_CurrMb3 |
or refIdxL0_A or refIdxL0_B or refIdxL0_C) |
//P_skip or Inter16x16 |
if (Is_skipMB_mv_calc || (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 0)) |
begin |
if (mb_num == 0) mvpBx <= 0; |
else if (mb_num_v == 0) mvpBx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0]; |
else mvpBx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[31:24]; |
end |
//Inter16x8 |
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 0) |
begin |
if (mbPartIdx == 0) |
begin |
if (mb_num == 0) mvpBx <= 0; |
else if (mb_num_v == 0) mvpBx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0]; |
else mvpBx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[31:24]; |
end |
else //for bottom 8x8 block when mbAddrA is not available |
mvpBx <= (!refIdxL0_A)? 0:mvx_CurrMb0[23:16]; |
end |
//Inter8x16:for left 8x8 block when mbAddrA is not available |
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 0) |
begin |
if (mbPartIdx == 0) //left blk |
mvpBx <= (refIdxL0_A && !refIdxL0_B)? mvx_mbAddrB_dout[31:24]:0; |
else //right blk |
case (!refIdxL0_C) |
1'b1:mvpBx <= 0; |
1'b0: |
if (mb_num_v == 0) |
mvpBx <= mvx_CurrMb0[7:0]; |
else |
mvpBx <= (!refIdxL0_B)? mvx_mbAddrB_dout[15:8]:0; |
endcase |
end |
//Inter8x8 |
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 0) |
case (mbPartIdx) |
0: |
case (sub_mb_type) |
0:if (mb_num == 0) mvpBx <= 0; |
else if (mb_num_v == 0) mvpBx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0]; |
else mvpBx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[31:24]; |
1: //8x4 |
case (subMbPartIdx) |
0:if (mb_num == 0) mvpBx <= 0; |
else if (mb_num_v == 0) mvpBx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0]; |
else mvpBx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[31:24]; |
1:mvpBx <= mvx_CurrMb0[7:0]; |
default:mvpBx <= 0; |
endcase |
2: //4x8 |
case (subMbPartIdx) |
0:if (mb_num == 0) mvpBx <= 0; |
else if (mb_num_v == 0) mvpBx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0]; |
else mvpBx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[31:24]; |
1:if (mb_num_v == 0) mvpBx <= mvx_CurrMb0[7:0]; |
else mvpBx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[23:16]; |
default:mvpBx <= 0; |
endcase |
3: //4x4 |
case (subMbPartIdx) |
0:if (mb_num == 0) mvpBx <= 0; |
else if (mb_num_v == 0) mvpBx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0]; |
else mvpBx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[31:24]; |
1:if (mb_num_v == 0) mvpBx <= mvx_CurrMb0[7:0]; |
else mvpBx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[23:16]; |
2:mvpBx <= mvx_CurrMb0[7:0]; |
3:mvpBx <= mvx_CurrMb0[15:8]; |
endcase |
endcase |
1: |
case (sub_mb_type) |
0:mvpBx <= (mb_num_v == 0)? mvx_CurrMb0[15:8]:((MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8]); |
1: //8x4 |
case (subMbPartIdx) |
0:mvpBx <= (mb_num_v == 0)? mvx_CurrMb0[15:8]:((MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8]); |
1:mvpBx <= mvx_CurrMb1[7:0]; |
default:mvpBx <= 0; |
endcase |
2: //4x8 |
case (subMbPartIdx) |
0:mvpBx <= (mb_num_v == 0)? mvx_CurrMb0[15:8]:((MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8]); |
1:mvpBx <= (mb_num_v == 0)? mvx_CurrMb1[7:0] :((MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[7:0]); |
default:mvpBx <= 0; |
endcase |
3: //4x4 |
case (subMbPartIdx) |
0:mvpBx <= (mb_num_v == 0)? mvx_CurrMb0[15:8]:((MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8]); |
1:mvpBx <= (mb_num_v == 0)? mvx_CurrMb1[7:0] :((MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[7:0]); |
2:mvpBx <= mvx_CurrMb1[7:0]; |
3:mvpBx <= mvx_CurrMb1[15:8]; |
endcase |
endcase |
2: |
case (sub_mb_type) |
0:mvpBx <= mvx_CurrMb0[23:16]; |
1: //8x4 |
case (subMbPartIdx) |
0:mvpBx <= mvx_CurrMb0[23:16]; 1:mvpBx <= mvx_CurrMb2[7:0]; default:mvpBx <= 0; |
endcase |
2: //4x8 |
case (subMbPartIdx) |
0:mvpBx <= mvx_CurrMb0[23:16]; 1:mvpBx <= mvx_CurrMb0[31:24]; default:mvpBx <= 0; |
endcase |
3: //4x4 |
case (subMbPartIdx) |
0:mvpBx <= mvx_CurrMb0[23:16]; 1:mvpBx <= mvx_CurrMb0[31:24]; |
2:mvpBx <= mvx_CurrMb2[7:0]; 3:mvpBx <= mvx_CurrMb2[15:8]; |
endcase |
endcase |
3: |
case (sub_mb_type) |
0:mvpBx <= mvx_CurrMb1[23:16]; |
1: //8x4 |
case (subMbPartIdx) |
0:mvpBx <= mvx_CurrMb1[23:16]; 1:mvpBx <= mvx_CurrMb3[7:0]; default:mvpBx <= 0; |
endcase |
2: //4x8 |
case (subMbPartIdx) |
0:mvpBx <= mvx_CurrMb1[23:16]; 1:mvpBx <= mvx_CurrMb1[31:24]; default:mvpBx <= 0; |
endcase |
3: //4x4 |
case (subMbPartIdx) |
0:mvpBx <= mvx_CurrMb1[23:16]; 1:mvpBx <= mvx_CurrMb1[31:24]; |
2:mvpBx <= mvx_CurrMb3[7:0]; 3:mvpBx <= mvx_CurrMb3[15:8]; |
endcase |
endcase |
endcase |
else |
mvpBx <= 0; |
//------------- |
//mvpBy |
//------------- |
//if B is not available,it can be predicted from A when both B and C are not available |
always @ (Is_skipMB_mv_calc or mb_pred_state or sub_mb_pred_state or mb_type_general or sub_mb_type |
or mb_num or mb_num_v or mbPartIdx or subMbPartIdx or compIdx or MBTypeGen_mbAddrA[1] or MBTypeGen_mbAddrB[1] |
or mvy_mbAddrA or mvy_mbAddrB_dout or mvy_CurrMb0 or mvy_CurrMb1 or mvy_CurrMb2 or mvy_CurrMb3 |
or refIdxL0_A or refIdxL0_B or refIdxL0_C) |
//P_skip or Inter16x16 |
if (Is_skipMB_mv_calc || (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 1)) |
begin |
if (mb_num == 0) mvpBy <= 0; |
else if (mb_num_v == 0) mvpBy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0]; |
else mvpBy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[31:24]; |
end |
//Inter16x8 |
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 1) |
begin |
if (mbPartIdx == 0) //upper 8x8 block |
begin |
if (mb_num == 0) mvpBy <= 0; |
else if (mb_num_v == 0) mvpBy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0]; |
else mvpBy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[31:24]; |
end |
else //for bottom 8x8 block when mbAddrA is not available |
mvpBy <= (!refIdxL0_A)? 0:mvy_CurrMb0[23:16]; |
end |
//Inter8x16:for left 8x8 block when mbAddrA is not available |
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 1) |
begin |
if (mbPartIdx == 0) //left blk |
mvpBy <= (refIdxL0_A && !refIdxL0_B)? mvy_mbAddrB_dout[31:24]:0; |
else //right blk |
case (!refIdxL0_C) |
1'b1:mvpBy <= 0; |
1'b0: |
if (mb_num_v == 0) |
mvpBy <= mvy_CurrMb0[7:0]; |
else |
mvpBy <= (!refIdxL0_B)? mvy_mbAddrB_dout[15:8]:0; |
endcase |
end |
//Inter8x8 |
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 1) |
case (mbPartIdx) |
0: |
case (sub_mb_type) |
0:if (mb_num == 0) mvpBy <= 0; |
else if (mb_num_v == 0) mvpBy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0]; |
else mvpBy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[31:24]; |
1: //8x4 |
case (subMbPartIdx) |
0:if (mb_num == 0) mvpBy <= 0; |
else if (mb_num_v == 0) mvpBy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0]; |
else mvpBy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[31:24]; |
1:mvpBy <= mvy_CurrMb0[7:0]; |
default:mvpBy <= 0; |
endcase |
2: //4x8 |
case (subMbPartIdx) |
0:if (mb_num == 0) mvpBy <= 0; |
else if (mb_num_v == 0) mvpBy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0]; |
else mvpBy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[31:24]; |
1:if (mb_num_v == 0) mvpBy <= mvy_CurrMb0[7:0]; |
else mvpBy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[23:16]; |
default:mvpBy <= 0; |
endcase |
3: //4x4 |
case (subMbPartIdx) |
0:if (mb_num == 0) mvpBy <= 0; |
else if (mb_num_v == 0) mvpBy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0]; |
else mvpBy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[31:24]; |
1:if (mb_num_v == 0) mvpBy <= mvy_CurrMb0[7:0]; |
else mvpBy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[23:16]; |
2:mvpBy <= mvy_CurrMb0[7:0]; |
3:mvpBy <= mvy_CurrMb0[15:8]; |
endcase |
endcase |
1: |
case (sub_mb_type) |
0:mvpBy <= (mb_num_v == 0)? mvy_CurrMb0[15:8]:((MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8]); |
1: //8x4 |
case (subMbPartIdx) |
0:mvpBy <= (mb_num_v == 0)? mvy_CurrMb0[15:8]:((MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8]); |
1:mvpBy <= mvy_CurrMb1[7:0]; |
default:mvpBy <= 0; |
endcase |
2: //4x8 |
case (subMbPartIdx) |
0:mvpBy <= (mb_num_v == 0)? mvy_CurrMb0[15:8]:((MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8]); |
1:mvpBy <= (mb_num_v == 0)? mvy_CurrMb1[7:0] :((MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[7:0]); |
default:mvpBy <= 0; |
endcase |
3: //4x4 |
case (subMbPartIdx) |
0:mvpBy <= (mb_num_v == 0)? mvy_CurrMb0[15:8]:((MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8]); |
1:mvpBy <= (mb_num_v == 0)? mvy_CurrMb1[7:0] :((MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[7:0]); |
2:mvpBy <= mvy_CurrMb1[7:0]; |
3:mvpBy <= mvy_CurrMb1[15:8]; |
endcase |
endcase |
2: |
case (sub_mb_type) |
0:mvpBy <= mvy_CurrMb0[23:16]; |
1: //8x4 |
case (subMbPartIdx) |
0:mvpBy <= mvy_CurrMb0[23:16]; 1:mvpBy <= mvy_CurrMb2[7:0]; default:mvpBy <= 0; |
endcase |
2: //4x8 |
case (subMbPartIdx) |
0:mvpBy <= mvy_CurrMb0[23:16]; 1:mvpBy <= mvy_CurrMb0[31:24]; default:mvpBy <= 0; |
endcase |
3: //4x4 |
case (subMbPartIdx) |
0:mvpBy <= mvy_CurrMb0[23:16]; 1:mvpBy <= mvy_CurrMb0[31:24]; |
2:mvpBy <= mvy_CurrMb2[7:0]; 3:mvpBy <= mvy_CurrMb2[15:8]; |
endcase |
endcase |
3: |
case (sub_mb_type) |
0:mvpBy <= mvy_CurrMb1[23:16]; |
1: //8x4 |
case (subMbPartIdx) |
0:mvpBy <= mvy_CurrMb1[23:16]; 1:mvpBy <= mvy_CurrMb3[7:0]; default:mvpBy <= 0; |
endcase |
2: //4x8 |
case (subMbPartIdx) |
0:mvpBy <= mvy_CurrMb1[23:16]; 1:mvpBy <= mvy_CurrMb1[31:24]; default:mvpBy <= 0; |
endcase |
3: //4x4 |
case (subMbPartIdx) |
0:mvpBy <= mvy_CurrMb1[23:16]; 1:mvpBy <= mvy_CurrMb1[31:24]; |
2:mvpBy <= mvy_CurrMb3[7:0]; 3:mvpBy <= mvy_CurrMb3[15:8]; |
endcase |
endcase |
endcase |
else |
mvpBy <= 0; |
//------------- |
//mvpCx |
//------------- |
//if C is not available,it can be predicted from D,then from A |
always @ (Is_skipMB_mv_calc or mb_pred_state or sub_mb_pred_state or mb_num or mb_num_h or mb_num_v |
or mb_type_general or sub_mb_type or mbPartIdx or subMbPartIdx or compIdx |
or MBTypeGen_mbAddrA[1] or MBTypeGen_mbAddrB[1] or MBTypeGen_mbAddrC[1] or MBTypeGen_mbAddrD |
or mvx_mbAddrA or mvx_mbAddrB_dout or mvx_mbAddrC_dout or mvx_mbAddrD |
or mvx_CurrMb0 or mvx_CurrMb1 or mvx_CurrMb2 or mvx_CurrMb3 |
or refIdxL0_A or refIdxL0_B or refIdxL0_C) |
//P_skip,Inter16x16 |
if (Is_skipMB_mv_calc || (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 0)) |
begin |
if (mb_num == 0) mvpCx <= 0; |
else if (mb_num_v == 0) mvpCx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0]; |
else if (mb_num_h == 10) mvpCx <= (MBTypeGen_mbAddrD == 1)? 0:mvx_mbAddrD; |
else mvpCx <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvx_mbAddrC_dout; |
end |
//Inter16x8 |
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 0) |
begin |
if (mbPartIdx == 0) |
mvpCx <= (refIdxL0_B && !refIdxL0_C)? ((mb_num_h == 10)? mvx_mbAddrD:mvx_mbAddrC_dout):0; |
else |
mvpCx <= 0; |
end |
//Inter8x16 |
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 0) |
begin |
//when mbAddrA is not available,Inter8x16 left blk needs to have its mbAddrC (= mbAddrB of upper line) derived |
if (mbPartIdx == 0) //left blk |
mvpCx <= (refIdxL0_A && !refIdxL0_B)? mvx_mbAddrB_dout[15:8]:0; |
else //right blk |
begin |
if (mb_num == 0) mvpCx <= 0; |
else if (mb_num_v == 0) mvpCx <= mvx_CurrMb0[15:8]; |
else if (mb_num_h == 10) mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[23:16]; |
else mvpCx <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvx_mbAddrC_dout; |
end |
end |
//Inter8x8 |
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 0) |
case (mbPartIdx) |
0: |
case (sub_mb_type) |
0:if (mb_num == 0) mvpCx <= 0; |
else if (mb_num_v == 0) mvpCx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0]; |
else mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8]; |
1: //8x4 |
case (subMbPartIdx) |
0:if (mb_num == 0) mvpCx <= 0; |
else if (mb_num_v == 0) mvpCx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0]; |
else mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8]; |
1:if (mb_num_h == 0) mvpCx <= 0; |
else mvpCx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrD; |
default:mvpCx <= 0; |
endcase |
2: //4x8 |
case (subMbPartIdx) |
0:if (mb_num == 0) mvpCx <= 0; |
else if (mb_num_v == 0) mvpCx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0]; |
else mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[23:16]; |
1:if (mb_num_v == 0) mvpCx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_CurrMb0[7:0]; |
else mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8]; |
default:mvpCx <= 0; |
endcase |
3: //4x4 |
case (subMbPartIdx) |
0:if (mb_num == 0) mvpCx <= 0; |
else if (mb_num_v == 0) mvpCx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0]; |
else mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[23:16]; |
1:if (mb_num_v == 0) mvpCx <= mvx_CurrMb0[7:0]; |
else mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8]; |
2:mvpCx <= mvx_CurrMb0[15:8]; //always available |
3:mvpCx <= mvx_CurrMb0[7:0]; //always from D |
endcase |
endcase |
1: |
case (sub_mb_type) |
0:if (mb_num_v == 0) mvpCx <= mvx_CurrMb0[15:8]; |
else if (mb_num_h == 10) //predicted from D,but lies initial mbAddrB |
mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[23:16]; |
else mvpCx <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvx_mbAddrC_dout; |
1: //8x4 |
case (subMbPartIdx) |
0:if (mb_num_v == 0) mvpCx <= mvx_CurrMb0[15:8]; |
else if (mb_num_h == 10) //predicted from D,but lies initial mbAddrB |
mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[23:16]; |
else mvpCx <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvx_mbAddrC_dout; |
1:mvpCx <= mvx_CurrMb0[15:8]; //C is always unavailable,D is always available |
default:mvpCx <= 0; |
endcase |
2: //4x8 |
case (subMbPartIdx) |
0:if (mb_num_v == 0) mvpCx <= mvx_CurrMb0[15:8]; |
else mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[7:0]; |
1:if (mb_num_v == 0) mvpCx <= mvx_CurrMb1[7:0]; |
else if (mb_num_h == 10) //predicted from D,but lies in mbAddrB |
mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8]; |
else mvpCx <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvx_mbAddrC_dout; |
default:mvpCx <= 0; |
endcase |
3: //4x4 |
case (subMbPartIdx) |
0:if (mb_num_v == 0) mvpCx <= mvx_CurrMb0[15:8]; |
else mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[7:0]; |
1:if (mb_num_v == 0) mvpCx <= mvx_CurrMb1[7:0]; |
else if (mb_num_h == 10) //predicted from D,but lies initial mbAddrB |
mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8]; |
else mvpCx <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvx_mbAddrC_dout; |
2:mvpCx <= mvx_CurrMb1[15:8]; |
3:mvpCx <= mvx_CurrMb1[7:0]; |
endcase |
endcase |
2: |
case (sub_mb_type) |
0:mvpCx <= mvx_CurrMb1[23:16]; |
1: //8x4 |
case (subMbPartIdx) |
0:mvpCx <= mvx_CurrMb1[23:16]; |
1:if (mb_num_h == 0) mvpCx <= 0; |
else mvpCx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrD; |
default:mvpCx <= 0; |
endcase |
2: //4x8 |
case (subMbPartIdx) |
0:mvpCx <= mvx_CurrMb0[31:24]; 1:mvpCx <= mvx_CurrMb1[23:16]; default:mvpCx <= 0; |
endcase |
3: //4x4 |
case (subMbPartIdx) |
0:mvpCx <= mvx_CurrMb0[31:24]; 1:mvpCx <= mvx_CurrMb1[23:16]; |
2:mvpCx <= mvx_CurrMb2[15:8]; 3:mvpCx <= mvx_CurrMb2[7:0]; |
endcase |
endcase |
3: |
case (sub_mb_type) |
0:mvpCx <= mvx_CurrMb0[31:24]; |
1: //8x4 |
case (subMbPartIdx) |
0:mvpCx <= mvx_CurrMb0[31:24]; 1:mvpCx <= mvx_CurrMb2[15:8]; default:mvpCx <= 0; |
endcase |
2: //4x8 |
case (subMbPartIdx) |
0:mvpCx <= mvx_CurrMb1[31:24]; 1:mvpCx <= mvx_CurrMb1[23:16]; default:mvpCx <= 0; |
endcase |
3: //4x4 |
case (subMbPartIdx) |
0:mvpCx <= mvx_CurrMb1[31:24]; 1:mvpCx <= mvx_CurrMb1[23:16]; |
2:mvpCx <= mvx_CurrMb3[15:8]; 3:mvpCx <= mvx_CurrMb3[7:0]; |
endcase |
endcase |
endcase |
else |
mvpCx <= 0; |
//------------- |
//mvpCy |
//------------- |
//if C is not available,it can be predicted from D,then from A |
always @ (Is_skipMB_mv_calc or mb_pred_state or sub_mb_pred_state or mb_num or mb_num_h or mb_num_v |
or mb_type_general or sub_mb_type or mbPartIdx or subMbPartIdx or compIdx |
or MBTypeGen_mbAddrA[1] or MBTypeGen_mbAddrB[1] or MBTypeGen_mbAddrC[1] or MBTypeGen_mbAddrD |
or mvy_mbAddrA or mvy_mbAddrB_dout or mvy_mbAddrC_dout or mvy_mbAddrD |
or mvy_CurrMb0 or mvy_CurrMb1 or mvy_CurrMb2 or mvy_CurrMb3 |
or refIdxL0_A or refIdxL0_B or refIdxL0_C) |
//P_skip,Inter16x16 |
if (Is_skipMB_mv_calc || (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 1)) |
begin |
if (mb_num == 0) mvpCy <= 0; |
else if (mb_num_v == 0) mvpCy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0]; |
else if (mb_num_h == 10) mvpCy <= (MBTypeGen_mbAddrD == 1)? 0:mvy_mbAddrD; |
else mvpCy <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvy_mbAddrC_dout; |
end |
//Inter16x8 |
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 1) |
begin |
if (mbPartIdx == 0) |
mvpCy <= (refIdxL0_B && !refIdxL0_C)? ((mb_num_h == 10)? mvy_mbAddrD:mvy_mbAddrC_dout):0; |
else |
mvpCy <= 0; |
end |
//Inter8x16 |
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 1) |
begin |
//when mbAddrA is not available,Inter8x16 left blk needs to have its mbAddrC (= mbAddrB of upper line) derived |
if (mbPartIdx == 0) //left blk |
mvpCy <= (refIdxL0_A && !refIdxL0_B)? mvy_mbAddrB_dout[15:8]:0; |
else //right blk |
begin |
if (mb_num == 0) mvpCy <= 0; |
else if (mb_num_v == 0) mvpCy <= mvy_CurrMb0[15:8]; |
else if (mb_num_h == 10) mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[23:16]; |
else mvpCy <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvy_mbAddrC_dout; |
end |
end |
//Inter8x8 |
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 1) |
case (mbPartIdx) |
0: |
case (sub_mb_type) |
0:if (mb_num == 0) mvpCy <= 0; |
else if (mb_num_v == 0) mvpCy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0]; |
else mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8]; |
1: //8x4 |
case (subMbPartIdx) |
0:if (mb_num == 0) mvpCy <= 0; |
else if (mb_num_v == 0) mvpCy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0]; |
else mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8]; |
1:if (mb_num_h == 0) mvpCy <= 0; |
else mvpCy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrD; |
default:mvpCy <= 0; |
endcase |
2: //4x8 |
case (subMbPartIdx) |
0:if (mb_num == 0) mvpCy <= 0; |
else if (mb_num_v == 0) mvpCy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0]; |
else mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[23:16]; |
1:if (mb_num_v == 0) mvpCy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_CurrMb0[7:0]; |
else mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8]; |
default:mvpCy <= 0; |
endcase |
3: //4x4 |
case (subMbPartIdx) |
0:if (mb_num == 0) mvpCy <= 0; |
else if (mb_num_v == 0) mvpCy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0]; |
else mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[23:16]; |
1:if (mb_num_v == 0) mvpCy <= mvy_CurrMb0[7:0]; |
else mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8]; |
2:mvpCy <= mvy_CurrMb0[15:8]; //always available |
3:mvpCy <= mvy_CurrMb0[7:0]; //always from D |
endcase |
endcase |
1: |
case (sub_mb_type) |
0:if (mb_num_v == 0) mvpCy <= mvy_CurrMb0[15:8]; |
else if (mb_num_h == 10) //predicted from D,but lies initial mbAddrB |
mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[23:16]; |
else mvpCy <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvy_mbAddrC_dout; |
1: //8x4 |
case (subMbPartIdx) |
0:if (mb_num_v == 0) mvpCy <= mvy_CurrMb0[15:8]; |
else if (mb_num_h == 10) //predicted from D,but lies initial mbAddrB |
mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[23:16]; |
else mvpCy <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvy_mbAddrC_dout; |
1:mvpCy <= mvy_CurrMb0[15:8]; //C is always unavailable,D is always available |
default:mvpCy <= 0; |
endcase |
2: //4x8 |
case (subMbPartIdx) |
0:if (mb_num_v == 0) mvpCy <= mvy_CurrMb0[15:8]; |
else mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[7:0]; |
1:if (mb_num_v == 0) mvpCy <= mvy_CurrMb1[7:0]; |
else if (mb_num_h == 10) //predicted from D,but lies in mbAddrB |
mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8]; |
else mvpCy <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvy_mbAddrC_dout; |
default:mvpCy <= 0; |
endcase |
3: //4x4 |
case (subMbPartIdx) |
0:if (mb_num_v == 0) mvpCy <= mvy_CurrMb0[15:8]; |
else mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[7:0]; |
1:if (mb_num_v == 0) mvpCy <= mvy_CurrMb1[7:0]; |
else if (mb_num_h == 10) //predicted from D,but lies initial mbAddrB |
mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8]; |
else mvpCy <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvy_mbAddrC_dout; |
2:mvpCy <= mvy_CurrMb1[15:8]; |
3:mvpCy <= mvy_CurrMb1[7:0]; |
endcase |
endcase |
2: |
case (sub_mb_type) |
0:mvpCy <= mvy_CurrMb1[23:16]; |
1: //8x4 |
case (subMbPartIdx) |
0:mvpCy <= mvy_CurrMb1[23:16]; |
1:if (mb_num_h == 0) mvpCy <= 0; |
else mvpCy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrD; |
default:mvpCy <= 0; |
endcase |
2: //4x8 |
case (subMbPartIdx) |
0:mvpCy <= mvy_CurrMb0[31:24]; 1:mvpCy <= mvy_CurrMb1[23:16]; default:mvpCy <= 0; |
endcase |
3: //4x4 |
case (subMbPartIdx) |
0:mvpCy <= mvy_CurrMb0[31:24]; 1:mvpCy <= mvy_CurrMb1[23:16]; |
2:mvpCy <= mvy_CurrMb2[15:8]; 3:mvpCy <= mvy_CurrMb2[7:0]; |
endcase |
endcase |
3: |
case (sub_mb_type) |
0:mvpCy <= mvy_CurrMb0[31:24]; |
1: //8x4 |
case (subMbPartIdx) |
0:mvpCy <= mvy_CurrMb0[31:24]; 1:mvpCy <= mvy_CurrMb2[15:8]; default:mvpCy <= 0; |
endcase |
2: //4x8 |
case (subMbPartIdx) |
0:mvpCy <= mvy_CurrMb1[31:24]; 1:mvpCy <= mvy_CurrMb1[23:16]; default:mvpCy <= 0; |
endcase |
3: //4x4 |
case (subMbPartIdx) |
0:mvpCy <= mvy_CurrMb1[31:24]; 1:mvpCy <= mvy_CurrMb1[23:16]; |
2:mvpCy <= mvy_CurrMb3[15:8]; 3:mvpCy <= mvy_CurrMb3[7:0]; |
endcase |
endcase |
endcase |
else |
mvpCy <= 0; |
//------------------------------------------------ |
//obtain motion vector prediction for current Blk |
//------------------------------------------------ |
wire [8:0] sub_ABx,sub_ACx,sub_BCx; |
wire flag_ABx,flag_ACx,flag_BCx; |
assign sub_ABx = {mvpAx[7],mvpAx[7:0]} - {mvpBx[7],mvpBx[7:0]}; |
assign sub_ACx = {mvpAx[7],mvpAx[7:0]} - {mvpCx[7],mvpCx[7:0]}; |
assign sub_BCx = {mvpBx[7],mvpBx[7:0]} - {mvpCx[7],mvpCx[7:0]}; |
assign flag_ABx = sub_ABx[8]; |
assign flag_ACx = sub_ACx[8]; |
assign flag_BCx = sub_BCx[8]; |
|
reg [7:0] mvpx_median; |
always @ (flag_ABx or flag_ACx or flag_BCx or mvpAx or mvpBx or mvpCx) |
if (((flag_ABx == 1'b1) && (flag_ACx == 1'b0)) || ((flag_ABx == 1'b0) && (flag_ACx == 1'b1))) |
mvpx_median <= mvpAx; |
else if (((flag_ABx == 1'b0) && (flag_BCx == 1'b0)) || ((flag_ABx == 1'b1) && (flag_BCx == 1'b1))) |
mvpx_median <= mvpBx; |
else |
mvpx_median <= mvpCx; |
|
always @ (refIdxL0_A or refIdxL0_B or refIdxL0_C or mvpAx or mvpBx or mvpCx or mvpx_median) |
case ({refIdxL0_A,refIdxL0_B,refIdxL0_C}) |
3'b011:mvpx <= mvpAx; |
3'b101:mvpx <= mvpBx; |
3'b110:mvpx <= mvpCx; |
default:mvpx <= mvpx_median; |
endcase |
|
wire [8:0] sub_ABy,sub_ACy,sub_BCy; |
wire flag_ABy,flag_ACy,flag_BCy; |
assign sub_ABy = {mvpAy[7],mvpAy[7:0]} - {mvpBy[7],mvpBy[7:0]}; |
assign sub_ACy = {mvpAy[7],mvpAy[7:0]} - {mvpCy[7],mvpCy[7:0]}; |
assign sub_BCy = {mvpBy[7],mvpBy[7:0]} - {mvpCy[7],mvpCy[7:0]}; |
assign flag_ABy = sub_ABy[8]; |
assign flag_ACy = sub_ACy[8]; |
assign flag_BCy = sub_BCy[8]; |
|
reg [7:0] mvpy_median; |
always @ (flag_ABy or flag_ACy or flag_BCy or mvpAy or mvpBy or mvpCy) |
if (((flag_ABy == 1'b1) && (flag_ACy == 1'b0)) || ((flag_ABy == 1'b0) && (flag_ACy == 1'b1))) |
mvpy_median <= mvpAy; |
else if (((flag_ABy == 1'b0) && (flag_BCy == 1'b0)) || ((flag_ABy == 1'b1) && (flag_BCy == 1'b1))) |
mvpy_median <= mvpBy; |
else |
mvpy_median <= mvpCy; |
|
always @ (refIdxL0_A or refIdxL0_B or refIdxL0_C or mvpAy or mvpBy or mvpCy or mvpy_median) |
case ({refIdxL0_A,refIdxL0_B,refIdxL0_C}) |
3'b011:mvpy <= mvpAy; |
3'b101:mvpy <= mvpBy; |
3'b110:mvpy <= mvpCy; |
default:mvpy <= mvpy_median; |
endcase |
|
always @ (Is_skipMB_mv_calc or mb_num_h or mb_num_v or mb_pred_state or sub_mb_pred_state or compIdx or mvpx or mvpy |
or mvd or mvpAx or mvpBx or mvpCx or mvpAy or mvpBy or mvpCy or mb_type_general or mbPartIdx |
or refIdxL0_A or refIdxL0_B or refIdxL0_C) |
if (Is_skipMB_mv_calc) |
begin |
//Refer to Page113,section 8.4.1.1 of H.264/AVC 2003.05 standard |
if (mb_num_h == 0 || mb_num_v == 0 || (refIdxL0_A == 0 && mvpAx == 0 && mvpAy == 0) || |
(refIdxL0_B == 0 && mvpBx == 0 && mvpBy == 0)) |
begin mvx <= 0; mvy <= 0; end |
else |
begin mvx <= mvpx; mvy <= mvpy; end |
end |
else if (mb_pred_state == `mvd_l0_s || sub_mb_pred_state == `sub_mvd_l0_s) |
begin |
if (mb_type_general == `MB_Inter16x8) //16x8 |
case (mbPartIdx) |
2'b00: //upper blk |
if (!refIdxL0_B) |
begin |
mvx <= (compIdx == 0)? (mvpBx + mvd):0; |
mvy <= (compIdx == 1)? (mvpBy + mvd):0; |
end |
else |
begin |
mvx <= (compIdx == 0)? (mvpx + mvd):0; |
mvy <= (compIdx == 1)? (mvpy + mvd):0; |
end |
default: //bottom blk |
if (!refIdxL0_A) |
begin |
mvx <= (compIdx == 0)? (mvpAx + mvd):0; |
mvy <= (compIdx == 1)? (mvpAy + mvd):0; |
end |
else |
begin |
mvx <= (compIdx == 0)? (mvpx + mvd):0; |
mvy <= (compIdx == 1)? (mvpy + mvd):0; |
end |
endcase |
else if (mb_type_general == `MB_Inter8x16) //8x16 |
case (mbPartIdx) |
2'b00: //left blk |
if (!refIdxL0_A) |
begin |
mvx <= (compIdx == 0)? (mvpAx + mvd):0; |
mvy <= (compIdx == 1)? (mvpAy + mvd):0; |
end |
else |
begin |
mvx <= (compIdx == 0)? (mvpx + mvd):0; |
mvy <= (compIdx == 1)? (mvpy + mvd):0; |
end |
default: //right blk |
//if mbAddrC is not available but mbAddrB (= mbAddrD) is INTER available (not only available,but also inter |
//available),it still predicted from mbAddrC <- mbAddrD |
if (!refIdxL0_C || (mb_num_h == 10 && !refIdxL0_B)) |
begin |
mvx <= (compIdx == 0)? (mvpCx + mvd):0; |
mvy <= (compIdx == 1)? (mvpCy + mvd):0; |
end |
else |
begin |
mvx <= (compIdx == 0)? (mvpx + mvd):0; |
mvy <= (compIdx == 1)? (mvpy + mvd):0; |
end |
endcase |
else |
begin |
mvx <= (compIdx == 0)? (mvpx + mvd):0; |
mvy <= (compIdx == 1)? (mvpy + mvd):0; |
end |
end |
else |
begin |
mvx <= 0; mvy <= 0; |
end |
//----------------------------------------------------- |
//Current MB write --> CurrMb0,CurrMb1,CurrMb2,CurrMb3 |
//----------------------------------------------------- |
always @ (posedge clk) |
if (reset_n == 0) |
mv_is16x16 <= 0; |
else if (mb_type_general == `MB_Inter16x16 || mb_type_general == `MB_P_skip) |
mv_is16x16 <= 1; |
else |
mv_is16x16 <= 0; |
|
always @ (posedge clk) |
if (reset_n == 0) |
begin |
mvx_CurrMb0 <= 0; mvx_CurrMb1 <= 0; mvx_CurrMb2 <= 0; mvx_CurrMb3 <= 0; |
end |
//Inter16x16 or P_skip |
else if (Is_skipMB_mv_calc || (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 0)) |
mvx_CurrMb0[7:0] <= mvx; |
//Inter16x8 |
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 0) |
case (mbPartIdx) |
0:begin mvx_CurrMb0 <= {mvx,mvx,mvx,mvx}; mvx_CurrMb1 <= {mvx,mvx,mvx,mvx}; end |
1:begin mvx_CurrMb2 <= {mvx,mvx,mvx,mvx}; mvx_CurrMb3 <= {mvx,mvx,mvx,mvx}; end |
endcase |
//Inter8x16 |
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 0) |
case (mbPartIdx) |
0:begin mvx_CurrMb0 <= {mvx,mvx,mvx,mvx}; mvx_CurrMb2 <= {mvx,mvx,mvx,mvx}; end |
1:begin mvx_CurrMb1 <= {mvx,mvx,mvx,mvx}; mvx_CurrMb3 <= {mvx,mvx,mvx,mvx}; end |
endcase |
//Inter8x8 |
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 0) |
case (mbPartIdx) |
0: |
case (sub_mb_type) |
0:mvx_CurrMb0 <= {mvx,mvx,mvx,mvx}; |
1: //8x4 |
case (subMbPartIdx) |
0:begin mvx_CurrMb0[7:0] <= mvx; mvx_CurrMb0[15:8] <= mvx; end |
1:begin mvx_CurrMb0[23:16] <= mvx; mvx_CurrMb0[31:24] <= mvx; end |
endcase |
2: //4x8 |
case (subMbPartIdx) |
0:begin mvx_CurrMb0[7:0] <= mvx; mvx_CurrMb0[23:16] <= mvx; end |
1:begin mvx_CurrMb0[15:8] <= mvx; mvx_CurrMb0[31:24] <= mvx; end |
endcase |
3: //4x4 |
case (subMbPartIdx) |
0:mvx_CurrMb0[7:0] <= mvx; |
1:mvx_CurrMb0[15:8] <= mvx; |
2:mvx_CurrMb0[23:16] <= mvx; |
3:mvx_CurrMb0[31:24] <= mvx; |
endcase |
endcase |
1: |
case (sub_mb_type) |
0:mvx_CurrMb1 <= {mvx,mvx,mvx,mvx}; |
1: //8x4 |
case (subMbPartIdx) |
0:begin mvx_CurrMb1[7:0] <= mvx; mvx_CurrMb1[15:8] <= mvx; end |
1:begin mvx_CurrMb1[23:16] <= mvx; mvx_CurrMb1[31:24] <= mvx; end |
endcase |
2: //4x8 |
case (subMbPartIdx) |
0:begin mvx_CurrMb1[7:0] <= mvx; mvx_CurrMb1[23:16] <= mvx; end |
1:begin mvx_CurrMb1[15:8] <= mvx; mvx_CurrMb1[31:24] <= mvx; end |
endcase |
3: //4x4 |
case (subMbPartIdx) |
0:mvx_CurrMb1[7:0] <= mvx; |
1:mvx_CurrMb1[15:8] <= mvx; |
2:mvx_CurrMb1[23:16] <= mvx; |
3:mvx_CurrMb1[31:24] <= mvx; |
endcase |
endcase |
2: |
case (sub_mb_type) |
0:mvx_CurrMb2 <= {mvx,mvx,mvx,mvx}; |
1: //8x4 |
case (subMbPartIdx) |
0:begin mvx_CurrMb2[7:0] <= mvx; mvx_CurrMb2[15:8] <= mvx; end |
1:begin mvx_CurrMb2[23:16] <= mvx; mvx_CurrMb2[31:24] <= mvx; end |
endcase |
2: //4x8 |
case (subMbPartIdx) |
0:begin mvx_CurrMb2[7:0] <= mvx; mvx_CurrMb2[23:16] <= mvx; end |
1:begin mvx_CurrMb2[15:8] <= mvx; mvx_CurrMb2[31:24] <= mvx; end |
endcase |
3: //4x4 |
case (subMbPartIdx) |
0:mvx_CurrMb2[7:0] <= mvx; |
1:mvx_CurrMb2[15:8] <= mvx; |
2:mvx_CurrMb2[23:16] <= mvx; |
3:mvx_CurrMb2[31:24] <= mvx; |
endcase |
endcase |
3: |
case (sub_mb_type) |
0:mvx_CurrMb3 <= {mvx,mvx,mvx,mvx}; |
1: //8x4 |
case (subMbPartIdx) |
0:begin mvx_CurrMb3[7:0] <= mvx; mvx_CurrMb3[15:8] <= mvx; end |
1:begin mvx_CurrMb3[23:16] <= mvx; mvx_CurrMb3[31:24] <= mvx; end |
endcase |
2: //4x8 |
case (subMbPartIdx) |
0:begin mvx_CurrMb3[7:0] <= mvx; mvx_CurrMb3[23:16] <= mvx; end |
1:begin mvx_CurrMb3[15:8] <= mvx; mvx_CurrMb3[31:24] <= mvx; end |
endcase |
3: //4x4 |
case (subMbPartIdx) |
0:mvx_CurrMb3[7:0] <= mvx; |
1:mvx_CurrMb3[15:8] <= mvx; |
2:mvx_CurrMb3[23:16] <= mvx; |
3:mvx_CurrMb3[31:24] <= mvx; |
endcase |
endcase |
endcase |
always @ (posedge clk) |
if (reset_n == 0) |
begin |
mvy_CurrMb0 <= 0; mvy_CurrMb1 <= 0; mvy_CurrMb2 <= 0; mvy_CurrMb3 <= 0; |
end |
//Inter16x16 or P_skip |
else if (Is_skipMB_mv_calc || (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 1)) |
begin |
mvy_CurrMb0[7:0] <= mvy; |
end |
//Inter16x8 |
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 1) |
case (mbPartIdx) |
0:begin mvy_CurrMb0 <= {mvy,mvy,mvy,mvy}; mvy_CurrMb1 <= {mvy,mvy,mvy,mvy}; end |
1:begin mvy_CurrMb2 <= {mvy,mvy,mvy,mvy}; mvy_CurrMb3 <= {mvy,mvy,mvy,mvy}; end |
endcase |
//Inter8x16 |
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 1) |
case (mbPartIdx) |
0:begin mvy_CurrMb0 <= {mvy,mvy,mvy,mvy}; mvy_CurrMb2 <= {mvy,mvy,mvy,mvy}; end |
1:begin mvy_CurrMb1 <= {mvy,mvy,mvy,mvy}; mvy_CurrMb3 <= {mvy,mvy,mvy,mvy}; end |
endcase |
//Inter8x8 |
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 1) |
case (mbPartIdx) |
0: |
case (sub_mb_type) |
0:mvy_CurrMb0 <= {mvy,mvy,mvy,mvy}; |
1: //8x4 |
case (subMbPartIdx) |
0:begin mvy_CurrMb0[7:0] <= mvy; mvy_CurrMb0[15:8] <= mvy; end |
1:begin mvy_CurrMb0[23:16] <= mvy; mvy_CurrMb0[31:24] <= mvy; end |
endcase |
2: //4x8 |
case (subMbPartIdx) |
0:begin mvy_CurrMb0[7:0] <= mvy; mvy_CurrMb0[23:16] <= mvy; end |
1:begin mvy_CurrMb0[15:8] <= mvy; mvy_CurrMb0[31:24] <= mvy; end |
endcase |
3: //4x4 |
case (subMbPartIdx) |
0:mvy_CurrMb0[7:0] <= mvy; |
1:mvy_CurrMb0[15:8] <= mvy; |
2:mvy_CurrMb0[23:16] <= mvy; |
3:mvy_CurrMb0[31:24] <= mvy; |
endcase |
endcase |
1: |
case (sub_mb_type) |
0:mvy_CurrMb1 <= {mvy,mvy,mvy,mvy}; |
1: //8x4 |
case (subMbPartIdx) |
0:begin mvy_CurrMb1[7:0] <= mvy; mvy_CurrMb1[15:8] <= mvy; end |
1:begin mvy_CurrMb1[23:16] <= mvy; mvy_CurrMb1[31:24] <= mvy; end |
endcase |
2: //4x8 |
case (subMbPartIdx) |
0:begin mvy_CurrMb1[7:0] <= mvy; mvy_CurrMb1[23:16] <= mvy; end |
1:begin mvy_CurrMb1[15:8] <= mvy; mvy_CurrMb1[31:24] <= mvy; end |
endcase |
3: //4x4 |
case (subMbPartIdx) |
0:mvy_CurrMb1[7:0] <= mvy; |
1:mvy_CurrMb1[15:8] <= mvy; |
2:mvy_CurrMb1[23:16] <= mvy; |
3:mvy_CurrMb1[31:24] <= mvy; |
endcase |
endcase |
2: |
case (sub_mb_type) |
0:mvy_CurrMb2 <= {mvy,mvy,mvy,mvy}; |
1: //8x4 |
case (subMbPartIdx) |
0:begin mvy_CurrMb2[7:0] <= mvy; mvy_CurrMb2[15:8] <= mvy; end |
1:begin mvy_CurrMb2[23:16] <= mvy; mvy_CurrMb2[31:24] <= mvy; end |
endcase |
2: //4x8 |
case (subMbPartIdx) |
0:begin mvy_CurrMb2[7:0] <= mvy; mvy_CurrMb2[23:16] <= mvy; end |
1:begin mvy_CurrMb2[15:8] <= mvy; mvy_CurrMb2[31:24] <= mvy; end |
endcase |
3: //4x4 |
case (subMbPartIdx) |
0:mvy_CurrMb2[7:0] <= mvy; |
1:mvy_CurrMb2[15:8] <= mvy; |
2:mvy_CurrMb2[23:16] <= mvy; |
3:mvy_CurrMb2[31:24] <= mvy; |
endcase |
endcase |
3: |
case (sub_mb_type) |
0:mvy_CurrMb3 <= {mvy,mvy,mvy,mvy}; |
1: //8x4 |
case (subMbPartIdx) |
0:begin mvy_CurrMb3[7:0] <= mvy; mvy_CurrMb3[15:8] <= mvy; end |
1:begin mvy_CurrMb3[23:16] <= mvy; mvy_CurrMb3[31:24] <= mvy; end |
endcase |
2: //4x8 |
case (subMbPartIdx) |
0:begin mvy_CurrMb3[7:0] <= mvy; mvy_CurrMb3[23:16] <= mvy; end |
1:begin mvy_CurrMb3[15:8] <= mvy; mvy_CurrMb3[31:24] <= mvy; end |
endcase |
3: //4x4 |
case (subMbPartIdx) |
0:mvy_CurrMb3[7:0] <= mvy; |
1:mvy_CurrMb3[15:8] <= mvy; |
2:mvy_CurrMb3[23:16] <= mvy; |
3:mvy_CurrMb3[31:24] <= mvy; |
endcase |
endcase |
endcase |
//---------------------------- |
//mbAddrA write --> mvx_mbAddrA |
//---------------------------- |
always @ (posedge clk) |
if (reset_n == 0) |
mvx_mbAddrA <= 0; |
else if (mb_num_h != 10)//if mb_num_h == 10,mvx_mbAddrA will be no use |
begin |
//P_skip |
if (slice_data_state == `skip_run_duration && end_of_MB_DEC) |
mvx_mbAddrA <= {mvx_CurrMb0[7:0],mvx_CurrMb0[7:0],mvx_CurrMb0[7:0],mvx_CurrMb0[7:0]}; |
//Inter16x16 |
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 0) |
mvx_mbAddrA <= {mvx,mvx,mvx,mvx}; |
//Inter16x8 |
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 0) |
case (mbPartIdx) |
0:begin mvx_mbAddrA[15:8] <= mvx; mvx_mbAddrA[7:0] <= mvx; end |
1:begin mvx_mbAddrA[23:16] <= mvx; mvx_mbAddrA[31:24] <= mvx; end |
endcase |
//Inter8x16 |
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && mbPartIdx == 1 && compIdx == 0) |
mvx_mbAddrA <= {mvx,mvx,mvx,mvx}; |
//Inter8x8 |
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 0) |
case (mbPartIdx) |
1: |
case (sub_mb_type) |
0:begin mvx_mbAddrA[15:8] <= mvx; mvx_mbAddrA[7:0] <= mvx; end |
1:if (subMbPartIdx == 0) mvx_mbAddrA[7:0] <= mvx; |
else mvx_mbAddrA[15:8] <= mvx; |
2:if (subMbPartIdx == 1) begin mvx_mbAddrA[15:8] <= mvx; mvx_mbAddrA[7:0] <= mvx;end |
3:if (subMbPartIdx == 1) mvx_mbAddrA[7:0] <= mvx; |
else if (subMbPartIdx == 3) mvx_mbAddrA[15:8] <= mvx; |
endcase |
3: |
case (sub_mb_type) |
0:begin mvx_mbAddrA[23:16] <= mvx; mvx_mbAddrA[31:24] <= mvx; end |
1:if (subMbPartIdx == 0) mvx_mbAddrA[23:16] <= mvx; |
else mvx_mbAddrA[31:24] <= mvx; |
2:if (subMbPartIdx == 1) begin mvx_mbAddrA[23:16] <= mvx; mvx_mbAddrA[31:24] <= mvx;end |
3:if (subMbPartIdx == 1) mvx_mbAddrA[23:16] <= mvx; |
else if (subMbPartIdx == 3) mvx_mbAddrA[31:24] <= mvx; |
endcase |
endcase |
end |
always @ (posedge clk) |
if (reset_n == 0) |
mvy_mbAddrA <= 0; |
else if (mb_num_h != 10)//if mb_num_h == 10,mvy_mbAddrA will be no use |
begin |
//P_skip |
if (slice_data_state == `skip_run_duration && end_of_MB_DEC) |
mvy_mbAddrA <= {mvy_CurrMb0[7:0],mvy_CurrMb0[7:0],mvy_CurrMb0[7:0],mvy_CurrMb0[7:0]}; |
//Inter16x16 |
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 1) |
mvy_mbAddrA <= {mvy,mvy,mvy,mvy}; |
//Inter16x8 |
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 1) |
case (mbPartIdx) |
0:begin mvy_mbAddrA[15:8] <= mvy; mvy_mbAddrA[7:0] <= mvy; end |
1:begin mvy_mbAddrA[23:16] <= mvy; mvy_mbAddrA[31:24] <= mvy; end |
endcase |
//Inter8x16 |
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && mbPartIdx == 1 && compIdx == 1) |
mvy_mbAddrA <= {mvy,mvy,mvy,mvy}; |
//Inter8x8 |
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 1) |
case (mbPartIdx) |
1: |
case (sub_mb_type) |
0:begin mvy_mbAddrA[15:8] <= mvy; mvy_mbAddrA[7:0] <= mvy; end |
1:if (subMbPartIdx == 0) mvy_mbAddrA[7:0] <= mvy; |
else mvy_mbAddrA[15:8] <= mvy; |
2:if (subMbPartIdx == 1) begin mvy_mbAddrA[15:8] <= mvy; mvy_mbAddrA[7:0] <= mvy;end |
3:if (subMbPartIdx == 1) mvy_mbAddrA[7:0] <= mvy; |
else if (subMbPartIdx == 3) mvy_mbAddrA[15:8] <= mvy; |
endcase |
3: |
case (sub_mb_type) |
0:begin mvy_mbAddrA[23:16] <= mvy; mvy_mbAddrA[31:24] <= mvy; end |
1:if (subMbPartIdx == 0) mvy_mbAddrA[23:16] <= mvy; |
else mvy_mbAddrA[31:24] <= mvy; |
2:if (subMbPartIdx == 1) begin mvy_mbAddrA[23:16] <= mvy; mvy_mbAddrA[31:24] <= mvy;end |
3:if (subMbPartIdx == 1) mvy_mbAddrA[23:16] <= mvy; |
else if (subMbPartIdx == 3) mvy_mbAddrA[31:24] <= mvy; |
endcase |
endcase |
end |
//----------------------------------------- |
//mbAddrB RF read and write --> mvx_mbAddrB |
//----------------------------------------- |
always @ (reset_n or slice_data_state or mb_pred_state or sub_mb_pred_state or mv_mbAddrB_rd_for_DF |
or Is_skipMB_mv_calc or end_of_MB_DEC or mb_type_general or sub_mb_type or mb_num_h or mb_num_v |
or mbPartIdx or subMbPartIdx or compIdx or mvx or mvx_CurrMb0[7:0] or mvx_CurrMb2 or mvx_CurrMb3 |
or refIdxL0_A or refIdxL0_C) |
if (reset_n == 0) |
begin |
mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1; |
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0; |
mvx_mbAddrB_din <= 0; |
end |
//read for DF boundary strength decoding |
else if (mv_mbAddrB_rd_for_DF) |
begin |
mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_rd_addr <= mb_num_h; |
mvx_mbAddrB_wr_n <= 1; mvx_mbAddrB_wr_addr <= 0; |
mvx_mbAddrB_din <= 0; |
end |
//P_skip |
else if (slice_data_state == `skip_run_duration) |
begin |
if (Is_skipMB_mv_calc) //read |
begin |
if (mb_num_v == 0) |
begin mvx_mbAddrB_cs_n <= 1;mvx_mbAddrB_rd_addr <= 0; end |
else |
begin mvx_mbAddrB_cs_n <= 0;mvx_mbAddrB_rd_addr <= mb_num_h;end |
mvx_mbAddrB_wr_n <= 1; |
mvx_mbAddrB_wr_addr <= 0; |
mvx_mbAddrB_din <= 0; |
end |
else if (end_of_MB_DEC) //write |
begin |
if (mb_num_v == 8) |
begin |
mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1; |
mvx_mbAddrB_wr_addr <= 0; mvx_mbAddrB_din <= 0; |
end |
else |
begin |
mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 0; |
mvx_mbAddrB_wr_addr <= mb_num_h; |
mvx_mbAddrB_din <= {mvx_CurrMb0[7:0],mvx_CurrMb0[7:0],mvx_CurrMb0[7:0],mvx_CurrMb0[7:0]}; |
end |
mvx_mbAddrB_rd_addr <= 0; |
end |
else |
begin |
mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1; |
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0; |
mvx_mbAddrB_din <= 0; |
end |
end |
//Inter16x16 |
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 0) |
begin |
if (mb_num_v == 0) //!read,write |
begin |
mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 0; |
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= mb_num_h; |
mvx_mbAddrB_din <= {mvx,mvx,mvx,mvx}; |
end |
else if (mb_num_v == 8) //read,!write |
begin |
mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_rd_addr <= mb_num_h; |
mvx_mbAddrB_wr_n <= 1; mvx_mbAddrB_wr_addr <= 0; |
mvx_mbAddrB_din <= 0; |
end |
else //read,write |
begin |
mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_rd_addr <= mb_num_h; |
mvx_mbAddrB_wr_n <= 0; mvx_mbAddrB_wr_addr <= mb_num_h; |
mvx_mbAddrB_din <= {mvx,mvx,mvx,mvx}; |
end |
end |
//Inter16x8 |
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 0) |
case (mbPartIdx) |
0: //read,!write |
begin |
if (mb_num_v == 0) //!read,!write |
begin |
mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1; |
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0; |
mvx_mbAddrB_din <= 0; |
end |
else //read,!write |
begin |
mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 1; |
mvx_mbAddrB_rd_addr <= mb_num_h; mvx_mbAddrB_wr_addr <= 0; |
mvx_mbAddrB_din <= 0; |
end |
end |
1: //!read,write |
begin |
if (mb_num_v == 8) //!read,!write |
begin |
mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_rd_addr <= mb_num_h; |
mvx_mbAddrB_wr_n <= 1; mvx_mbAddrB_wr_addr <= 0; |
mvx_mbAddrB_din <= 0; |
end |
else //!read,write |
begin |
mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 0; |
mvx_mbAddrB_rd_addr <= mb_num_h; mvx_mbAddrB_wr_addr <= mb_num_h; |
mvx_mbAddrB_din <= {mvx,mvx,mvx,mvx}; |
end |
end |
default: |
begin |
mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1; |
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0; |
mvx_mbAddrB_din <= 0; |
end |
endcase |
//Inter8x16 |
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 0) |
case (mbPartIdx) |
0: //read when mbAddrA is not available for inter pred,!write |
if (refIdxL0_A == 1'b1) |
begin |
mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 1; |
mvx_mbAddrB_rd_addr <= mb_num_h;mvx_mbAddrB_wr_addr <= 0; |
mvx_mbAddrB_din <= 0; |
end |
else |
begin |
mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1; |
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0; |
mvx_mbAddrB_din <= 0; |
end |
1: //need read :mb_num_h == 10 && mb_num_v != 0 |
//need write:mb_num_v != 8 |
begin |
mvx_mbAddrB_cs_n <= ((mb_num_v != 8 || mb_num_h == 10) || (refIdxL0_C && mb_num_v != 0))? 1'b0:1'b1; |
mvx_mbAddrB_wr_n <= (mb_num_v == 8)? 1'b1:1'b0; |
mvx_mbAddrB_rd_addr <= mb_num_h; |
mvx_mbAddrB_wr_addr <= mb_num_h; |
mvx_mbAddrB_din <= {mvx_CurrMb2[23:16],mvx_CurrMb2[31:24],mvx,mvx}; |
end |
default: |
begin |
mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1; |
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0; |
mvx_mbAddrB_din <= 0; |
end |
endcase |
//8x8 |
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 0) |
case (mbPartIdx) |
0,1: //read,!write |
if (mb_num_v == 0) //!read,!write |
begin |
mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1; |
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0; |
mvx_mbAddrB_din <= 0; |
end |
else //read,!write |
begin |
mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 1; |
mvx_mbAddrB_rd_addr <= mb_num_h; mvx_mbAddrB_wr_addr <= 0; |
mvx_mbAddrB_din <= 0; |
end |
2: //!read,!write |
begin |
mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1; |
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0; |
mvx_mbAddrB_din <= 0; |
end |
3: //!read,write |
if (mb_num_v == 8) //!read,!write |
begin |
mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1; |
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0; |
mvx_mbAddrB_din <= 0; |
end |
else |
case (sub_mb_type) |
0: //8x8 |
begin |
mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 0; |
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= mb_num_h; |
mvx_mbAddrB_din <= {mvx_CurrMb2[23:16],mvx_CurrMb2[31:24],mvx,mvx}; |
end |
1: //8x4 |
case (subMbPartIdx) |
1: |
begin |
mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 0; |
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= mb_num_h; |
mvx_mbAddrB_din <= {mvx_CurrMb2[23:16],mvx_CurrMb2[31:24],mvx,mvx}; |
end |
default: |
begin |
mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1; |
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0; |
mvx_mbAddrB_din <= 0; |
end |
endcase |
2: //4x8 |
case (subMbPartIdx) |
1: |
begin |
mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 0; |
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= mb_num_h; |
mvx_mbAddrB_din <= {mvx_CurrMb2[23:16],mvx_CurrMb2[31:24],mvx_CurrMb3[23:16],mvx}; |
end |
default: |
begin |
mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1; |
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0; |
mvx_mbAddrB_din <= 0; |
end |
endcase |
3: //4x4 |
case (subMbPartIdx) |
3: |
begin |
mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 0; |
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= mb_num_h; |
mvx_mbAddrB_din <= {mvx_CurrMb2[23:16],mvx_CurrMb2[31:24], |
mvx_CurrMb3[23:16],mvx}; |
end |
default: |
begin |
mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1; |
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0; |
mvx_mbAddrB_din <= 0; |
end |
endcase |
endcase |
endcase |
else |
begin |
mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1; |
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0; |
mvx_mbAddrB_din <= 0; |
end |
|
always @ (reset_n or slice_data_state or mb_pred_state or sub_mb_pred_state or mv_mbAddrB_rd_for_DF |
or Is_skipMB_mv_calc or end_of_MB_DEC or mb_type_general or sub_mb_type or mb_num_h or mb_num_v |
or mbPartIdx or subMbPartIdx or compIdx or mvy or mvy_CurrMb0[7:0] or mvy_CurrMb2 or mvy_CurrMb3 |
or refIdxL0_A or refIdxL0_C) |
if (reset_n == 0) |
begin |
mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1; |
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0; |
mvy_mbAddrB_din <= 0; |
end |
//read for DF boundary strength decoding |
else if (mv_mbAddrB_rd_for_DF) |
begin |
mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_rd_addr <= mb_num_h; |
mvy_mbAddrB_wr_n <= 1; mvy_mbAddrB_wr_addr <= 0; |
mvy_mbAddrB_din <= 0; |
end |
//P_skip |
else if (slice_data_state == `skip_run_duration) |
begin |
if (Is_skipMB_mv_calc) //read |
begin |
if (mb_num_v == 0) |
begin mvy_mbAddrB_cs_n <= 1;mvy_mbAddrB_rd_addr <= 0; end |
else |
begin mvy_mbAddrB_cs_n <= 0;mvy_mbAddrB_rd_addr <= mb_num_h;end |
mvy_mbAddrB_wr_n <= 1; |
mvy_mbAddrB_wr_addr <= 0; |
mvy_mbAddrB_din <= 0; |
end |
else if (end_of_MB_DEC) //write |
begin |
if (mb_num_v == 8) |
begin |
mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1; |
mvy_mbAddrB_wr_addr <= 0; mvy_mbAddrB_din <= 0; |
end |
else |
begin |
mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 0; |
mvy_mbAddrB_wr_addr <= mb_num_h; |
mvy_mbAddrB_din <= {mvy_CurrMb0[7:0],mvy_CurrMb0[7:0],mvy_CurrMb0[7:0],mvy_CurrMb0[7:0]}; |
end |
mvy_mbAddrB_rd_addr <= 0; |
end |
else |
begin |
mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1; |
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0; |
mvy_mbAddrB_din <= 0; |
end |
end |
//Inter16x16 |
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 1) |
begin |
if (mb_num_v == 0) //!read,write |
begin |
mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 0; |
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= mb_num_h; |
mvy_mbAddrB_din <= {mvy,mvy,mvy,mvy}; |
end |
else if (mb_num_v == 8) //read,!write |
begin |
mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_rd_addr <= mb_num_h; |
mvy_mbAddrB_wr_n <= 1; mvy_mbAddrB_wr_addr <= 0; |
mvy_mbAddrB_din <= 0; |
end |
else //read,write |
begin |
mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_rd_addr <= mb_num_h; |
mvy_mbAddrB_wr_n <= 0; mvy_mbAddrB_wr_addr <= mb_num_h; |
mvy_mbAddrB_din <= {mvy,mvy,mvy,mvy}; |
end |
end |
//Inter16x8 |
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 1) |
case (mbPartIdx) |
0: //read,!write |
begin |
if (mb_num_v == 0) //!read,!write |
begin |
mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1; |
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0; |
mvy_mbAddrB_din <= 0; |
end |
else //read,!write |
begin |
mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 1; |
mvy_mbAddrB_rd_addr <= mb_num_h; mvy_mbAddrB_wr_addr <= 0; |
mvy_mbAddrB_din <= 0; |
end |
end |
1: //!read,write |
begin |
if (mb_num_v == 8) //!read,!write |
begin |
mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_rd_addr <= mb_num_h; |
mvy_mbAddrB_wr_n <= 1; mvy_mbAddrB_wr_addr <= 0; |
mvy_mbAddrB_din <= 0; |
end |
else //!read,write |
begin |
mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 0; |
mvy_mbAddrB_rd_addr <= mb_num_h; mvy_mbAddrB_wr_addr <= mb_num_h; |
mvy_mbAddrB_din <= {mvy,mvy,mvy,mvy}; |
end |
end |
default: |
begin |
mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1; |
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0; |
mvy_mbAddrB_din <= 0; |
end |
endcase |
//Inter8x16 |
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 1) |
case (mbPartIdx) |
0: //read when mbAddrA is not available for inter pred,!write |
if (refIdxL0_A == 1'b1) |
begin |
mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 1; |
mvy_mbAddrB_rd_addr <= mb_num_h;mvy_mbAddrB_wr_addr <= 0; |
mvy_mbAddrB_din <= 0; |
end |
else |
begin |
mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1; |
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0; |
mvy_mbAddrB_din <= 0; |
end |
1: //need read :mb_num_h == 10 && mb_num_v != 0 |
//need write:mb_num_v != 8 |
begin |
mvy_mbAddrB_cs_n <= ((mb_num_v != 8 || mb_num_h == 10) || (refIdxL0_C && mb_num_v != 0))? 1'b0:1'b1; |
mvy_mbAddrB_wr_n <= (mb_num_v == 8)? 1'b1:1'b0; |
mvy_mbAddrB_rd_addr <= mb_num_h; |
mvy_mbAddrB_wr_addr <= mb_num_h; |
mvy_mbAddrB_din <= {mvy_CurrMb2[23:16],mvy_CurrMb2[31:24],mvy,mvy}; |
end |
default: |
begin |
mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1; |
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0; |
mvy_mbAddrB_din <= 0; |
end |
endcase |
//8x8 |
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 1) |
case (mbPartIdx) |
0,1: //read,!write |
if (mb_num_v == 0) //!read,!write |
begin |
mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1; |
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0; |
mvy_mbAddrB_din <= 0; |
end |
else //read,!write |
begin |
mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 1; |
mvy_mbAddrB_rd_addr <= mb_num_h; mvy_mbAddrB_wr_addr <= 0; |
mvy_mbAddrB_din <= 0; |
end |
2: //!read,!write |
begin |
mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1; |
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0; |
mvy_mbAddrB_din <= 0; |
end |
3: //!read,write |
if (mb_num_v == 8) //!read,!write |
begin |
mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1; |
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0; |
mvy_mbAddrB_din <= 0; |
end |
else |
case (sub_mb_type) |
0: //8x8 |
begin |
mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 0; |
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= mb_num_h; |
mvy_mbAddrB_din <= {mvy_CurrMb2[23:16],mvy_CurrMb2[31:24],mvy,mvy}; |
end |
1: //8x4 |
case (subMbPartIdx) |
1: |
begin |
mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 0; |
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= mb_num_h; |
mvy_mbAddrB_din <= {mvy_CurrMb2[23:16],mvy_CurrMb2[31:24],mvy,mvy}; |
end |
default: |
begin |
mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1; |
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0; |
mvy_mbAddrB_din <= 0; |
end |
endcase |
2: //4x8 |
case (subMbPartIdx) |
1: |
begin |
mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 0; |
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= mb_num_h; |
mvy_mbAddrB_din <= {mvy_CurrMb2[23:16],mvy_CurrMb2[31:24],mvy_CurrMb3[23:16],mvy}; |
end |
default: |
begin |
mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1; |
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0; |
mvy_mbAddrB_din <= 0; |
end |
endcase |
3: //4x4 |
case (subMbPartIdx) |
3: |
begin |
mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 0; |
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= mb_num_h; |
mvy_mbAddrB_din <= {mvy_CurrMb2[23:16],mvy_CurrMb2[31:24], |
mvy_CurrMb3[23:16],mvy}; |
end |
default: |
begin |
mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1; |
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0; |
mvy_mbAddrB_din <= 0; |
end |
endcase |
endcase |
endcase |
else |
begin |
mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1; |
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0; |
mvy_mbAddrB_din <= 0; |
end |
//----------------------------------------- |
//mbAddrC RF read and write --> mvx_mbAddrC |
//----------------------------------------- |
always @ (reset_n or slice_data_state or Is_skipMB_mv_calc or end_of_MB_DEC or mb_pred_state or sub_mb_type or sub_mb_pred_state |
or mb_type_general or mb_num or mb_num_h or mb_num_v or mbPartIdx or subMbPartIdx or compIdx or mvx or mvx_CurrMb0[7:0] |
or refIdxL0_B or refIdxL0_C) |
if (reset_n == 0) |
begin |
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1; |
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0; |
mvx_mbAddrC_din <= 0; |
end |
//P_skip |
else if (slice_data_state == `skip_run_duration) |
begin |
if (Is_skipMB_mv_calc) //read |
begin |
if (mb_num_v == 0 || mb_num_h == 10)//!read,!write |
begin mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_rd_addr <= 0; end |
else |
begin mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_rd_addr <= mb_num_h; end |
mvx_mbAddrC_wr_n <= 1; |
mvx_mbAddrC_wr_addr <= 0; |
mvx_mbAddrC_din <= 0; |
end |
else if (end_of_MB_DEC) //write |
begin |
if (mb_num_v == 8 || mb_num_h == 0) //!write |
begin |
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1; |
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0; |
mvx_mbAddrC_din <= 0; |
end |
else //write |
begin |
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 0; |
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= mb_num_h - 1; |
mvx_mbAddrC_din <= mvx_CurrMb0[7:0]; |
end |
end |
else |
begin |
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1; |
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0; |
mvx_mbAddrC_din <= 0; |
end |
end |
//Inter16x16 |
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 0) |
begin |
if (mb_num == 0)//!read,!write |
begin |
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1; |
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0; |
mvx_mbAddrC_din <= 0; |
end |
else if (mb_num_v == 0)//!read,write |
begin |
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 0; |
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= mb_num_h - 1; |
mvx_mbAddrC_din <= mvx; |
end |
else if (mb_num_h == 0 || mb_num_v == 8) //read,!write |
begin |
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 1; |
mvx_mbAddrC_rd_addr <= mb_num_h; mvx_mbAddrC_wr_addr <= 0; |
mvx_mbAddrC_din <= 0; |
end |
else //read,write |
begin |
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 0; |
mvx_mbAddrC_rd_addr <= mb_num_h; mvx_mbAddrC_wr_addr <= mb_num_h - 1; |
mvx_mbAddrC_din <= mvx; |
end |
end |
//Inter16x8 |
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 0) |
begin |
if (mbPartIdx == 0) //upper blk,may read,no write |
begin |
if (refIdxL0_B && !refIdxL0_C) //read,!write |
begin |
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 1; |
mvx_mbAddrC_rd_addr <= mb_num_h; mvx_mbAddrC_wr_addr <= 0; |
mvx_mbAddrC_din <= 0; |
end |
else //!read,!write |
begin |
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1; |
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0; |
mvx_mbAddrC_din <= 0; |
end |
end |
else //bottom blk,may write,no read |
begin |
if (mb_num_h != 0) //!read,write |
begin |
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 0; |
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= mb_num_h - 1; |
mvx_mbAddrC_din <= mvx; |
end |
else //!read,!write |
begin |
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1; |
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0; |
mvx_mbAddrC_din <= 0; |
end |
end |
end |
//Inter8x16 |
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 0) |
case (mbPartIdx) |
0: //!read,write |
if (mb_num_v == 8) |
begin |
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1; |
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0; |
mvx_mbAddrC_din <= 0; |
end |
else |
begin |
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 0; |
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= mb_num_h - 1; |
mvx_mbAddrC_din <= mvx; |
end |
default: //read,!write |
begin |
if (mb_num_v == 0 || mb_num_h == 10) //!read,!write |
begin |
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1; |
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0; |
mvx_mbAddrC_din <= 0; |
end |
else //read,!write |
begin |
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 1; |
mvx_mbAddrC_rd_addr <= mb_num_h; mvx_mbAddrC_wr_addr <= 0; |
mvx_mbAddrC_din <= 0; |
end |
end |
endcase |
//Inter8x8 |
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 0) |
case (mbPartIdx) |
1: //read,!write |
if (mb_num_v == 0 || mb_num_h == 10) //!read,!write |
begin |
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1; |
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0; |
mvx_mbAddrC_din <= 0; |
end |
else //read,!write |
case (sub_mb_type) |
0: //8x8 |
begin |
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 1; |
mvx_mbAddrC_rd_addr <= mb_num_h; mvx_mbAddrC_wr_addr <= 0; |
mvx_mbAddrC_din <= mvx; |
end |
1: //8x4 |
case (subMbPartIdx) |
0: //read,!write |
begin |
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 1; |
mvx_mbAddrC_rd_addr <= mb_num_h; mvx_mbAddrC_wr_addr <= 0; |
mvx_mbAddrC_din <= mvx; |
end |
default: //!read,!write |
begin |
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1; |
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0; |
mvx_mbAddrC_din <= 0; |
end |
endcase |
2: //4x8 |
case (subMbPartIdx) |
1: //read,!write |
begin |
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 1; |
mvx_mbAddrC_rd_addr <= mb_num_h; mvx_mbAddrC_wr_addr <= 0; |
mvx_mbAddrC_din <= mvx; |
end |
default: //!read,!write |
begin |
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1; |
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0; |
mvx_mbAddrC_din <= 0; |
end |
endcase |
3: //4x4 |
case (subMbPartIdx) |
1: //read,!write |
begin |
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 1; |
mvx_mbAddrC_rd_addr <= mb_num_h; mvx_mbAddrC_wr_addr <= 0; |
mvx_mbAddrC_din <= mvx; |
end |
default: //!read,!write |
begin |
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1; |
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0; |
mvx_mbAddrC_din <= 0; |
end |
endcase |
endcase |
2: //!read,write |
if (mb_num_h == 0 || mb_num_v == 8) //!read,!write |
begin |
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1; |
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0; |
mvx_mbAddrC_din <= 0; |
end |
else //!read,write |
case (sub_mb_type) |
0: //8x8 |
begin |
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 0; |
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= mb_num_h - 1; |
mvx_mbAddrC_din <= mvx; |
end |
1: //8x4 |
case (subMbPartIdx) |
1: //!read,write |
begin |
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 0; |
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= mb_num_h - 1; |
mvx_mbAddrC_din <= mvx; |
end |
default: //!read,!write |
begin |
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1; |
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0; |
mvx_mbAddrC_din <= 0; |
end |
endcase |
2: //4x8 |
case (subMbPartIdx) |
0: //!read,write |
begin |
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 0; |
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= mb_num_h - 1; |
mvx_mbAddrC_din <= mvx; |
end |
default: //!read,!write |
begin |
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1; |
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0; |
mvx_mbAddrC_din <= 0; |
end |
endcase |
3: //4x4 |
case (subMbPartIdx) |
2: //!read,write |
begin |
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 0; |
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= mb_num_h - 1; |
mvx_mbAddrC_din <= mvx; |
end |
default: //!read,!write |
begin |
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1; |
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0; |
mvx_mbAddrC_din <= 0; |
end |
endcase |
endcase |
default: |
begin |
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1; |
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0; |
mvx_mbAddrC_din <= 0; |
end |
endcase |
else |
begin |
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1; |
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0; |
mvx_mbAddrC_din <= 0; |
end |
|
always @ (reset_n or slice_data_state or Is_skipMB_mv_calc or end_of_MB_DEC or mb_pred_state or sub_mb_type or sub_mb_pred_state |
or mb_type_general or mb_num or mb_num_h or mb_num_v or mbPartIdx or subMbPartIdx or compIdx or mvy or mvy_CurrMb0[7:0] |
or refIdxL0_B or refIdxL0_C) |
if (reset_n == 0) |
begin |
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1; |
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0; |
mvy_mbAddrC_din <= 0; |
end |
//P_skip |
else if (slice_data_state == `skip_run_duration) |
begin |
if (Is_skipMB_mv_calc) //read |
begin |
if (mb_num_v == 0 || mb_num_h == 10)//!read,!write |
begin mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_rd_addr <= 0; end |
else |
begin mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_rd_addr <= mb_num_h; end |
mvy_mbAddrC_wr_n <= 1; |
mvy_mbAddrC_wr_addr <= 0; |
mvy_mbAddrC_din <= 0; |
end |
else if (end_of_MB_DEC) //write |
begin |
if (mb_num_v == 8 || mb_num_h == 0) //!write |
begin |
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1; |
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0; |
mvy_mbAddrC_din <= 0; |
end |
else //write |
begin |
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 0; |
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= mb_num_h - 1; |
mvy_mbAddrC_din <= mvy_CurrMb0[7:0]; |
end |
end |
else |
begin |
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1; |
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0; |
mvy_mbAddrC_din <= 0; |
end |
end |
//Inter16x16 |
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 1) |
begin |
if (mb_num == 0)//!read,!write |
begin |
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1; |
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0; |
mvy_mbAddrC_din <= 0; |
end |
else if (mb_num_v == 0)//!read,write |
begin |
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 0; |
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= mb_num_h - 1; |
mvy_mbAddrC_din <= mvy; |
end |
else if (mb_num_h == 0 || mb_num_v == 8) //read,!write |
begin |
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 1; |
mvy_mbAddrC_rd_addr <= mb_num_h; mvy_mbAddrC_wr_addr <= 0; |
mvy_mbAddrC_din <= 0; |
end |
else //read,write |
begin |
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 0; |
mvy_mbAddrC_rd_addr <= mb_num_h; mvy_mbAddrC_wr_addr <= mb_num_h - 1; |
mvy_mbAddrC_din <= mvy; |
end |
end |
//Inter16x8 |
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 1) |
begin |
if (mbPartIdx == 0) //upper blk,may read,no write |
begin |
if (refIdxL0_B && !refIdxL0_C) //read,!write |
begin |
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 1; |
mvy_mbAddrC_rd_addr <= mb_num_h; mvy_mbAddrC_wr_addr <= 0; |
mvy_mbAddrC_din <= 0; |
end |
else //!read,!write |
begin |
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1; |
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0; |
mvy_mbAddrC_din <= 0; |
end |
end |
else //bottom blk,may write,no read |
begin |
if (mb_num_h != 0) //!read,write |
begin |
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 0; |
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= mb_num_h - 1; |
mvy_mbAddrC_din <= mvy; |
end |
else //!read,!write |
begin |
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1; |
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0; |
mvy_mbAddrC_din <= 0; |
end |
end |
end |
//Inter8x16 |
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 1) |
case (mbPartIdx) |
0: //!read,write |
if (mb_num_v == 8) |
begin |
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1; |
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0; |
mvy_mbAddrC_din <= 0; |
end |
else |
begin |
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 0; |
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= mb_num_h - 1; |
mvy_mbAddrC_din <= mvy; |
end |
default: //read,!write |
begin |
if (mb_num_v == 0 || mb_num_h == 10) //!read,!write |
begin |
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1; |
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0; |
mvy_mbAddrC_din <= 0; |
end |
else //read,!write |
begin |
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 1; |
mvy_mbAddrC_rd_addr <= mb_num_h; mvy_mbAddrC_wr_addr <= 0; |
mvy_mbAddrC_din <= 0; |
end |
end |
endcase |
//Inter8x8 |
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 1) |
case (mbPartIdx) |
1: //read,!write |
if (mb_num_v == 0 || mb_num_h == 10) //!read,!write |
begin |
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1; |
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0; |
mvy_mbAddrC_din <= 0; |
end |
else //read,!write |
case (sub_mb_type) |
0: //8x8 |
begin |
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 1; |
mvy_mbAddrC_rd_addr <= mb_num_h; mvy_mbAddrC_wr_addr <= 0; |
mvy_mbAddrC_din <= mvy; |
end |
1: //8x4 |
case (subMbPartIdx) |
0: //read,!write |
begin |
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 1; |
mvy_mbAddrC_rd_addr <= mb_num_h; mvy_mbAddrC_wr_addr <= 0; |
mvy_mbAddrC_din <= mvy; |
end |
default: //!read,!write |
begin |
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1; |
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0; |
mvy_mbAddrC_din <= 0; |
end |
endcase |
2: //4x8 |
case (subMbPartIdx) |
1: //read,!write |
begin |
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 1; |
mvy_mbAddrC_rd_addr <= mb_num_h; mvy_mbAddrC_wr_addr <= 0; |
mvy_mbAddrC_din <= mvy; |
end |
default: //!read,!write |
begin |
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1; |
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0; |
mvy_mbAddrC_din <= 0; |
end |
endcase |
3: //4x4 |
case (subMbPartIdx) |
1: //read,!write |
begin |
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 1; |
mvy_mbAddrC_rd_addr <= mb_num_h; mvy_mbAddrC_wr_addr <= 0; |
mvy_mbAddrC_din <= mvy; |
end |
default: //!read,!write |
begin |
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1; |
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0; |
mvy_mbAddrC_din <= 0; |
end |
endcase |
endcase |
2: //!read,write |
if (mb_num_h == 0 || mb_num_v == 8) //!read,!write |
begin |
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1; |
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0; |
mvy_mbAddrC_din <= 0; |
end |
else //!read,write |
case (sub_mb_type) |
0: //8x8 |
begin |
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 0; |
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= mb_num_h - 1; |
mvy_mbAddrC_din <= mvy; |
end |
1: //8x4 |
case (subMbPartIdx) |
1: //!read,write |
begin |
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 0; |
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= mb_num_h - 1; |
mvy_mbAddrC_din <= mvy; |
end |
default: //!read,!write |
begin |
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1; |
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0; |
mvy_mbAddrC_din <= 0; |
end |
endcase |
2: //4x8 |
case (subMbPartIdx) |
0: //!read,write |
begin |
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 0; |
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= mb_num_h - 1; |
mvy_mbAddrC_din <= mvy; |
end |
default: //!read,!write |
begin |
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1; |
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0; |
mvy_mbAddrC_din <= 0; |
end |
endcase |
3: //4x4 |
case (subMbPartIdx) |
2: //!read,write |
begin |
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 0; |
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= mb_num_h - 1; |
mvy_mbAddrC_din <= mvy; |
end |
default: //!read,!write |
begin |
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1; |
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0; |
mvy_mbAddrC_din <= 0; |
end |
endcase |
endcase |
default: |
begin |
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1; |
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0; |
mvy_mbAddrC_din <= 0; |
end |
endcase |
else |
begin |
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1; |
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0; |
mvy_mbAddrC_din <= 0; |
end |
|
//------------------------------- |
//mbAddrD write --> mvx_mbAddrD |
//------------------------------- |
//mvx_mbAddrD |
reg [7:0] mvx_mbAddrD_subMB; |
reg [7:0] mvx_mbAddrD_MB,mvx_mbAddrD_MB_tmp; |
always @ (posedge clk) |
if (reset_n == 0) |
mvx_mbAddrD_subMB <= 0; |
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 0) |
case (mbPartIdx) |
0:if (sub_mb_type == 1 && subMbPartIdx == 0) //8x4 UpperBlk |
mvx_mbAddrD_subMB <= mvx_mbAddrA[7:0]; |
2:if (sub_mb_type == 1 && subMbPartIdx == 0) //8x4 UpperBlk |
mvx_mbAddrD_subMB <= mvx_mbAddrA[23:16]; |
endcase |
|
always @ (posedge clk) |
if (reset_n == 1'b0) |
mvx_mbAddrD_MB_tmp <= 0; |
else if (end_of_MB_DEC && mb_num_v != 8 && mb_num_h == 9 && mb_type_general[3] == 0) |
mvx_mbAddrD_MB_tmp <= (mv_is16x16)? mvx_CurrMb0[7:0]:mvx_CurrMb3[31:24]; |
|
always @ (posedge clk) |
if (reset_n == 1'b0) |
mvx_mbAddrD_MB <= 0; |
else if (end_of_MB_DEC && mb_num_h == 10) |
mvx_mbAddrD_MB <= mvx_mbAddrD_MB_tmp; |
|
assign mvx_mbAddrD = ((mbPartIdx == 0 || mbPartIdx == 2) && sub_mb_type == 1 && subMbPartIdx == 1)? mvx_mbAddrD_subMB:mvx_mbAddrD_MB; |
|
//mvy_mbAddrD |
reg [7:0] mvy_mbAddrD_subMB; |
reg [7:0] mvy_mbAddrD_MB,mvy_mbAddrD_MB_tmp; |
always @ (posedge clk) |
if (reset_n == 0) |
mvy_mbAddrD_subMB <= 0; |
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 0) |
case (mbPartIdx) |
0:if (sub_mb_type == 1 && subMbPartIdx == 0) //8x4 UpperBlk |
mvy_mbAddrD_subMB <= mvy_mbAddrA[7:0]; |
2:if (sub_mb_type == 1 && subMbPartIdx == 0) //8x4 UpperBlk |
mvy_mbAddrD_subMB <= mvy_mbAddrA[23:16]; |
endcase |
|
always @ (posedge clk) |
if (reset_n == 1'b0) |
mvy_mbAddrD_MB_tmp <= 0; |
else if (end_of_MB_DEC && mb_num_v != 8 && mb_num_h == 9 && mb_type_general[3] == 0) |
mvy_mbAddrD_MB_tmp <= (mv_is16x16)? mvy_CurrMb0[7:0]:mvy_CurrMb3[31:24]; |
|
always @ (posedge clk) |
if (reset_n == 1'b0) |
mvy_mbAddrD_MB <= 0; |
else if (end_of_MB_DEC && mb_num_h == 10) |
mvy_mbAddrD_MB <= mvy_mbAddrD_MB_tmp; |
|
assign mvy_mbAddrD = ((mbPartIdx == 0 || mbPartIdx == 2) && sub_mb_type == 1 && subMbPartIdx == 1)? mvy_mbAddrD_subMB:mvy_mbAddrD_MB; |
|
endmodule |
/trunk/src/Inter_pred_pipeline.v
0,0 → 1,782
//-------------------------------------------------------------------------------------------------- |
// Design : nova |
// Author(s) : Ke Xu |
// Email : eexuke@yahoo.com |
// File : Inter_pred_pipeline.v |
// Generated : Oct 4, 2005 |
// Copyright (C) 2008 Ke Xu |
//------------------------------------------------------------------------------------------------- |
// Description |
// Inter prediction pipeline |
//------------------------------------------------------------------------------------------------- |
// Revise log |
// 1.July 23,2006 |
// Change the ext_frame_RAM from async read to sync read.Therefore,blk4x4_inter_preload_counter has to +1 for all the cases |
//------------------------------------------------------------------------------------------------- |
|
// synopsys translate_off |
`include "timescale.v" |
// synopsys translate_on |
`include "nova_defines.v" |
|
module Inter_pred_pipeline (clk,reset_n, |
mb_num_h,mb_num_v,trigger_blk4x4_inter_pred,blk4x4_rec_counter,mb_type_general_bit3, |
mv_is16x16,mv_below8x8, |
mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3, |
mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3, |
Inter_pix_copy0,Inter_pix_copy1,Inter_pix_copy2,Inter_pix_copy3, |
LPE0_out,LPE1_out,LPE2_out,LPE3_out, |
CPE0_out,CPE1_out,CPE2_out,CPE3_out, |
|
mv_below8x8_curr,blk4x4_inter_preload_counter,blk4x4_inter_calculate_counter,Inter_chroma2x2_counter, |
end_of_one_blk4x4_inter,IsInterLuma,IsInterChroma,Is_InterChromaCopy, |
xInt_addr_unclip,xInt_org_unclip_1to0,pos_FracL,xFracC,yFracC, |
Inter_pred_out0,Inter_pred_out1,Inter_pred_out2,Inter_pred_out3,Inter_blk4x4_pred_output_valid, |
ref_frame_RAM_rd,ref_frame_RAM_rd_addr); |
input clk; |
input reset_n; |
input [3:0] mb_num_h,mb_num_v; |
input trigger_blk4x4_inter_pred; |
input [4:0] blk4x4_rec_counter; |
input mb_type_general_bit3; |
input mv_is16x16; |
input [3:0] mv_below8x8; |
input [31:0] mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3; |
input [31:0] mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3; |
input [7:0] Inter_pix_copy0,Inter_pix_copy1,Inter_pix_copy2,Inter_pix_copy3; |
input [7:0] LPE0_out,LPE1_out,LPE2_out,LPE3_out; |
input [7:0] CPE0_out,CPE1_out,CPE2_out,CPE3_out; |
|
output mv_below8x8_curr; |
output [5:0] blk4x4_inter_preload_counter; |
output [3:0] blk4x4_inter_calculate_counter; |
output [1:0] Inter_chroma2x2_counter; |
output end_of_one_blk4x4_inter; |
output IsInterLuma,IsInterChroma; |
output Is_InterChromaCopy; |
output [8:0] xInt_addr_unclip; |
output [1:0] xInt_org_unclip_1to0; |
output [3:0] pos_FracL; |
output [2:0] xFracC,yFracC; |
output [7:0] Inter_pred_out0,Inter_pred_out1,Inter_pred_out2,Inter_pred_out3; |
output [1:0] Inter_blk4x4_pred_output_valid; //2'b01:luma output valid 2'b10:chroma output valid |
output ref_frame_RAM_rd; |
output [13:0] ref_frame_RAM_rd_addr; |
|
reg [5:0] blk4x4_inter_preload_counter; |
reg [3:0] blk4x4_inter_calculate_counter; |
reg mv_below8x8_curr; |
reg [7:0] Inter_pred_out0,Inter_pred_out1,Inter_pred_out2,Inter_pred_out3; |
reg [1:0] Inter_blk4x4_pred_output_valid; |
wire ref_frame_RAM_rd; |
wire IsInterLuma; |
wire IsInterChroma; |
wire [1:0] xFracL; |
wire [1:0] yFracL; |
wire [2:0] xFracC; |
wire [2:0] yFracC; |
wire [13:0] ref_frame_RAM_rd_addr; |
|
assign IsInterLuma = (!mb_type_general_bit3 && blk4x4_rec_counter < 16)? 1'b1:1'b0; |
assign IsInterChroma = (!mb_type_general_bit3 && blk4x4_rec_counter > 15)? 1'b1:1'b0; |
//------------------------------------------------------------------------- |
//mv_below8x8_curr for each 2x2 Inter Chroma prediction |
//------------------------------------------------------------------------- |
always @ (IsInterLuma or IsInterChroma or blk4x4_rec_counter[3:0] or mv_below8x8) |
if (IsInterLuma) |
case (blk4x4_rec_counter[3:2]) |
2'b00:mv_below8x8_curr <= mv_below8x8[0]; |
2'b01:mv_below8x8_curr <= mv_below8x8[1]; |
2'b10:mv_below8x8_curr <= mv_below8x8[2]; |
2'b11:mv_below8x8_curr <= mv_below8x8[3]; |
endcase |
else if (IsInterChroma) |
case (blk4x4_rec_counter[1:0]) |
2'b00:mv_below8x8_curr <= mv_below8x8[0]; |
2'b01:mv_below8x8_curr <= mv_below8x8[1]; |
2'b10:mv_below8x8_curr <= mv_below8x8[2]; |
2'b11:mv_below8x8_curr <= mv_below8x8[3]; |
endcase |
else |
mv_below8x8_curr <= 0; |
//---------------------------------------------------------------------------------------- |
//Inter_chroma2x2_counter to guide the prediction of 2x2 chroma blocks |
//2'b11 -> 2'b10 -> 2'b01 -> 2'b00 |
//---------------------------------------------------------------------------------------- |
reg [1:0] Inter_chroma2x2_counter; |
always @ (posedge clk) |
if (reset_n == 1'b0) |
Inter_chroma2x2_counter <= 0; |
//mv_below8x8_curr == 1'b1 includes the condition that "blk4x4_rec_counter > 15" |
else if (IsInterChroma && trigger_blk4x4_inter_pred && mv_below8x8_curr) |
Inter_chroma2x2_counter <= 2'b11; |
else if (blk4x4_inter_calculate_counter == 4'd1 && Inter_chroma2x2_counter != 0) |
Inter_chroma2x2_counter <= Inter_chroma2x2_counter - 1; |
|
//---------------------------------------------------------------------------------------- |
//trigger_blk2x2_inter_pred:only for chroma 2x2 decoding |
//We introduce this additional signal since we need Inter_chroma2x2_counter to update |
//one cycle before blk4x4_inter_calculate_counter |
//---------------------------------------------------------------------------------------- |
reg trigger_blk2x2_inter_pred; |
always @ (posedge clk) |
if (reset_n == 1'b0) |
trigger_blk2x2_inter_pred <= 0; |
else if ((IsInterChroma && trigger_blk4x4_inter_pred && mv_below8x8_curr) || |
(blk4x4_inter_calculate_counter == 4'd1 && Inter_chroma2x2_counter != 0)) |
trigger_blk2x2_inter_pred <= 1'b1; |
else |
trigger_blk2x2_inter_pred <= 1'b0; |
//---------------------------------------------------------------------------------------- |
//Inter motion vector for current 4x4 luma/chroma block or 2x2 chroma block |
// Inter_blk_mvx,Inter_blk_mvy |
//---------------------------------------------------------------------------------------- |
reg [7:0] Inter_blk_mvx,Inter_blk_mvy; |
always @ (blk4x4_rec_counter or mv_below8x8_curr or Inter_chroma2x2_counter |
or IsInterLuma or IsInterChroma or mv_is16x16 |
or mvx_CurrMb0 or mvx_CurrMb1 or mvx_CurrMb2 or mvx_CurrMb3 |
or mvy_CurrMb0 or mvy_CurrMb1 or mvy_CurrMb2 or mvy_CurrMb3) |
//Inter luma |
if (IsInterLuma) |
begin |
if (mv_is16x16) |
begin Inter_blk_mvx <= mvx_CurrMb0[7:0]; Inter_blk_mvy <= mvy_CurrMb0[7:0]; end |
else |
case (mv_below8x8_curr) |
1'b0: |
case (blk4x4_rec_counter[3:2]) |
2'b00:begin Inter_blk_mvx <= mvx_CurrMb0[7:0]; Inter_blk_mvy <= mvy_CurrMb0[7:0]; end |
2'b01:begin Inter_blk_mvx <= mvx_CurrMb1[7:0]; Inter_blk_mvy <= mvy_CurrMb1[7:0]; end |
2'b10:begin Inter_blk_mvx <= mvx_CurrMb2[7:0]; Inter_blk_mvy <= mvy_CurrMb2[7:0]; end |
2'b11:begin Inter_blk_mvx <= mvx_CurrMb3[7:0]; Inter_blk_mvy <= mvy_CurrMb3[7:0]; end |
endcase |
1'b1: |
case (blk4x4_rec_counter) |
0 :begin Inter_blk_mvx <= mvx_CurrMb0[7:0]; Inter_blk_mvy <= mvy_CurrMb0[7:0]; end |
1 :begin Inter_blk_mvx <= mvx_CurrMb0[15:8]; Inter_blk_mvy <= mvy_CurrMb0[15:8]; end |
2 :begin Inter_blk_mvx <= mvx_CurrMb0[23:16];Inter_blk_mvy <= mvy_CurrMb0[23:16]; end |
3 :begin Inter_blk_mvx <= mvx_CurrMb0[31:24];Inter_blk_mvy <= mvy_CurrMb0[31:24]; end |
4 :begin Inter_blk_mvx <= mvx_CurrMb1[7:0]; Inter_blk_mvy <= mvy_CurrMb1[7:0]; end |
5 :begin Inter_blk_mvx <= mvx_CurrMb1[15:8]; Inter_blk_mvy <= mvy_CurrMb1[15:8]; end |
6 :begin Inter_blk_mvx <= mvx_CurrMb1[23:16];Inter_blk_mvy <= mvy_CurrMb1[23:16]; end |
7 :begin Inter_blk_mvx <= mvx_CurrMb1[31:24];Inter_blk_mvy <= mvy_CurrMb1[31:24]; end |
8 :begin Inter_blk_mvx <= mvx_CurrMb2[7:0]; Inter_blk_mvy <= mvy_CurrMb2[7:0]; end |
9 :begin Inter_blk_mvx <= mvx_CurrMb2[15:8]; Inter_blk_mvy <= mvy_CurrMb2[15:8]; end |
10:begin Inter_blk_mvx <= mvx_CurrMb2[23:16];Inter_blk_mvy <= mvy_CurrMb2[23:16]; end |
11:begin Inter_blk_mvx <= mvx_CurrMb2[31:24];Inter_blk_mvy <= mvy_CurrMb2[31:24]; end |
12:begin Inter_blk_mvx <= mvx_CurrMb3[7:0]; Inter_blk_mvy <= mvy_CurrMb3[7:0]; end |
13:begin Inter_blk_mvx <= mvx_CurrMb3[15:8]; Inter_blk_mvy <= mvy_CurrMb3[15:8]; end |
14:begin Inter_blk_mvx <= mvx_CurrMb3[23:16];Inter_blk_mvy <= mvy_CurrMb3[23:16]; end |
15:begin Inter_blk_mvx <= mvx_CurrMb3[31:24];Inter_blk_mvy <= mvy_CurrMb3[31:24]; end |
default:begin Inter_blk_mvx <= 0;Inter_blk_mvy <= 0; end |
endcase |
endcase |
end |
//Inter chroma |
else if (IsInterChroma) |
begin |
if (mv_is16x16) |
begin Inter_blk_mvx <= mvx_CurrMb0[7:0]; Inter_blk_mvy <= mvy_CurrMb0[7:0]; end |
else |
case (blk4x4_rec_counter[1:0]) |
2'b00: |
if (mv_below8x8_curr) //chroma2x2 prediction |
case (Inter_chroma2x2_counter) |
3:begin Inter_blk_mvx <= mvx_CurrMb0[7:0]; Inter_blk_mvy <= mvy_CurrMb0[7:0]; end |
2:begin Inter_blk_mvx <= mvx_CurrMb0[15:8]; Inter_blk_mvy <= mvy_CurrMb0[15:8]; end |
1:begin Inter_blk_mvx <= mvx_CurrMb0[23:16];Inter_blk_mvy <= mvy_CurrMb0[23:16]; end |
0:begin Inter_blk_mvx <= mvx_CurrMb0[31:24];Inter_blk_mvy <= mvy_CurrMb0[31:24]; end |
endcase |
else //chroma 4x4 prediction |
begin Inter_blk_mvx <= mvx_CurrMb0[7:0]; Inter_blk_mvy <= mvy_CurrMb0[7:0]; end |
2'b01: |
if (mv_below8x8_curr) //need chroma2x2 prediction |
case (Inter_chroma2x2_counter) |
3:begin Inter_blk_mvx <= mvx_CurrMb1[7:0]; Inter_blk_mvy <= mvy_CurrMb1[7:0]; end |
2:begin Inter_blk_mvx <= mvx_CurrMb1[15:8]; Inter_blk_mvy <= mvy_CurrMb1[15:8]; end |
1:begin Inter_blk_mvx <= mvx_CurrMb1[23:16];Inter_blk_mvy <= mvy_CurrMb1[23:16]; end |
0:begin Inter_blk_mvx <= mvx_CurrMb1[31:24];Inter_blk_mvy <= mvy_CurrMb1[31:24]; end |
endcase |
else //chroma 4x4 prediction |
begin Inter_blk_mvx <= mvx_CurrMb1[7:0]; Inter_blk_mvy <= mvy_CurrMb1[7:0]; end |
2'b10: |
if (mv_below8x8_curr) //chroma2x2 prediction |
case (Inter_chroma2x2_counter) |
3:begin Inter_blk_mvx <= mvx_CurrMb2[7:0]; Inter_blk_mvy <= mvy_CurrMb2[7:0]; end |
2:begin Inter_blk_mvx <= mvx_CurrMb2[15:8]; Inter_blk_mvy <= mvy_CurrMb2[15:8]; end |
1:begin Inter_blk_mvx <= mvx_CurrMb2[23:16];Inter_blk_mvy <= mvy_CurrMb2[23:16]; end |
0:begin Inter_blk_mvx <= mvx_CurrMb2[31:24];Inter_blk_mvy <= mvy_CurrMb2[31:24]; end |
endcase |
else //chroma 4x4 prediction |
begin Inter_blk_mvx <= mvx_CurrMb2[7:0]; Inter_blk_mvy <= mvy_CurrMb2[7:0]; end |
2'b11: |
if (mv_below8x8_curr) //chroma2x2 prediction |
case (Inter_chroma2x2_counter) |
3:begin Inter_blk_mvx <= mvx_CurrMb3[7:0]; Inter_blk_mvy <= mvy_CurrMb3[7:0]; end |
2:begin Inter_blk_mvx <= mvx_CurrMb3[15:8]; Inter_blk_mvy <= mvy_CurrMb3[15:8]; end |
1:begin Inter_blk_mvx <= mvx_CurrMb3[23:16];Inter_blk_mvy <= mvy_CurrMb3[23:16]; end |
0:begin Inter_blk_mvx <= mvx_CurrMb3[31:24];Inter_blk_mvy <= mvy_CurrMb3[31:24]; end |
endcase |
else //chroma 4x4 prediction |
begin Inter_blk_mvx <= mvx_CurrMb3[7:0]; Inter_blk_mvy <= mvy_CurrMb3[7:0]; end |
endcase |
end |
else |
begin Inter_blk_mvx <= 0; Inter_blk_mvy <= 0; end |
//---------------------------------------------------------------------------------------- |
//Describes the offset of each blk4x4 inside a MB |
//---------------------------------------------------------------------------------------- |
// xOffset = 0 for 0,2,8, 10 yOffset = 0 for 0, 1, 4, 5 |
// xOffset = 4 for 1,3,9, 11 yOffset = 4 for 2, 3, 6, 7 |
// xOffset = 8 for 4,6,12,14 yOffset = 8 for 8, 9, 12,13 |
// xOffset = 12 for 5,7,13,15 yOffset = 12 for 10,11,14,15 |
reg [3:0] xOffsetL,yOffsetL; |
always @ (IsInterLuma or mv_below8x8_curr or blk4x4_rec_counter[2] or blk4x4_rec_counter[0]) |
if (IsInterLuma) |
begin |
if (!mv_below8x8_curr) |
xOffsetL <= (blk4x4_rec_counter[2])? 4'd8:4'd0; |
else |
case ({blk4x4_rec_counter[2],blk4x4_rec_counter[0]}) |
2'b00:xOffsetL <= 4'd0; |
2'b01:xOffsetL <= 4'd4; |
2'b10:xOffsetL <= 4'd8; |
2'b11:xOffsetL <= 4'd12; |
endcase |
end |
else |
xOffsetL <= 0; |
|
always @ (IsInterLuma or mv_below8x8_curr or blk4x4_rec_counter[3] or blk4x4_rec_counter[1]) |
if (IsInterLuma) |
begin |
if (!mv_below8x8_curr) |
yOffsetL <= (blk4x4_rec_counter[3])? 4'd8:4'd0; |
else |
case ({blk4x4_rec_counter[3],blk4x4_rec_counter[1]}) |
2'b00:yOffsetL <= 4'd0; |
2'b01:yOffsetL <= 4'd4; |
2'b10:yOffsetL <= 4'd8; |
2'b11:yOffsetL <= 4'd12; |
endcase |
end |
else |
yOffsetL <= 0; |
|
reg [2:0] xOffsetC,yOffsetC; |
always @ (IsInterChroma or mv_below8x8_curr or blk4x4_rec_counter[0] or Inter_chroma2x2_counter[0]) |
if (IsInterChroma) |
begin |
if (mv_below8x8_curr == 1'b0) |
xOffsetC <= (blk4x4_rec_counter[0] == 1'b0)? 3'd0:3'd4; |
else |
case (blk4x4_rec_counter[0]) |
1'b0:xOffsetC <= (Inter_chroma2x2_counter[0] == 1'b1)? 3'd0:3'd2; |
1'b1:xOffsetC <= (Inter_chroma2x2_counter[0] == 1'b1)? 3'd4:3'd6; |
endcase |
end |
else |
xOffsetC <= 0; |
|
always @ (IsInterChroma or mv_below8x8_curr or blk4x4_rec_counter[1] or Inter_chroma2x2_counter[1]) |
if (IsInterChroma) |
begin |
if (mv_below8x8_curr == 1'b0) |
yOffsetC <= (blk4x4_rec_counter[1] == 1'b0)? 3'd0:3'd4; |
else |
case (blk4x4_rec_counter[1]) |
1'b0:yOffsetC <= (Inter_chroma2x2_counter[1] == 1'b1)? 3'd0:3'd2; |
1'b1:yOffsetC <= (Inter_chroma2x2_counter[1] == 1'b1)? 3'd4:3'd6; |
endcase |
end |
else |
yOffsetC <= 3'd0; |
//---------------------------------------------------------------------------------------- |
//Integer position of each left-up-most pixel of a 8x8/4x4/2x2 blk |
//---------------------------------------------------------------------------------------- |
wire [8:0] xIntL_unclip,yIntL_unclip; // 2's complement,bit[8] is the sign bit |
wire [7:0] xIntC_unclip,yIntC_unclip; // 2's complement,bit[7] is the sign bit |
assign xIntL_unclip = (IsInterLuma)? ({1'b0,mb_num_h,4'b0} + xOffsetL + {{3{Inter_blk_mvx[7]}},Inter_blk_mvx[7:2]}):0; |
assign yIntL_unclip = (IsInterLuma)? ({1'b0,mb_num_v,4'b0} + yOffsetL + {{3{Inter_blk_mvy[7]}},Inter_blk_mvy[7:2]}):0; |
assign xIntC_unclip = (IsInterChroma)? ({1'b0,mb_num_h,3'b0} + xOffsetC + {{3{Inter_blk_mvx[7]}},Inter_blk_mvx[7:3]}):0; |
assign yIntC_unclip = (IsInterChroma)? ({1'b0,mb_num_v,3'b0} + yOffsetC + {{3{Inter_blk_mvy[7]}},Inter_blk_mvy[7:3]}):0; |
|
wire [8:0] xInt_org_unclip; |
wire [8:0] yInt_org_unclip; |
assign xInt_org_unclip = (IsInterLuma)? xIntL_unclip:{xIntC_unclip[7],xIntC_unclip}; |
assign yInt_org_unclip = (IsInterLuma)? yIntL_unclip:{yIntC_unclip[7],yIntC_unclip}; |
assign xInt_org_unclip_1to0 = xInt_org_unclip[1:0]; |
//---------------------------------------------------------------------------------------- |
//Fractional motion vector for both luma and chroma |
//---------------------------------------------------------------------------------------- |
wire [3:0] pos_FracL; |
wire Is_InterChromaCopy;//If chroma is predicted by direct copy,calculate cycle would reduce |
//from 16 cycles to 4 cycles |
|
assign xFracL = (IsInterLuma)? Inter_blk_mvx[1:0]:0; |
assign yFracL = (IsInterLuma)? Inter_blk_mvy[1:0]:0; |
assign xFracC = (IsInterChroma)? Inter_blk_mvx[2:0]:0; |
assign yFracC = (IsInterChroma)? Inter_blk_mvy[2:0]:0; |
assign pos_FracL = {xFracL,yFracL}; |
assign Is_InterChromaCopy = (IsInterChroma && xFracC == 0 && yFracC == 0)? 1'b1:1'b0; |
|
//---------------------------------------------------------------------------------------- |
//Inter prediction step control counter |
//---------------------------------------------------------------------------------------- |
//1.Preload integer pels counter |
// If block partition equals 8x8 or above,preload only at first 4x4 block of each 8x8block |
// If block partition is 8x4,4x8 or 4x4, preload at each 4x4 block |
always @ (posedge clk) |
if (reset_n == 1'b0) |
blk4x4_inter_preload_counter <= 0; |
//luma |
else if (trigger_blk4x4_inter_pred && IsInterLuma) |
begin |
if (!mv_below8x8_curr && blk4x4_rec_counter[1:0] == 2'b00) |
case (pos_FracL) |
`pos_Int :blk4x4_inter_preload_counter <= (xInt_org_unclip[1:0] == 2'b00)? 6'd17:6'd25; |
`pos_f,`pos_q,`pos_i,`pos_k,`pos_j:blk4x4_inter_preload_counter <= 6'd53; |
`pos_d,`pos_h,`pos_n :blk4x4_inter_preload_counter <= (xInt_org_unclip[1:0] == 2'b00)? 6'd27:6'd40; |
`pos_a,`pos_b,`pos_c :blk4x4_inter_preload_counter <= 6'd33; |
`pos_e,`pos_g,`pos_p,`pos_r :blk4x4_inter_preload_counter <= 6'd49; |
endcase |
else if (mv_below8x8_curr) //partition below 8x8block |
case (pos_FracL) |
`pos_Int :blk4x4_inter_preload_counter <= (xInt_org_unclip[1:0] == 2'b00)? 6'd5:6'd9; |
`pos_f,`pos_q,`pos_i,`pos_k,`pos_j:blk4x4_inter_preload_counter <= 6'd28; |
`pos_d,`pos_h,`pos_n :blk4x4_inter_preload_counter <= (xInt_org_unclip[1:0] == 2'b00)? 6'd10:6'd19; |
`pos_a,`pos_b,`pos_c :blk4x4_inter_preload_counter <= 6'd13; |
`pos_e,`pos_g,`pos_p,`pos_r :blk4x4_inter_preload_counter <= 6'd24; |
endcase |
end |
//chroma |
else if (trigger_blk4x4_inter_pred && IsInterChroma && mv_below8x8_curr == 1'b0) |
begin |
if (xFracC == 0 && yFracC == 0) |
blk4x4_inter_preload_counter <= (xInt_org_unclip[1:0] == 2'b00)? 6'd5:6'd9; |
else |
blk4x4_inter_preload_counter <= 6'd11; |
end |
else if (trigger_blk2x2_inter_pred && IsInterChroma && mv_below8x8_curr == 1'b1) |
begin |
if (xFracC == 0 && yFracC == 0) |
blk4x4_inter_preload_counter <= (xInt_org_unclip[1:0] == 2'b11)? 6'd5:6'd3; |
else |
blk4x4_inter_preload_counter <= (xInt_org_unclip[1] == 1'b0 )? 6'd4:6'd7; |
end |
else if (blk4x4_inter_preload_counter != 0) |
blk4x4_inter_preload_counter <= blk4x4_inter_preload_counter - 1; |
|
//2.Calculate counter |
always @ (posedge clk) |
if (reset_n == 1'b0) |
blk4x4_inter_calculate_counter <= 0; |
//luma |
else if (IsInterLuma && ((!mv_below8x8_curr && ( |
(blk4x4_rec_counter[1:0] == 2'b00 && blk4x4_inter_preload_counter == 1) || |
(blk4x4_rec_counter[1:0] != 2'b00 && trigger_blk4x4_inter_pred))) || |
(mv_below8x8_curr && blk4x4_inter_preload_counter == 1))) |
case (pos_FracL) |
`pos_j,`pos_f,`pos_q:blk4x4_inter_calculate_counter <= 4'd5; |
`pos_i,`pos_k :blk4x4_inter_calculate_counter <= 4'd8; |
default :blk4x4_inter_calculate_counter <= 4'd4; |
endcase |
//chroma |
else if (blk4x4_inter_preload_counter == 1 && IsInterChroma == 1'b1) |
case (mv_below8x8_curr) |
1'b0:blk4x4_inter_calculate_counter <= 4'd4; |
1'b1:blk4x4_inter_calculate_counter <= 4'd1; |
endcase |
else if (blk4x4_inter_calculate_counter != 0) |
blk4x4_inter_calculate_counter <= blk4x4_inter_calculate_counter - 1; |
|
assign end_of_one_blk4x4_inter = (blk4x4_inter_calculate_counter == 4'd1 && |
((IsInterChroma && mv_below8x8_curr && Inter_chroma2x2_counter == 2'b00) || |
!(IsInterChroma && mv_below8x8_curr))); |
//---------------------------------------------------------------------------------------- |
//Inter prediction reference frame RAM read control |
//---------------------------------------------------------------------------------------- |
assign ref_frame_RAM_rd = ((IsInterLuma || IsInterChroma) && blk4x4_inter_preload_counter != 6'd0 && blk4x4_inter_preload_counter != 6'd1); |
|
//compared with blk4x4_inter_preload_counter,blk4x4_inter_preload_counter_m2 has some advantages |
//during some pos_FracL for vertical memory address decoding |
wire [5:0] blk4x4_inter_preload_counter_m2; |
assign blk4x4_inter_preload_counter_m2 = (blk4x4_inter_preload_counter == 6'd0 || blk4x4_inter_preload_counter == 6'd1)? |
6'd0:(blk4x4_inter_preload_counter - 2); |
|
//xInt_curr_offset: offset from the left-upper most pixel of current block,ranging -2 ~ +10. |
//After each preload cycle,xInt_curr_offset will increase 4 |
reg [4:0] xInt_curr_offset; |
always @ (IsInterLuma or mv_below8x8_curr or pos_FracL or xFracC or yFracC |
or xInt_org_unclip[1:0] or blk4x4_inter_preload_counter_m2 or blk4x4_inter_preload_counter) |
if (blk4x4_inter_preload_counter != 6'd0 && blk4x4_inter_preload_counter != 6'd1) |
begin |
if (IsInterLuma) |
begin |
if (!mv_below8x8_curr) |
case (pos_FracL) |
`pos_f,`pos_q,`pos_i,`pos_k,`pos_j: |
case (blk4x4_inter_preload_counter_m2[1:0]) |
2'b00:xInt_curr_offset <= 5'b01010; //+10 |
2'b01:xInt_curr_offset <= 5'b00110; //+6 |
2'b10:xInt_curr_offset <= 5'b00010; //+2 |
2'b11:xInt_curr_offset <= 5'b11110; //-2 |
endcase |
`pos_d,`pos_h,`pos_n: |
if (xInt_org_unclip[1:0] == 2'b00) |
xInt_curr_offset <= (blk4x4_inter_preload_counter_m2[0])? 4'b0:4'b0100; //+0 or +4 |
else |
case (blk4x4_inter_preload_counter_m2) |
6'd38,6'd35,6'd32,6'd29,6'd26,6'd23,6'd20,6'd17,6'd14,6'd11,6'd8,6'd5,6'd2: |
xInt_curr_offset <= 5'b0; //+0 |
6'd37,6'd34,6'd31,6'd28,6'd25,6'd22,6'd19,6'd16,6'd13,6'd10,6'd7,6'd4,6'd1: |
xInt_curr_offset <= 5'b00100; //+4 |
default:xInt_curr_offset <= 5'b01000;//+8 |
endcase |
`pos_a,`pos_b,`pos_c: |
case (blk4x4_inter_preload_counter_m2[1:0]) |
2'b00:xInt_curr_offset <= 5'b01010; //+10 |
2'b01:xInt_curr_offset <= 5'b00110; //+6 |
2'b10:xInt_curr_offset <= 5'b00010; //+2 |
2'b11:xInt_curr_offset <= 5'b11110; //-2 |
endcase |
`pos_Int: |
if (xInt_org_unclip[1:0] == 2'b00) |
xInt_curr_offset <= (blk4x4_inter_preload_counter_m2[0])? 5'b0:5'b0100; //+0 or +4 |
else |
case (blk4x4_inter_preload_counter_m2) |
6'd23,6'd20,6'd17,6'd14,6'd11,6'd8,6'd5,6'd2: |
xInt_curr_offset <= 5'b00000; //+0 |
6'd22,6'd19,6'd16,6'd13,6'd10,6'd7,6'd4,6'd1: |
xInt_curr_offset <= 5'b00100; //+4 |
default:xInt_curr_offset <= 5'b01000;//+8 |
endcase |
`pos_e,`pos_g,`pos_p,`pos_r: |
case (blk4x4_inter_preload_counter_m2) |
6'd47,6'd44,6'd5,6'd2: |
xInt_curr_offset <= 5'b00000; //+0 |
6'd46,6'd43,6'd4,6'd1: |
xInt_curr_offset <= 5'b00100; //+4 |
6'd45,6'd42,6'd3,6'd0: |
xInt_curr_offset <= 5'b01000; //+8 |
default: |
case (blk4x4_inter_preload_counter_m2[1:0]) |
2'b00:xInt_curr_offset <= 5'b00010; //+2 |
2'b01:xInt_curr_offset <= 5'b11110; //-2 |
2'b10:xInt_curr_offset <= 5'b01010; //+10 |
2'b11:xInt_curr_offset <= 5'b00110; //+6 |
endcase |
endcase |
endcase |
else //block partition below 8x8 |
case (pos_FracL) |
`pos_f,`pos_q,`pos_i,`pos_k,`pos_j: |
case (blk4x4_inter_preload_counter_m2) |
6'd26,6'd23,6'd20,6'd17,6'd14,6'd11,6'd8,6'd5,6'd2:xInt_curr_offset <= 5'b11110;//-2 |
6'd25,6'd22,6'd19,6'd16,6'd13,6'd10,6'd7,6'd4,6'd1:xInt_curr_offset <= 5'b00010;//+2 |
default:xInt_curr_offset <= 5'b00110; //+6 |
endcase |
`pos_d,`pos_h,`pos_n: |
if (xInt_org_unclip[1:0] == 2'b00) |
xInt_curr_offset <= 5'b0; //+0 |
else |
xInt_curr_offset <= (blk4x4_inter_preload_counter_m2[0])? 5'b0:5'b00100;//+0 or +4 |
`pos_a,`pos_b,`pos_c: |
case (blk4x4_inter_preload_counter_m2) |
6'd11,6'd8,6'd5,6'd2:xInt_curr_offset <= 5'b11110; //-2 |
6'd10,6'd7,6'd4,6'd1:xInt_curr_offset <= 5'b00010; //+2 |
default:xInt_curr_offset <= 5'b00110; //+6 |
endcase |
`pos_Int: |
if (xInt_org_unclip[1:0] == 2'b00) |
xInt_curr_offset <= 5'b0; //+0 |
else |
xInt_curr_offset <= (blk4x4_inter_preload_counter_m2[0])? 5'b0:5'b00100; //+0 or +4 |
`pos_e,`pos_g,`pos_p,`pos_r: |
case (blk4x4_inter_preload_counter_m2) |
6'd22,6'd20,6'd3,6'd1:xInt_curr_offset <= 5'b0; //+0 |
6'd21,6'd19,6'd2,6'd0:xInt_curr_offset <= 5'b00100; //+4 |
6'd18,6'd15,6'd12,6'd9,6'd6:xInt_curr_offset <= 5'b11110;//-2 |
6'd17,6'd14,6'd11,6'd8,6'd5:xInt_curr_offset <= 5'b00010;//+2 |
6'd16,6'd13,6'd10,6'd7,6'd4:xInt_curr_offset <= 5'b00110;//+6 |
default:xInt_curr_offset <= 5'b0; |
endcase |
endcase |
end |
else //IsInterChroma |
begin |
if (!mv_below8x8_curr) |
begin |
if (xFracC == 0 && yFracC == 0) |
begin |
if (xInt_org_unclip[1:0] == 2'b00) |
xInt_curr_offset <= 5'b0; |
else |
xInt_curr_offset <= (blk4x4_inter_preload_counter_m2[0] == 1'b1)? 5'b0:5'b0100; |
end |
else |
xInt_curr_offset <= (blk4x4_inter_preload_counter_m2[0] == 1'b1)? 5'b0:5'b0100; |
end |
else //mv_below8x8_curr == 1'b1 |
begin |
if (xFracC == 0 && yFracC == 0) |
begin |
if (xInt_org_unclip[1:0] == 2'b11) // 4 preload cycles |
xInt_curr_offset <= (blk4x4_inter_preload_counter_m2[0] == 1'b1)? 5'b0:5'b0100; |
else |
xInt_curr_offset <= 0; |
end |
else |
begin |
if (xInt_org_unclip[1] == 1'b0) |
xInt_curr_offset <= 0; |
else |
xInt_curr_offset <= (blk4x4_inter_preload_counter_m2[0] == 1'b1)? 5'b0:5'b0100; |
end |
end |
end |
end |
else //blk4x4_inter_preload_counter == 0 || blk4x4_inter_preload_counter == 1 |
xInt_curr_offset <= 5'b0; |
|
//Derive unclipped x pos for each preload cycle |
wire [8:0] xInt_addr_unclip; |
assign xInt_addr_unclip = xInt_org_unclip + {{4{xInt_curr_offset[4]}},xInt_curr_offset}; |
|
//x addr clipped:x address in pixels |
reg [7:0] xInt_addr; |
always @ (xInt_addr_unclip or IsInterLuma or IsInterChroma) |
if (xInt_addr_unclip[8] == 1'b1) //negative |
xInt_addr <= 0; |
else if (IsInterLuma) |
xInt_addr <= (xInt_addr_unclip[7:0] > (`pic_width - 4))? 8'd172:xInt_addr_unclip[7:0]; |
else if (IsInterChroma) |
xInt_addr <= (xInt_addr_unclip[7:0] > (`half_pic_width - 4))? 8'd84:xInt_addr_unclip[7:0]; |
else |
xInt_addr <= 0; |
|
//yInt_p1:when loading from Xth line to (X-1)th line,yInt_p1 is set to 1'b1 at the last |
//loading cycle of current Xth line |
reg yInt_p1; |
always @ (IsInterLuma or mv_below8x8_curr or pos_FracL or xFracC or yFracC |
or blk4x4_inter_preload_counter or blk4x4_inter_preload_counter_m2 or xInt_org_unclip[1:0] or xInt_org_unclip[1]) |
if (blk4x4_inter_preload_counter != 6'd0 && blk4x4_inter_preload_counter != 6'd1) |
begin |
if (IsInterLuma) |
case (mv_below8x8_curr) |
1'b0: |
case (pos_FracL) |
`pos_f,`pos_q,`pos_i,`pos_k,`pos_j: |
yInt_p1 <= (blk4x4_inter_preload_counter_m2[1:0] == 2'b00)? 1'b1:1'b0; |
`pos_d,`pos_h,`pos_n: |
if (xInt_org_unclip[1:0] == 2'b00) |
yInt_p1 <= (blk4x4_inter_preload_counter_m2[0] == 1'b0)? 1'b1:1'b0; |
else |
case (blk4x4_inter_preload_counter_m2) |
6'd36,6'd33,6'd30,6'd27,6'd24,6'd21,6'd18,6'd15,6'd12,6'd9,6'd6,6'd3,6'd0: |
yInt_p1 <= 1'b1; |
default:yInt_p1 <= 1'b0; |
endcase |
`pos_a,`pos_b,`pos_c: |
yInt_p1 <= (blk4x4_inter_preload_counter_m2[1:0] == 2'b00)? 1'b1:1'b0; |
`pos_Int: |
if (xInt_org_unclip[1:0] == 2'b00) |
yInt_p1 <= (blk4x4_inter_preload_counter_m2[0] == 1'b0)? 1'b1:1'b0; |
else |
case (blk4x4_inter_preload_counter_m2) |
6'd21,6'd18,6'd15,6'd12,6'd9,6'd6,6'd3,6'd0:yInt_p1 <= 1'b1; |
default: yInt_p1 <= 1'b0; |
endcase |
`pos_e,`pos_g,`pos_p,`pos_r: |
case (blk4x4_inter_preload_counter_m2) |
6'd45,6'd42,6'd3,6'd0:yInt_p1 <= 1'b1; |
6'd6,6'd10,6'd14,6'd18,6'd22,6'd26,6'd30,6'd34,6'd38:yInt_p1 <= 1'b1; |
default:yInt_p1 <= 1'b0; |
endcase |
endcase |
1'b1: //block partition below 8x8 |
case (pos_FracL) |
`pos_f,`pos_q,`pos_i,`pos_k,`pos_j: |
case (blk4x4_inter_preload_counter_m2) |
6'd24,6'd21,6'd18,6'd15,6'd12,6'd9,6'd6,6'd3,6'd0:yInt_p1 <= 1'b1; |
default:yInt_p1 <= 1'b0; |
endcase |
`pos_d,`pos_h,`pos_n: |
if (xInt_org_unclip[1:0] == 2'b00) |
yInt_p1 <= 1'b1; |
else |
yInt_p1 <= (blk4x4_inter_preload_counter_m2[0] == 1'b0)? 1'b1:1'b0; |
`pos_a,`pos_b,`pos_c: |
case (blk4x4_inter_preload_counter_m2) |
5'd9,5'd6,5'd3,5'd0 :yInt_p1 <= 1'b1; |
default :yInt_p1 <= 1'b0; |
endcase |
`pos_Int: |
if (xInt_org_unclip[1:0] == 2'b00) |
yInt_p1 <= 1'b1; |
else |
yInt_p1 <= (blk4x4_inter_preload_counter_m2[0] == 1'b0)? 1'b1:1'b0; |
`pos_e,`pos_g,`pos_p,`pos_r: |
case (blk4x4_inter_preload_counter_m2) |
6'd21,6'd19,6'd2,6'd0 :yInt_p1 <= 1'b1; |
6'd4,6'd7,6'd10,6'd13,6'd16 :yInt_p1 <= 1'b1; |
default :yInt_p1 <= 1'b0; |
endcase |
endcase |
endcase |
else //IsInterChroma |
case (mv_below8x8_curr) |
1'b0: |
if (xFracC == 0 && yFracC == 0) |
begin |
if (xInt_org_unclip[1:0] == 2'b00) |
yInt_p1 <= 1'b1; |
else |
yInt_p1 <= (blk4x4_inter_preload_counter_m2[0] == 1'b0)? 1'b1:1'b0; |
end |
else |
yInt_p1 <= (blk4x4_inter_preload_counter_m2[0] == 1'b0)? 1'b1:1'b0; |
1'b1: |
if (xFracC == 0 && yFracC == 0) |
begin |
if (xInt_org_unclip[1:0] != 2'b11) |
yInt_p1 <= 1'b1; |
else |
yInt_p1 <= (blk4x4_inter_preload_counter_m2[0] == 1'b0)? 1'b1:1'b0; |
end |
else |
begin |
if (xInt_org_unclip[1] == 1'b0) |
yInt_p1 <= 1'b1; |
else |
yInt_p1 <= (blk4x4_inter_preload_counter_m2[0] == 1'b0)? 1'b1:1'b0; |
end |
endcase |
end |
else // blk4x4_inter_preload_counter == 0 || blk4x4_inter_preload_counter == 1 |
yInt_p1 <= 1'b0; |
|
//Derive unclipped y pos for each preload cycle |
reg [8:0] yInt_addr_unclip; |
always @ (posedge clk) |
if (reset_n == 1'b0) |
yInt_addr_unclip <= 0; |
else if ((IsInterLuma && (trigger_blk4x4_inter_pred && (mv_below8x8_curr || |
(!mv_below8x8_curr && blk4x4_rec_counter[1:0] == 2'b00)))) || |
(IsInterChroma && (!mv_below8x8_curr && trigger_blk4x4_inter_pred) || |
(mv_below8x8_curr && trigger_blk2x2_inter_pred))) |
begin |
if (IsInterLuma) //Luma |
case (pos_FracL) |
`pos_a,`pos_b,`pos_c,`pos_Int: |
yInt_addr_unclip <= yInt_org_unclip; |
default: //need -2 here |
yInt_addr_unclip <= yInt_org_unclip + 9'b111111110; |
endcase |
else //Chroma |
yInt_addr_unclip <= yInt_org_unclip; |
end |
else if (blk4x4_inter_preload_counter_m2 != 0 && yInt_p1 == 1'b1) |
yInt_addr_unclip <= yInt_addr_unclip + 1; |
|
//y addr clipped |
reg [7:0] yInt_addr; |
always @ (yInt_addr_unclip or IsInterLuma or IsInterChroma) |
if (yInt_addr_unclip[8] == 1'b1) //negative |
yInt_addr <= 0; |
else if (IsInterLuma) |
yInt_addr <= (yInt_addr_unclip[7:0] > (`pic_height - 1))? 8'd143:yInt_addr_unclip[7:0]; |
else if (IsInterChroma) |
yInt_addr <= (yInt_addr_unclip[7:0] > (`half_pic_height - 1))? 8'd71:yInt_addr_unclip[7:0]; |
else |
yInt_addr <= 0; |
|
wire [12:0] offset_constant; |
wire [10:0] yInt_addr_x11; |
wire [12:0] offset_yInt_addr; |
assign offset_constant = (IsInterLuma)? 0:((IsInterChroma)? ((blk4x4_rec_counter < 5'd20)? 13'd6336:13'd7920):0); |
assign yInt_addr_x11 = {yInt_addr,3'b0} + {2'b0,yInt_addr,1'b0} + {3'b0,yInt_addr}; |
assign offset_yInt_addr = (IsInterLuma)? {yInt_addr_x11,2'b0}:{1'b0,yInt_addr_x11,1'b0}; |
assign ref_frame_RAM_rd_addr = (offset_constant + {8'b0,xInt_addr[7:2]}) + {1'b0,offset_yInt_addr}; |
|
//---------------------------------------------------------------------------------------- |
//Inter prediction output control: from LPE or from CPE |
//---------------------------------------------------------------------------------------- |
always @ (IsInterLuma or IsInterChroma or Is_InterChromaCopy |
or blk4x4_inter_calculate_counter or pos_FracL |
or Inter_pix_copy0 or Inter_pix_copy1 or Inter_pix_copy2 or Inter_pix_copy3 |
or LPE0_out or LPE1_out or LPE2_out or LPE3_out |
or CPE0_out or CPE1_out or CPE2_out or CPE3_out) |
if (IsInterLuma && blk4x4_inter_calculate_counter != 0) |
begin |
Inter_blk4x4_pred_output_valid <= 2'b01; |
case (pos_FracL) |
`pos_Int: |
begin |
Inter_pred_out0 <= Inter_pix_copy0;Inter_pred_out1 <= Inter_pix_copy1; |
Inter_pred_out2 <= Inter_pix_copy2;Inter_pred_out3 <= Inter_pix_copy3; |
end |
`pos_i,`pos_k: |
if (blk4x4_inter_calculate_counter == 4'd7 || blk4x4_inter_calculate_counter == 4'd5 || |
blk4x4_inter_calculate_counter == 4'd3 || blk4x4_inter_calculate_counter == 4'd1) |
begin |
Inter_pred_out0 <= LPE0_out;Inter_pred_out1 <= LPE1_out; |
Inter_pred_out2 <= LPE2_out;Inter_pred_out3 <= LPE3_out; |
end |
else |
begin |
Inter_pred_out0 <= 0;Inter_pred_out1 <= 0;Inter_pred_out2 <= 0;Inter_pred_out3 <= 0; |
end |
default: |
if (blk4x4_inter_calculate_counter == 4'd4 || blk4x4_inter_calculate_counter == 4'd3 || |
blk4x4_inter_calculate_counter == 4'd2 || blk4x4_inter_calculate_counter == 4'd1) |
begin |
Inter_pred_out0 <= LPE0_out;Inter_pred_out1 <= LPE1_out; |
Inter_pred_out2 <= LPE2_out;Inter_pred_out3 <= LPE3_out; |
end |
else |
begin |
Inter_pred_out0 <= 0;Inter_pred_out1 <= 0;Inter_pred_out2 <= 0;Inter_pred_out3 <= 0; |
end |
endcase |
end |
else if (IsInterChroma && blk4x4_inter_calculate_counter != 0) |
begin |
Inter_pred_out0 <= (Is_InterChromaCopy)? Inter_pix_copy0:CPE0_out; |
Inter_pred_out1 <= (Is_InterChromaCopy)? Inter_pix_copy1:CPE1_out; |
Inter_pred_out2 <= (Is_InterChromaCopy)? Inter_pix_copy2:CPE2_out; |
Inter_pred_out3 <= (Is_InterChromaCopy)? Inter_pix_copy3:CPE3_out; |
Inter_blk4x4_pred_output_valid <= 2'b10; |
end |
else |
begin |
Inter_pred_out0 <= 0;Inter_pred_out1 <= 0;Inter_pred_out2 <= 0;Inter_pred_out3 <= 0; |
Inter_blk4x4_pred_output_valid <= 2'b00; |
end |
endmodule |
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/trunk/src/Inter_pred_sliding_window.v
0,0 → 1,2227
//-------------------------------------------------------------------------------------------------- |
// Design : nova |
// Author(s) : Ke Xu |
// Email : eexuke@yahoo.com |
// File : Inter_pred_sliding_window.v |
// Generated : Oct 25, 2005 |
// Copyright (C) 2008 Ke Xu |
//------------------------------------------------------------------------------------------------- |
// Description |
// Prepare the appropriate registers for Inter prediction (luma & chroma) |
// 1)Luma:horizontal window 6x9,vertical window 1x9 |
// 2)Chroma:window 2x2 |
//------------------------------------------------------------------------------------------------- |
|
// synopsys translate_off |
`include "timescale.v" |
// synopsys translate_on |
`include "nova_defines.v" |
|
module Inter_pred_sliding_window (IsInterLuma,IsInterChroma,Is_InterChromaCopy,mv_below8x8_curr, |
pos_FracL,blk4x4_rec_counter_1to0,blk4x4_inter_calculate_counter, |
Inter_ref_00_00,Inter_ref_01_00,Inter_ref_02_00,Inter_ref_03_00,Inter_ref_04_00,Inter_ref_05_00, |
Inter_ref_06_00,Inter_ref_07_00,Inter_ref_08_00,Inter_ref_09_00,Inter_ref_10_00,Inter_ref_11_00,Inter_ref_12_00, |
Inter_ref_00_01,Inter_ref_01_01,Inter_ref_02_01,Inter_ref_03_01,Inter_ref_04_01,Inter_ref_05_01, |
Inter_ref_06_01,Inter_ref_07_01,Inter_ref_08_01,Inter_ref_09_01,Inter_ref_10_01,Inter_ref_11_01,Inter_ref_12_01, |
Inter_ref_00_02,Inter_ref_01_02,Inter_ref_02_02,Inter_ref_03_02,Inter_ref_04_02,Inter_ref_05_02, |
Inter_ref_06_02,Inter_ref_07_02,Inter_ref_08_02,Inter_ref_09_02,Inter_ref_10_02,Inter_ref_11_02,Inter_ref_12_02, |
Inter_ref_00_03,Inter_ref_01_03,Inter_ref_02_03,Inter_ref_03_03,Inter_ref_04_03,Inter_ref_05_03, |
Inter_ref_06_03,Inter_ref_07_03,Inter_ref_08_03,Inter_ref_09_03,Inter_ref_10_03,Inter_ref_11_03,Inter_ref_12_03, |
Inter_ref_00_04,Inter_ref_01_04,Inter_ref_02_04,Inter_ref_03_04,Inter_ref_04_04,Inter_ref_05_04, |
Inter_ref_06_04,Inter_ref_07_04,Inter_ref_08_04,Inter_ref_09_04,Inter_ref_10_04,Inter_ref_11_04,Inter_ref_12_04, |
Inter_ref_00_05,Inter_ref_01_05,Inter_ref_02_05,Inter_ref_03_05,Inter_ref_04_05,Inter_ref_05_05, |
Inter_ref_06_05,Inter_ref_07_05,Inter_ref_08_05,Inter_ref_09_05,Inter_ref_10_05,Inter_ref_11_05,Inter_ref_12_05, |
Inter_ref_00_06,Inter_ref_01_06,Inter_ref_02_06,Inter_ref_03_06,Inter_ref_04_06,Inter_ref_05_06, |
Inter_ref_06_06,Inter_ref_07_06,Inter_ref_08_06,Inter_ref_09_06,Inter_ref_10_06,Inter_ref_11_06,Inter_ref_12_06, |
Inter_ref_00_07,Inter_ref_01_07,Inter_ref_02_07,Inter_ref_03_07,Inter_ref_04_07,Inter_ref_05_07, |
Inter_ref_06_07,Inter_ref_07_07,Inter_ref_08_07,Inter_ref_09_07,Inter_ref_10_07,Inter_ref_11_07,Inter_ref_12_07, |
Inter_ref_00_08,Inter_ref_01_08,Inter_ref_02_08,Inter_ref_03_08,Inter_ref_04_08,Inter_ref_05_08, |
Inter_ref_06_08,Inter_ref_07_08,Inter_ref_08_08,Inter_ref_09_08,Inter_ref_10_08,Inter_ref_11_08,Inter_ref_12_08, |
Inter_ref_00_09,Inter_ref_01_09,Inter_ref_02_09,Inter_ref_03_09,Inter_ref_04_09,Inter_ref_05_09, |
Inter_ref_06_09,Inter_ref_07_09,Inter_ref_08_09,Inter_ref_09_09,Inter_ref_10_09,Inter_ref_11_09,Inter_ref_12_09, |
Inter_ref_00_10,Inter_ref_01_10,Inter_ref_02_10,Inter_ref_03_10,Inter_ref_04_10,Inter_ref_05_10, |
Inter_ref_06_10,Inter_ref_07_10,Inter_ref_08_10,Inter_ref_09_10,Inter_ref_10_10,Inter_ref_11_10,Inter_ref_12_10, |
Inter_ref_00_11,Inter_ref_01_11,Inter_ref_02_11,Inter_ref_03_11,Inter_ref_04_11,Inter_ref_05_11, |
Inter_ref_06_11,Inter_ref_07_11,Inter_ref_08_11,Inter_ref_09_11,Inter_ref_10_11,Inter_ref_11_11,Inter_ref_12_11, |
Inter_ref_00_12,Inter_ref_01_12,Inter_ref_02_12,Inter_ref_03_12,Inter_ref_04_12,Inter_ref_05_12, |
Inter_ref_06_12,Inter_ref_07_12,Inter_ref_08_12,Inter_ref_09_12,Inter_ref_10_12,Inter_ref_11_12,Inter_ref_12_12, |
|
Inter_pix_copy0,Inter_pix_copy1,Inter_pix_copy2,Inter_pix_copy3, |
Inter_H_window_0_0,Inter_H_window_1_0,Inter_H_window_2_0,Inter_H_window_3_0,Inter_H_window_4_0,Inter_H_window_5_0, |
Inter_H_window_0_1,Inter_H_window_1_1,Inter_H_window_2_1,Inter_H_window_3_1,Inter_H_window_4_1,Inter_H_window_5_1, |
Inter_H_window_0_2,Inter_H_window_1_2,Inter_H_window_2_2,Inter_H_window_3_2,Inter_H_window_4_2,Inter_H_window_5_2, |
Inter_H_window_0_3,Inter_H_window_1_3,Inter_H_window_2_3,Inter_H_window_3_3,Inter_H_window_4_3,Inter_H_window_5_3, |
Inter_H_window_0_4,Inter_H_window_1_4,Inter_H_window_2_4,Inter_H_window_3_4,Inter_H_window_4_4,Inter_H_window_5_4, |
Inter_H_window_0_5,Inter_H_window_1_5,Inter_H_window_2_5,Inter_H_window_3_5,Inter_H_window_4_5,Inter_H_window_5_5, |
Inter_H_window_0_6,Inter_H_window_1_6,Inter_H_window_2_6,Inter_H_window_3_6,Inter_H_window_4_6,Inter_H_window_5_6, |
Inter_H_window_0_7,Inter_H_window_1_7,Inter_H_window_2_7,Inter_H_window_3_7,Inter_H_window_4_7,Inter_H_window_5_7, |
Inter_H_window_0_8,Inter_H_window_1_8,Inter_H_window_2_8,Inter_H_window_3_8,Inter_H_window_4_8,Inter_H_window_5_8, |
Inter_V_window_0,Inter_V_window_1,Inter_V_window_2,Inter_V_window_3,Inter_V_window_4, |
Inter_V_window_5,Inter_V_window_6,Inter_V_window_7,Inter_V_window_8, |
Inter_C_window_0_0,Inter_C_window_1_0,Inter_C_window_2_0, |
Inter_C_window_0_1,Inter_C_window_1_1,Inter_C_window_2_1, |
Inter_C_window_0_2,Inter_C_window_1_2,Inter_C_window_2_2, |
Inter_bi_window_0,Inter_bi_window_1,Inter_bi_window_2,Inter_bi_window_3); |
input IsInterLuma; |
input IsInterChroma; |
input Is_InterChromaCopy; |
input mv_below8x8_curr; |
input [3:0] pos_FracL; |
input [1:0] blk4x4_rec_counter_1to0; |
input [3:0] blk4x4_inter_calculate_counter; |
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input [7:0] Inter_ref_00_00,Inter_ref_01_00,Inter_ref_02_00,Inter_ref_03_00,Inter_ref_04_00,Inter_ref_05_00; |
input [7:0] Inter_ref_06_00,Inter_ref_07_00,Inter_ref_08_00,Inter_ref_09_00,Inter_ref_10_00,Inter_ref_11_00,Inter_ref_12_00; |
input [7:0] Inter_ref_00_01,Inter_ref_01_01,Inter_ref_02_01,Inter_ref_03_01,Inter_ref_04_01,Inter_ref_05_01; |
input [7:0] Inter_ref_06_01,Inter_ref_07_01,Inter_ref_08_01,Inter_ref_09_01,Inter_ref_10_01,Inter_ref_11_01,Inter_ref_12_01; |
input [7:0] Inter_ref_00_02,Inter_ref_01_02,Inter_ref_02_02,Inter_ref_03_02,Inter_ref_04_02,Inter_ref_05_02; |
input [7:0] Inter_ref_06_02,Inter_ref_07_02,Inter_ref_08_02,Inter_ref_09_02,Inter_ref_10_02,Inter_ref_11_02,Inter_ref_12_02; |
input [7:0] Inter_ref_00_03,Inter_ref_01_03,Inter_ref_02_03,Inter_ref_03_03,Inter_ref_04_03,Inter_ref_05_03; |
input [7:0] Inter_ref_06_03,Inter_ref_07_03,Inter_ref_08_03,Inter_ref_09_03,Inter_ref_10_03,Inter_ref_11_03,Inter_ref_12_03; |
input [7:0] Inter_ref_00_04,Inter_ref_01_04,Inter_ref_02_04,Inter_ref_03_04,Inter_ref_04_04,Inter_ref_05_04; |
input [7:0] Inter_ref_06_04,Inter_ref_07_04,Inter_ref_08_04,Inter_ref_09_04,Inter_ref_10_04,Inter_ref_11_04,Inter_ref_12_04; |
input [7:0] Inter_ref_00_05,Inter_ref_01_05,Inter_ref_02_05,Inter_ref_03_05,Inter_ref_04_05,Inter_ref_05_05; |
input [7:0] Inter_ref_06_05,Inter_ref_07_05,Inter_ref_08_05,Inter_ref_09_05,Inter_ref_10_05,Inter_ref_11_05,Inter_ref_12_05; |
input [7:0] Inter_ref_00_06,Inter_ref_01_06,Inter_ref_02_06,Inter_ref_03_06,Inter_ref_04_06,Inter_ref_05_06; |
input [7:0] Inter_ref_06_06,Inter_ref_07_06,Inter_ref_08_06,Inter_ref_09_06,Inter_ref_10_06,Inter_ref_11_06,Inter_ref_12_06; |
input [7:0] Inter_ref_00_07,Inter_ref_01_07,Inter_ref_02_07,Inter_ref_03_07,Inter_ref_04_07,Inter_ref_05_07; |
input [7:0] Inter_ref_06_07,Inter_ref_07_07,Inter_ref_08_07,Inter_ref_09_07,Inter_ref_10_07,Inter_ref_11_07,Inter_ref_12_07; |
input [7:0] Inter_ref_00_08,Inter_ref_01_08,Inter_ref_02_08,Inter_ref_03_08,Inter_ref_04_08,Inter_ref_05_08; |
input [7:0] Inter_ref_06_08,Inter_ref_07_08,Inter_ref_08_08,Inter_ref_09_08,Inter_ref_10_08,Inter_ref_11_08,Inter_ref_12_08; |
input [7:0] Inter_ref_00_09,Inter_ref_01_09,Inter_ref_02_09,Inter_ref_03_09,Inter_ref_04_09,Inter_ref_05_09; |
input [7:0] Inter_ref_06_09,Inter_ref_07_09,Inter_ref_08_09,Inter_ref_09_09,Inter_ref_10_09,Inter_ref_11_09,Inter_ref_12_09; |
input [7:0] Inter_ref_00_10,Inter_ref_01_10,Inter_ref_02_10,Inter_ref_03_10,Inter_ref_04_10,Inter_ref_05_10; |
input [7:0] Inter_ref_06_10,Inter_ref_07_10,Inter_ref_08_10,Inter_ref_09_10,Inter_ref_10_10,Inter_ref_11_10,Inter_ref_12_10; |
input [7:0] Inter_ref_00_11,Inter_ref_01_11,Inter_ref_02_11,Inter_ref_03_11,Inter_ref_04_11,Inter_ref_05_11; |
input [7:0] Inter_ref_06_11,Inter_ref_07_11,Inter_ref_08_11,Inter_ref_09_11,Inter_ref_10_11,Inter_ref_11_11,Inter_ref_12_11; |
input [7:0] Inter_ref_00_12,Inter_ref_01_12,Inter_ref_02_12,Inter_ref_03_12,Inter_ref_04_12,Inter_ref_05_12; |
input [7:0] Inter_ref_06_12,Inter_ref_07_12,Inter_ref_08_12,Inter_ref_09_12,Inter_ref_10_12,Inter_ref_11_12,Inter_ref_12_12; |
|
output [7:0] Inter_pix_copy0,Inter_pix_copy1,Inter_pix_copy2,Inter_pix_copy3; |
output [7:0] Inter_H_window_0_0,Inter_H_window_1_0,Inter_H_window_2_0,Inter_H_window_3_0,Inter_H_window_4_0,Inter_H_window_5_0; |
output [7:0] Inter_H_window_0_1,Inter_H_window_1_1,Inter_H_window_2_1,Inter_H_window_3_1,Inter_H_window_4_1,Inter_H_window_5_1; |
output [7:0] Inter_H_window_0_2,Inter_H_window_1_2,Inter_H_window_2_2,Inter_H_window_3_2,Inter_H_window_4_2,Inter_H_window_5_2; |
output [7:0] Inter_H_window_0_3,Inter_H_window_1_3,Inter_H_window_2_3,Inter_H_window_3_3,Inter_H_window_4_3,Inter_H_window_5_3; |
output [7:0] Inter_H_window_0_4,Inter_H_window_1_4,Inter_H_window_2_4,Inter_H_window_3_4,Inter_H_window_4_4,Inter_H_window_5_4; |
output [7:0] Inter_H_window_0_5,Inter_H_window_1_5,Inter_H_window_2_5,Inter_H_window_3_5,Inter_H_window_4_5,Inter_H_window_5_5; |
output [7:0] Inter_H_window_0_6,Inter_H_window_1_6,Inter_H_window_2_6,Inter_H_window_3_6,Inter_H_window_4_6,Inter_H_window_5_6; |
output [7:0] Inter_H_window_0_7,Inter_H_window_1_7,Inter_H_window_2_7,Inter_H_window_3_7,Inter_H_window_4_7,Inter_H_window_5_7; |
output [7:0] Inter_H_window_0_8,Inter_H_window_1_8,Inter_H_window_2_8,Inter_H_window_3_8,Inter_H_window_4_8,Inter_H_window_5_8; |
output [7:0] Inter_V_window_0,Inter_V_window_1,Inter_V_window_2,Inter_V_window_3,Inter_V_window_4; |
output [7:0] Inter_V_window_5,Inter_V_window_6,Inter_V_window_7,Inter_V_window_8; |
output [7:0] Inter_C_window_0_0,Inter_C_window_1_0,Inter_C_window_2_0; |
output [7:0] Inter_C_window_0_1,Inter_C_window_1_1,Inter_C_window_2_1; |
output [7:0] Inter_C_window_0_2,Inter_C_window_1_2,Inter_C_window_2_2; |
output [7:0] Inter_bi_window_0,Inter_bi_window_1,Inter_bi_window_2,Inter_bi_window_3; |
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reg [7:0] Inter_pix_copy0,Inter_pix_copy1,Inter_pix_copy2,Inter_pix_copy3; |
reg [7:0] Inter_H_window_0_0,Inter_H_window_1_0,Inter_H_window_2_0,Inter_H_window_3_0,Inter_H_window_4_0,Inter_H_window_5_0; |
reg [7:0] Inter_H_window_0_1,Inter_H_window_1_1,Inter_H_window_2_1,Inter_H_window_3_1,Inter_H_window_4_1,Inter_H_window_5_1; |
reg [7:0] Inter_H_window_0_2,Inter_H_window_1_2,Inter_H_window_2_2,Inter_H_window_3_2,Inter_H_window_4_2,Inter_H_window_5_2; |
reg [7:0] Inter_H_window_0_3,Inter_H_window_1_3,Inter_H_window_2_3,Inter_H_window_3_3,Inter_H_window_4_3,Inter_H_window_5_3; |
reg [7:0] Inter_H_window_0_4,Inter_H_window_1_4,Inter_H_window_2_4,Inter_H_window_3_4,Inter_H_window_4_4,Inter_H_window_5_4; |
reg [7:0] Inter_H_window_0_5,Inter_H_window_1_5,Inter_H_window_2_5,Inter_H_window_3_5,Inter_H_window_4_5,Inter_H_window_5_5; |
reg [7:0] Inter_H_window_0_6,Inter_H_window_1_6,Inter_H_window_2_6,Inter_H_window_3_6,Inter_H_window_4_6,Inter_H_window_5_6; |
reg [7:0] Inter_H_window_0_7,Inter_H_window_1_7,Inter_H_window_2_7,Inter_H_window_3_7,Inter_H_window_4_7,Inter_H_window_5_7; |
reg [7:0] Inter_H_window_0_8,Inter_H_window_1_8,Inter_H_window_2_8,Inter_H_window_3_8,Inter_H_window_4_8,Inter_H_window_5_8; |
reg [7:0] Inter_V_window_0,Inter_V_window_1,Inter_V_window_2,Inter_V_window_3,Inter_V_window_4; |
reg [7:0] Inter_V_window_5,Inter_V_window_6,Inter_V_window_7,Inter_V_window_8; |
reg [7:0] Inter_C_window_0_0,Inter_C_window_1_0,Inter_C_window_2_0; |
reg [7:0] Inter_C_window_0_1,Inter_C_window_1_1,Inter_C_window_2_1; |
reg [7:0] Inter_C_window_0_2,Inter_C_window_1_2,Inter_C_window_2_2; |
reg [7:0] Inter_bi_window_0,Inter_bi_window_1,Inter_bi_window_2,Inter_bi_window_3; |
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parameter pos_Int = 4'b0000; |
parameter pos_a = 4'b0100; |
parameter pos_b = 4'b1000; |
parameter pos_c = 4'b1100; |
parameter pos_d = 4'b0001; |
parameter pos_e = 4'b0101; |
parameter pos_f = 4'b1001; |
parameter pos_g = 4'b1101; |
parameter pos_h = 4'b0010; |
parameter pos_i = 4'b0110; |
parameter pos_j = 4'b1010; |
parameter pos_k = 4'b1110; |
parameter pos_n = 4'b0011; |
parameter pos_p = 4'b0111; |
parameter pos_q = 4'b1011; |
parameter pos_r = 4'b1111; |
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//------------------------------- |
//sliding window control |
//------------------------------- |
wire Is_blk4x4_0;//When inter 8x8(or above) predicted: top-left blk4x4 |
//When inter 4x4 predicted: each blk4x4 |
wire Is_blk4x4_1; |
wire Is_blk4x4_2; |
wire Is_blk4x4_3; |
assign Is_blk4x4_0 = (IsInterLuma && (mv_below8x8_curr || (!mv_below8x8_curr && |
blk4x4_rec_counter_1to0 == 2'b00))); //top-left |
assign Is_blk4x4_1 = (IsInterLuma && (!mv_below8x8_curr && blk4x4_rec_counter_1to0 == 2'b01)); //top-right |
assign Is_blk4x4_2 = (IsInterLuma && (!mv_below8x8_curr && blk4x4_rec_counter_1to0 == 2'b10)); //bottom-left |
assign Is_blk4x4_3 = (IsInterLuma && (!mv_below8x8_curr && blk4x4_rec_counter_1to0 == 2'b11)); //bottom-right |
|
//For both luma & chroma,if current pixel is to be directly copied instead of inter calculated, |
//the sliding windows output Inter_pix_copy0 ~ 3 is the inter prediction output |
always @ (IsInterLuma or pos_FracL or blk4x4_inter_calculate_counter |
or Is_blk4x4_0 or Is_blk4x4_1 or Is_blk4x4_2 or Is_blk4x4_3 |
or Is_InterChromaCopy or mv_below8x8_curr |
or Inter_ref_00_00 or Inter_ref_01_00 or Inter_ref_02_00 or Inter_ref_03_00 |
or Inter_ref_00_01 or Inter_ref_01_01 or Inter_ref_02_01 or Inter_ref_03_01 |
or Inter_ref_00_02 or Inter_ref_01_02 or Inter_ref_02_02 or Inter_ref_03_02 |
or Inter_ref_04_02 or Inter_ref_05_02 or Inter_ref_06_02 or Inter_ref_07_02 |
or Inter_ref_08_02 or Inter_ref_09_02 or Inter_ref_00_03 or Inter_ref_01_03 |
or Inter_ref_02_03 or Inter_ref_03_03 or Inter_ref_04_03 or Inter_ref_05_03 |
or Inter_ref_06_03 or Inter_ref_07_03 or Inter_ref_08_03 or Inter_ref_09_03 |
or Inter_ref_02_04 or Inter_ref_03_04 or Inter_ref_04_04 or Inter_ref_05_04 |
or Inter_ref_06_04 or Inter_ref_07_04 or Inter_ref_08_04 or Inter_ref_09_04 |
or Inter_ref_02_05 or Inter_ref_03_05 or Inter_ref_04_05 or Inter_ref_05_05 |
or Inter_ref_06_05 or Inter_ref_07_05 or Inter_ref_08_05 or Inter_ref_09_05 |
or Inter_ref_02_06 or Inter_ref_03_06 or Inter_ref_04_06 or Inter_ref_05_06 |
or Inter_ref_06_06 or Inter_ref_07_06 or Inter_ref_08_06 or Inter_ref_09_06 |
or Inter_ref_02_07 or Inter_ref_03_07 or Inter_ref_04_07 or Inter_ref_05_07 |
or Inter_ref_06_07 or Inter_ref_07_07 or Inter_ref_08_07 or Inter_ref_09_07 |
or Inter_ref_02_08 or Inter_ref_03_08 or Inter_ref_04_08 or Inter_ref_05_08 |
or Inter_ref_06_08 or Inter_ref_07_08 or Inter_ref_08_08 or Inter_ref_09_08 |
or Inter_ref_02_09 or Inter_ref_03_09 or Inter_ref_04_09 or Inter_ref_05_09 |
or Inter_ref_06_09 or Inter_ref_07_09 or Inter_ref_08_09 or Inter_ref_09_09) |
if (IsInterLuma && pos_FracL == `pos_Int) |
case ({Is_blk4x4_0,Is_blk4x4_1,Is_blk4x4_2,Is_blk4x4_3}) |
4'b1000: |
case (blk4x4_inter_calculate_counter) |
4'd4:begin Inter_pix_copy0 <= Inter_ref_02_02; Inter_pix_copy1 <= Inter_ref_02_03; |
Inter_pix_copy2 <= Inter_ref_02_04; Inter_pix_copy3 <= Inter_ref_02_05;end |
4'd3:begin Inter_pix_copy0 <= Inter_ref_03_02; Inter_pix_copy1 <= Inter_ref_03_03; |
Inter_pix_copy2 <= Inter_ref_03_04; Inter_pix_copy3 <= Inter_ref_03_05;end |
4'd2:begin Inter_pix_copy0 <= Inter_ref_04_02; Inter_pix_copy1 <= Inter_ref_04_03; |
Inter_pix_copy2 <= Inter_ref_04_04; Inter_pix_copy3 <= Inter_ref_04_05;end |
4'd1:begin Inter_pix_copy0 <= Inter_ref_05_02; Inter_pix_copy1 <= Inter_ref_05_03; |
Inter_pix_copy2 <= Inter_ref_05_04; Inter_pix_copy3 <= Inter_ref_05_05;end |
default:begin Inter_pix_copy0 <= 0; Inter_pix_copy1 <= 0; |
Inter_pix_copy2 <= 0; Inter_pix_copy3 <= 0;end |
endcase |
4'b0100: |
case (blk4x4_inter_calculate_counter) |
4'd4:begin Inter_pix_copy0 <= Inter_ref_06_02; Inter_pix_copy1 <= Inter_ref_06_03; |
Inter_pix_copy2 <= Inter_ref_06_04; Inter_pix_copy3 <= Inter_ref_06_05;end |
4'd3:begin Inter_pix_copy0 <= Inter_ref_07_02; Inter_pix_copy1 <= Inter_ref_07_03; |
Inter_pix_copy2 <= Inter_ref_07_04; Inter_pix_copy3 <= Inter_ref_07_05;end |
4'd2:begin Inter_pix_copy0 <= Inter_ref_08_02; Inter_pix_copy1 <= Inter_ref_08_03; |
Inter_pix_copy2 <= Inter_ref_08_04; Inter_pix_copy3 <= Inter_ref_08_05;end |
4'd1:begin Inter_pix_copy0 <= Inter_ref_09_02; Inter_pix_copy1 <= Inter_ref_09_03; |
Inter_pix_copy2 <= Inter_ref_09_04; Inter_pix_copy3 <= Inter_ref_09_05;end |
default:begin Inter_pix_copy0 <= 0; Inter_pix_copy1 <= 0; |
Inter_pix_copy2 <= 0; Inter_pix_copy3 <= 0;end |
endcase |
4'b0010: |
case (blk4x4_inter_calculate_counter) |
4'd4:begin Inter_pix_copy0 <= Inter_ref_02_06; Inter_pix_copy1 <= Inter_ref_02_07; |
Inter_pix_copy2 <= Inter_ref_02_08; Inter_pix_copy3 <= Inter_ref_02_09;end |
4'd3:begin Inter_pix_copy0 <= Inter_ref_03_06; Inter_pix_copy1 <= Inter_ref_03_07; |
Inter_pix_copy2 <= Inter_ref_03_08; Inter_pix_copy3 <= Inter_ref_03_09;end |
4'd2:begin Inter_pix_copy0 <= Inter_ref_04_06; Inter_pix_copy1 <= Inter_ref_04_07; |
Inter_pix_copy2 <= Inter_ref_04_08; Inter_pix_copy3 <= Inter_ref_04_09;end |
4'd1:begin Inter_pix_copy0 <= Inter_ref_05_06; Inter_pix_copy1 <= Inter_ref_05_07; |
Inter_pix_copy2 <= Inter_ref_05_08; Inter_pix_copy3 <= Inter_ref_05_09;end |
default:begin Inter_pix_copy0 <= 0; Inter_pix_copy1 <= 0; |
Inter_pix_copy2 <= 0; Inter_pix_copy3 <= 0;end |
endcase |
4'b0001: |
case (blk4x4_inter_calculate_counter) |
4'd4:begin Inter_pix_copy0 <= Inter_ref_06_06; Inter_pix_copy1 <= Inter_ref_06_07; |
Inter_pix_copy2 <= Inter_ref_06_08; Inter_pix_copy3 <= Inter_ref_06_09;end |
4'd3:begin Inter_pix_copy0 <= Inter_ref_07_06; Inter_pix_copy1 <= Inter_ref_07_07; |
Inter_pix_copy2 <= Inter_ref_07_08; Inter_pix_copy3 <= Inter_ref_07_09;end |
4'd2:begin Inter_pix_copy0 <= Inter_ref_08_06; Inter_pix_copy1 <= Inter_ref_08_07; |
Inter_pix_copy2 <= Inter_ref_08_08; Inter_pix_copy3 <= Inter_ref_08_09;end |
4'd1:begin Inter_pix_copy0 <= Inter_ref_09_06; Inter_pix_copy1 <= Inter_ref_09_07; |
Inter_pix_copy2 <= Inter_ref_09_08; Inter_pix_copy3 <= Inter_ref_09_09;end |
default:begin Inter_pix_copy0 <= 0; Inter_pix_copy1 <= 0; |
Inter_pix_copy2 <= 0; Inter_pix_copy3 <= 0;end |
endcase |
default:begin Inter_pix_copy0 <= 0; Inter_pix_copy1 <= 0; |
Inter_pix_copy2 <= 0; Inter_pix_copy3 <= 0;end |
endcase |
else if (Is_InterChromaCopy) |
case (mv_below8x8_curr) |
1'b1://only one cycle |
begin |
Inter_pix_copy0 <= (blk4x4_inter_calculate_counter != 0)? Inter_ref_00_00:0; |
Inter_pix_copy1 <= (blk4x4_inter_calculate_counter != 0)? Inter_ref_01_00:0; |
Inter_pix_copy2 <= (blk4x4_inter_calculate_counter != 0)? Inter_ref_00_01:0; |
Inter_pix_copy3 <= (blk4x4_inter_calculate_counter != 0)? Inter_ref_01_01:0; |
end |
1'b0://4 cycles,each cycle for one blk2x2 in blk2x2-zig-zag order |
case (blk4x4_inter_calculate_counter) |
4'd4: |
begin |
Inter_pix_copy0 <= Inter_ref_00_00; Inter_pix_copy1 <= Inter_ref_01_00; |
Inter_pix_copy2 <= Inter_ref_00_01; Inter_pix_copy3 <= Inter_ref_01_01; |
end |
4'd3: |
begin |
Inter_pix_copy0 <= Inter_ref_02_00; Inter_pix_copy1 <= Inter_ref_03_00; |
Inter_pix_copy2 <= Inter_ref_02_01; Inter_pix_copy3 <= Inter_ref_03_01; |
end |
4'd2: |
begin |
Inter_pix_copy0 <= Inter_ref_00_02; Inter_pix_copy1 <= Inter_ref_01_02; |
Inter_pix_copy2 <= Inter_ref_00_03; Inter_pix_copy3 <= Inter_ref_01_03; |
end |
4'd1: |
begin |
Inter_pix_copy0 <= Inter_ref_02_02; Inter_pix_copy1 <= Inter_ref_03_02; |
Inter_pix_copy2 <= Inter_ref_02_03; Inter_pix_copy3 <= Inter_ref_03_03; |
end |
default: |
begin |
Inter_pix_copy0 <= 0; Inter_pix_copy1 <= 0; Inter_pix_copy2 <= 0; Inter_pix_copy3 <= 0; |
end |
endcase |
endcase |
else |
begin |
Inter_pix_copy0 <= 0; Inter_pix_copy1 <= 0; Inter_pix_copy2 <= 0; Inter_pix_copy3 <= 0; |
end |
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//Horizontal sliding windows:Inter_H_window_0_0 ~ Inter_H_window_5_8 (6x9 windows) |
// Inter_H_window_x_0,Inter_H_window_x_1,Inter_H_window_x_6,Inter_H_window_x_7,Inter_H_window_x_8 |
// are only used for pos_j/pos_i/pos_k/pos_f/pos_q |
//Vertical sliding window:Inter_V_window_0 ~ Inter_V_window_8 |
//Chroma sliding window:Inter_C_window_0 ~ Inter_C_window_3 |
|
//By careful study,we find that pos_b calculate cycle4 needs the same window as pos_a calculate cycl5. |
//Similar cases happens with pos_b and pos_a/pos_c,pos_h and pos_d/pos_n, pos_j and pos_f/pos_q/pos_i/pos_k...... |
|
//Inter_H_window_counter0:for Inter_H_window_x_0/1/6/7/8 sliding window control |
reg [2:0] Inter_H_window_counter0; |
always @ (pos_FracL or blk4x4_inter_calculate_counter) |
if ((pos_FracL == `pos_j && blk4x4_inter_calculate_counter == 4'd5) || |
((pos_FracL == `pos_f || pos_FracL == `pos_q) && blk4x4_inter_calculate_counter == 4'd5) || |
((pos_FracL == `pos_i || pos_FracL == `pos_k) && blk4x4_inter_calculate_counter == 4'd8)) |
Inter_H_window_counter0 <= 3'd4; |
else if ((pos_FracL == `pos_j && blk4x4_inter_calculate_counter == 4'd4) || |
((pos_FracL == `pos_f || pos_FracL == `pos_q) && blk4x4_inter_calculate_counter == 4'd4) || |
((pos_FracL == `pos_i || pos_FracL == `pos_k) && blk4x4_inter_calculate_counter == 4'd6)) |
Inter_H_window_counter0 <= 3'd3; |
else if ((pos_FracL == `pos_j && blk4x4_inter_calculate_counter == 4'd3) || |
((pos_FracL == `pos_f || pos_FracL == `pos_q) && blk4x4_inter_calculate_counter == 4'd3) || |
((pos_FracL == `pos_i || pos_FracL == `pos_k) && blk4x4_inter_calculate_counter == 4'd4)) |
Inter_H_window_counter0 <= 3'd2; |
else if ((pos_FracL == `pos_j && blk4x4_inter_calculate_counter == 4'd2) || |
((pos_FracL == `pos_f || pos_FracL == `pos_q) && blk4x4_inter_calculate_counter == 4'd2) || |
((pos_FracL == `pos_i || pos_FracL == `pos_k) && blk4x4_inter_calculate_counter == 4'd2)) |
Inter_H_window_counter0 <= 3'd1; |
else |
Inter_H_window_counter0 <= 0; |
|
|
//Inter_H_window_x_0,Inter_H_window_x_1 |
//Inter_H_window_x_6,Inter_H_window_x_7,Inter_H_window_x_8 |
//Active only for pos j,i/k/f/q |
always @ (Is_blk4x4_0 or Is_blk4x4_1 or Is_blk4x4_2 or Is_blk4x4_3 or Inter_H_window_counter0 |
|
or Inter_ref_00_00 or Inter_ref_01_00 or Inter_ref_02_00 or Inter_ref_03_00 |
or Inter_ref_04_00 or Inter_ref_05_00 or Inter_ref_06_00 or Inter_ref_07_00 |
or Inter_ref_08_00 or Inter_ref_09_00 or Inter_ref_10_00 or Inter_ref_11_00 or Inter_ref_12_00 |
|
or Inter_ref_00_01 or Inter_ref_01_01 or Inter_ref_02_01 or Inter_ref_03_01 |
or Inter_ref_04_01 or Inter_ref_05_01 or Inter_ref_06_01 or Inter_ref_07_01 |
or Inter_ref_08_01 or Inter_ref_09_01 or Inter_ref_10_01 or Inter_ref_11_01 or Inter_ref_12_01 |
|
or Inter_ref_00_06 or Inter_ref_01_06 or Inter_ref_02_06 or Inter_ref_03_06 |
or Inter_ref_04_06 or Inter_ref_05_06 or Inter_ref_06_06 or Inter_ref_07_06 |
or Inter_ref_08_06 or Inter_ref_09_06 or Inter_ref_10_06 or Inter_ref_11_06 or Inter_ref_12_06 |
|
or Inter_ref_00_07 or Inter_ref_01_07 or Inter_ref_02_07 or Inter_ref_03_07 |
or Inter_ref_04_07 or Inter_ref_05_07 or Inter_ref_06_07 or Inter_ref_07_07 |
or Inter_ref_08_07 or Inter_ref_09_07 or Inter_ref_10_07 or Inter_ref_11_07 or Inter_ref_12_07 |
|
or Inter_ref_00_08 or Inter_ref_01_08 or Inter_ref_02_08 or Inter_ref_03_08 |
or Inter_ref_04_08 or Inter_ref_05_08 or Inter_ref_06_08 or Inter_ref_07_08 |
or Inter_ref_08_08 or Inter_ref_09_08 or Inter_ref_10_08 or Inter_ref_11_08 or Inter_ref_12_08 |
|
or Inter_ref_00_04 or Inter_ref_01_04 or Inter_ref_02_04 or Inter_ref_03_04 |
or Inter_ref_04_04 or Inter_ref_05_04 or Inter_ref_06_04 or Inter_ref_07_04 |
or Inter_ref_08_04 or Inter_ref_09_04 or Inter_ref_10_04 or Inter_ref_11_04 or Inter_ref_12_04 |
|
or Inter_ref_00_05 or Inter_ref_01_05 or Inter_ref_02_05 or Inter_ref_03_05 |
or Inter_ref_04_05 or Inter_ref_05_05 or Inter_ref_06_05 or Inter_ref_07_05 |
or Inter_ref_08_05 or Inter_ref_09_05 or Inter_ref_10_05 or Inter_ref_11_05 or Inter_ref_12_05 |
|
or Inter_ref_00_10 or Inter_ref_01_10 or Inter_ref_02_10 or Inter_ref_03_10 |
or Inter_ref_04_10 or Inter_ref_05_10 or Inter_ref_06_10 or Inter_ref_07_10 |
or Inter_ref_08_10 or Inter_ref_09_10 or Inter_ref_10_10 or Inter_ref_11_10 or Inter_ref_12_10 |
|
or Inter_ref_00_11 or Inter_ref_01_11 or Inter_ref_02_11 or Inter_ref_03_11 |
or Inter_ref_04_11 or Inter_ref_05_11 or Inter_ref_06_11 or Inter_ref_07_11 |
or Inter_ref_08_11 or Inter_ref_09_11 or Inter_ref_10_11 or Inter_ref_11_11 or Inter_ref_12_11 |
|
or Inter_ref_00_12 or Inter_ref_01_12 or Inter_ref_02_12 or Inter_ref_03_12 |
or Inter_ref_04_12 or Inter_ref_05_12 or Inter_ref_06_12 or Inter_ref_07_12 |
or Inter_ref_08_12 or Inter_ref_09_12 or Inter_ref_10_12 or Inter_ref_11_12 or Inter_ref_12_12 |
) |
case ({Is_blk4x4_0,Is_blk4x4_1,Is_blk4x4_2,Is_blk4x4_3}) |
4'b1000: //Left top blk4x4 |
case (Inter_H_window_counter0) |
3'd4: |
begin |
Inter_H_window_0_0 <= Inter_ref_00_00;Inter_H_window_1_0 <= Inter_ref_01_00; |
Inter_H_window_2_0 <= Inter_ref_02_00;Inter_H_window_3_0 <= Inter_ref_03_00; |
Inter_H_window_4_0 <= Inter_ref_04_00;Inter_H_window_5_0 <= Inter_ref_05_00; |
|
Inter_H_window_0_1 <= Inter_ref_00_01;Inter_H_window_1_1 <= Inter_ref_01_01; |
Inter_H_window_2_1 <= Inter_ref_02_01;Inter_H_window_3_1 <= Inter_ref_03_01; |
Inter_H_window_4_1 <= Inter_ref_04_01;Inter_H_window_5_1 <= Inter_ref_05_01; |
|
Inter_H_window_0_6 <= Inter_ref_00_06;Inter_H_window_1_6 <= Inter_ref_01_06; |
Inter_H_window_2_6 <= Inter_ref_02_06;Inter_H_window_3_6 <= Inter_ref_03_06; |
Inter_H_window_4_6 <= Inter_ref_04_06;Inter_H_window_5_6 <= Inter_ref_05_06; |
|
Inter_H_window_0_7 <= Inter_ref_00_07;Inter_H_window_1_7 <= Inter_ref_01_07; |
Inter_H_window_2_7 <= Inter_ref_02_07;Inter_H_window_3_7 <= Inter_ref_03_07; |
Inter_H_window_4_7 <= Inter_ref_04_07;Inter_H_window_5_7 <= Inter_ref_05_07; |
|
Inter_H_window_0_8 <= Inter_ref_00_08;Inter_H_window_1_8 <= Inter_ref_01_08; |
Inter_H_window_2_8 <= Inter_ref_02_08;Inter_H_window_3_8 <= Inter_ref_03_08; |
Inter_H_window_4_8 <= Inter_ref_04_08;Inter_H_window_5_8 <= Inter_ref_05_08; |
end |
3'd3: |
begin |
Inter_H_window_0_0 <= Inter_ref_01_00;Inter_H_window_1_0 <= Inter_ref_02_00; |
Inter_H_window_2_0 <= Inter_ref_03_00;Inter_H_window_3_0 <= Inter_ref_04_00; |
Inter_H_window_4_0 <= Inter_ref_05_00;Inter_H_window_5_0 <= Inter_ref_06_00; |
|
Inter_H_window_0_1 <= Inter_ref_01_01;Inter_H_window_1_1 <= Inter_ref_02_01; |
Inter_H_window_2_1 <= Inter_ref_03_01;Inter_H_window_3_1 <= Inter_ref_04_01; |
Inter_H_window_4_1 <= Inter_ref_05_01;Inter_H_window_5_1 <= Inter_ref_06_01; |
|
Inter_H_window_0_6 <= Inter_ref_01_06;Inter_H_window_1_6 <= Inter_ref_02_06; |
Inter_H_window_2_6 <= Inter_ref_03_06;Inter_H_window_3_6 <= Inter_ref_04_06; |
Inter_H_window_4_6 <= Inter_ref_05_06;Inter_H_window_5_6 <= Inter_ref_06_06; |
|
Inter_H_window_0_7 <= Inter_ref_01_07;Inter_H_window_1_7 <= Inter_ref_02_07; |
Inter_H_window_2_7 <= Inter_ref_03_07;Inter_H_window_3_7 <= Inter_ref_04_07; |
Inter_H_window_4_7 <= Inter_ref_05_07;Inter_H_window_5_7 <= Inter_ref_06_07; |
|
Inter_H_window_0_8 <= Inter_ref_01_08;Inter_H_window_1_8 <= Inter_ref_02_08; |
Inter_H_window_2_8 <= Inter_ref_03_08;Inter_H_window_3_8 <= Inter_ref_04_08; |
Inter_H_window_4_8 <= Inter_ref_05_08;Inter_H_window_5_8 <= Inter_ref_06_08; |
end |
3'd2: |
begin |
Inter_H_window_0_0 <= Inter_ref_02_00;Inter_H_window_1_0 <= Inter_ref_03_00; |
Inter_H_window_2_0 <= Inter_ref_04_00;Inter_H_window_3_0 <= Inter_ref_05_00; |
Inter_H_window_4_0 <= Inter_ref_06_00;Inter_H_window_5_0 <= Inter_ref_07_00; |
|
Inter_H_window_0_1 <= Inter_ref_02_01;Inter_H_window_1_1 <= Inter_ref_03_01; |
Inter_H_window_2_1 <= Inter_ref_04_01;Inter_H_window_3_1 <= Inter_ref_05_01; |
Inter_H_window_4_1 <= Inter_ref_06_01;Inter_H_window_5_1 <= Inter_ref_07_01; |
|
Inter_H_window_0_6 <= Inter_ref_02_06;Inter_H_window_1_6 <= Inter_ref_03_06; |
Inter_H_window_2_6 <= Inter_ref_04_06;Inter_H_window_3_6 <= Inter_ref_05_06; |
Inter_H_window_4_6 <= Inter_ref_06_06;Inter_H_window_5_6 <= Inter_ref_07_06; |
|
Inter_H_window_0_7 <= Inter_ref_02_07;Inter_H_window_1_7 <= Inter_ref_03_07; |
Inter_H_window_2_7 <= Inter_ref_04_07;Inter_H_window_3_7 <= Inter_ref_05_07; |
Inter_H_window_4_7 <= Inter_ref_06_07;Inter_H_window_5_7 <= Inter_ref_07_07; |
|
Inter_H_window_0_8 <= Inter_ref_02_08;Inter_H_window_1_8 <= Inter_ref_03_08; |
Inter_H_window_2_8 <= Inter_ref_04_08;Inter_H_window_3_8 <= Inter_ref_05_08; |
Inter_H_window_4_8 <= Inter_ref_06_08;Inter_H_window_5_8 <= Inter_ref_07_08; |
end |
3'd1: |
begin |
Inter_H_window_0_0 <= Inter_ref_03_00;Inter_H_window_1_0 <= Inter_ref_04_00; |
Inter_H_window_2_0 <= Inter_ref_05_00;Inter_H_window_3_0 <= Inter_ref_06_00; |
Inter_H_window_4_0 <= Inter_ref_07_00;Inter_H_window_5_0 <= Inter_ref_08_00; |
|
Inter_H_window_0_1 <= Inter_ref_03_01;Inter_H_window_1_1 <= Inter_ref_04_01; |
Inter_H_window_2_1 <= Inter_ref_05_01;Inter_H_window_3_1 <= Inter_ref_06_01; |
Inter_H_window_4_1 <= Inter_ref_07_01;Inter_H_window_5_1 <= Inter_ref_08_01; |
|
Inter_H_window_0_6 <= Inter_ref_03_06;Inter_H_window_1_6 <= Inter_ref_04_06; |
Inter_H_window_2_6 <= Inter_ref_05_06;Inter_H_window_3_6 <= Inter_ref_06_06; |
Inter_H_window_4_6 <= Inter_ref_07_06;Inter_H_window_5_6 <= Inter_ref_08_06; |
|
Inter_H_window_0_7 <= Inter_ref_03_07;Inter_H_window_1_7 <= Inter_ref_04_07; |
Inter_H_window_2_7 <= Inter_ref_05_07;Inter_H_window_3_7 <= Inter_ref_06_07; |
Inter_H_window_4_7 <= Inter_ref_07_07;Inter_H_window_5_7 <= Inter_ref_08_07; |
|
Inter_H_window_0_8 <= Inter_ref_03_08;Inter_H_window_1_8 <= Inter_ref_04_08; |
Inter_H_window_2_8 <= Inter_ref_05_08;Inter_H_window_3_8 <= Inter_ref_06_08; |
Inter_H_window_4_8 <= Inter_ref_07_08;Inter_H_window_5_8 <= Inter_ref_08_08; |
end |
default: |
begin |
Inter_H_window_0_0 <= 0;Inter_H_window_1_0 <= 0;Inter_H_window_2_0 <= 0; |
Inter_H_window_3_0 <= 0;Inter_H_window_4_0 <= 0;Inter_H_window_5_0 <= 0; |
|
Inter_H_window_0_1 <= 0;Inter_H_window_1_1 <= 0;Inter_H_window_2_1 <= 0; |
Inter_H_window_3_1 <= 0;Inter_H_window_4_1 <= 0;Inter_H_window_5_1 <= 0; |
|
Inter_H_window_0_6 <= 0;Inter_H_window_1_6 <= 0;Inter_H_window_2_6 <= 0; |
Inter_H_window_3_6 <= 0;Inter_H_window_4_6 <= 0;Inter_H_window_5_6 <= 0; |
|
Inter_H_window_0_7 <= 0;Inter_H_window_1_7 <= 0;Inter_H_window_2_7 <= 0; |
Inter_H_window_3_7 <= 0;Inter_H_window_4_7 <= 0;Inter_H_window_5_7 <= 0; |
|
Inter_H_window_0_8 <= 0;Inter_H_window_1_8 <= 0;Inter_H_window_2_8 <= 0; |
Inter_H_window_3_8 <= 0;Inter_H_window_4_8 <= 0;Inter_H_window_5_8 <= 0; |
end |
endcase |
4'b0100: //Right top blk8x8 |
case (Inter_H_window_counter0) |
3'd4: |
begin |
Inter_H_window_0_0 <= Inter_ref_04_00;Inter_H_window_1_0 <= Inter_ref_05_00; |
Inter_H_window_2_0 <= Inter_ref_06_00;Inter_H_window_3_0 <= Inter_ref_07_00; |
Inter_H_window_4_0 <= Inter_ref_08_00;Inter_H_window_5_0 <= Inter_ref_09_00; |
|
Inter_H_window_0_1 <= Inter_ref_04_01;Inter_H_window_1_1 <= Inter_ref_05_01; |
Inter_H_window_2_1 <= Inter_ref_06_01;Inter_H_window_3_1 <= Inter_ref_07_01; |
Inter_H_window_4_1 <= Inter_ref_08_01;Inter_H_window_5_1 <= Inter_ref_09_01; |
|
Inter_H_window_0_6 <= Inter_ref_04_06;Inter_H_window_1_6 <= Inter_ref_05_06; |
Inter_H_window_2_6 <= Inter_ref_06_06;Inter_H_window_3_6 <= Inter_ref_07_06; |
Inter_H_window_4_6 <= Inter_ref_08_06;Inter_H_window_5_6 <= Inter_ref_09_06; |
|
Inter_H_window_0_7 <= Inter_ref_04_07;Inter_H_window_1_7 <= Inter_ref_05_07; |
Inter_H_window_2_7 <= Inter_ref_06_07;Inter_H_window_3_7 <= Inter_ref_07_07; |
Inter_H_window_4_7 <= Inter_ref_08_07;Inter_H_window_5_7 <= Inter_ref_09_07; |
|
Inter_H_window_0_8 <= Inter_ref_04_08;Inter_H_window_1_8 <= Inter_ref_05_08; |
Inter_H_window_2_8 <= Inter_ref_06_08;Inter_H_window_3_8 <= Inter_ref_07_08; |
Inter_H_window_4_8 <= Inter_ref_08_08;Inter_H_window_5_8 <= Inter_ref_09_08; |
end |
3'd3: |
begin |
Inter_H_window_0_0 <= Inter_ref_05_00;Inter_H_window_1_0 <= Inter_ref_06_00; |
Inter_H_window_2_0 <= Inter_ref_07_00;Inter_H_window_3_0 <= Inter_ref_08_00; |
Inter_H_window_4_0 <= Inter_ref_09_00;Inter_H_window_5_0 <= Inter_ref_10_00; |
|
Inter_H_window_0_1 <= Inter_ref_05_01;Inter_H_window_1_1 <= Inter_ref_06_01; |
Inter_H_window_2_1 <= Inter_ref_07_01;Inter_H_window_3_1 <= Inter_ref_08_01; |
Inter_H_window_4_1 <= Inter_ref_09_01;Inter_H_window_5_1 <= Inter_ref_10_01; |
|
Inter_H_window_0_6 <= Inter_ref_05_06;Inter_H_window_1_6 <= Inter_ref_06_06; |
Inter_H_window_2_6 <= Inter_ref_07_06;Inter_H_window_3_6 <= Inter_ref_08_06; |
Inter_H_window_4_6 <= Inter_ref_09_06;Inter_H_window_5_6 <= Inter_ref_10_06; |
|
Inter_H_window_0_7 <= Inter_ref_05_07;Inter_H_window_1_7 <= Inter_ref_06_07; |
Inter_H_window_2_7 <= Inter_ref_07_07;Inter_H_window_3_7 <= Inter_ref_08_07; |
Inter_H_window_4_7 <= Inter_ref_09_07;Inter_H_window_5_7 <= Inter_ref_10_07; |
|
Inter_H_window_0_8 <= Inter_ref_05_08;Inter_H_window_1_8 <= Inter_ref_06_08; |
Inter_H_window_2_8 <= Inter_ref_07_08;Inter_H_window_3_8 <= Inter_ref_08_08; |
Inter_H_window_4_8 <= Inter_ref_09_08;Inter_H_window_5_8 <= Inter_ref_10_08; |
end |
3'd2: |
begin |
Inter_H_window_0_0 <= Inter_ref_06_00;Inter_H_window_1_0 <= Inter_ref_07_00; |
Inter_H_window_2_0 <= Inter_ref_08_00;Inter_H_window_3_0 <= Inter_ref_09_00; |
Inter_H_window_4_0 <= Inter_ref_10_00;Inter_H_window_5_0 <= Inter_ref_11_00; |
|
Inter_H_window_0_1 <= Inter_ref_06_01;Inter_H_window_1_1 <= Inter_ref_07_01; |
Inter_H_window_2_1 <= Inter_ref_08_01;Inter_H_window_3_1 <= Inter_ref_09_01; |
Inter_H_window_4_1 <= Inter_ref_10_01;Inter_H_window_5_1 <= Inter_ref_11_01; |
|
Inter_H_window_0_6 <= Inter_ref_06_06;Inter_H_window_1_6 <= Inter_ref_07_06; |
Inter_H_window_2_6 <= Inter_ref_08_06;Inter_H_window_3_6 <= Inter_ref_09_06; |
Inter_H_window_4_6 <= Inter_ref_10_06;Inter_H_window_5_6 <= Inter_ref_11_06; |
|
Inter_H_window_0_7 <= Inter_ref_06_07;Inter_H_window_1_7 <= Inter_ref_07_07; |
Inter_H_window_2_7 <= Inter_ref_08_07;Inter_H_window_3_7 <= Inter_ref_09_07; |
Inter_H_window_4_7 <= Inter_ref_10_07;Inter_H_window_5_7 <= Inter_ref_11_07; |
|
Inter_H_window_0_8 <= Inter_ref_06_08;Inter_H_window_1_8 <= Inter_ref_07_08; |
Inter_H_window_2_8 <= Inter_ref_08_08;Inter_H_window_3_8 <= Inter_ref_09_08; |
Inter_H_window_4_8 <= Inter_ref_10_08;Inter_H_window_5_8 <= Inter_ref_11_08; |
end |
3'd1: |
begin |
Inter_H_window_0_0 <= Inter_ref_07_00;Inter_H_window_1_0 <= Inter_ref_08_00; |
Inter_H_window_2_0 <= Inter_ref_09_00;Inter_H_window_3_0 <= Inter_ref_10_00; |
Inter_H_window_4_0 <= Inter_ref_11_00;Inter_H_window_5_0 <= Inter_ref_12_00; |
|
Inter_H_window_0_1 <= Inter_ref_07_01;Inter_H_window_1_1 <= Inter_ref_08_01; |
Inter_H_window_2_1 <= Inter_ref_09_01;Inter_H_window_3_1 <= Inter_ref_10_01; |
Inter_H_window_4_1 <= Inter_ref_11_01;Inter_H_window_5_1 <= Inter_ref_12_01; |
|
Inter_H_window_0_6 <= Inter_ref_07_06;Inter_H_window_1_6 <= Inter_ref_08_06; |
Inter_H_window_2_6 <= Inter_ref_09_06;Inter_H_window_3_6 <= Inter_ref_10_06; |
Inter_H_window_4_6 <= Inter_ref_11_06;Inter_H_window_5_6 <= Inter_ref_12_06; |
|
Inter_H_window_0_7 <= Inter_ref_07_07;Inter_H_window_1_7 <= Inter_ref_08_07; |
Inter_H_window_2_7 <= Inter_ref_09_07;Inter_H_window_3_7 <= Inter_ref_10_07; |
Inter_H_window_4_7 <= Inter_ref_11_07;Inter_H_window_5_7 <= Inter_ref_12_07; |
|
Inter_H_window_0_8 <= Inter_ref_07_08;Inter_H_window_1_8 <= Inter_ref_08_08; |
Inter_H_window_2_8 <= Inter_ref_09_08;Inter_H_window_3_8 <= Inter_ref_10_08; |
Inter_H_window_4_8 <= Inter_ref_11_08;Inter_H_window_5_8 <= Inter_ref_12_08; |
end |
default: |
begin |
Inter_H_window_0_0 <= 0;Inter_H_window_1_0 <= 0;Inter_H_window_2_0 <= 0; |
Inter_H_window_3_0 <= 0;Inter_H_window_4_0 <= 0;Inter_H_window_5_0 <= 0; |
|
Inter_H_window_0_1 <= 0;Inter_H_window_1_1 <= 0;Inter_H_window_2_1 <= 0; |
Inter_H_window_3_1 <= 0;Inter_H_window_4_1 <= 0;Inter_H_window_5_1 <= 0; |
|
Inter_H_window_0_6 <= 0;Inter_H_window_1_6 <= 0;Inter_H_window_2_6 <= 0; |
Inter_H_window_3_6 <= 0;Inter_H_window_4_6 <= 0;Inter_H_window_5_6 <= 0; |
|
Inter_H_window_0_7 <= 0;Inter_H_window_1_7 <= 0;Inter_H_window_2_7 <= 0; |
Inter_H_window_3_7 <= 0;Inter_H_window_4_7 <= 0;Inter_H_window_5_7 <= 0; |
|
Inter_H_window_0_8 <= 0;Inter_H_window_1_8 <= 0;Inter_H_window_2_8 <= 0; |
Inter_H_window_3_8 <= 0;Inter_H_window_4_8 <= 0;Inter_H_window_5_8 <= 0; |
end |
endcase |
4'b0010: //Left bottom blk4x4 |
case (Inter_H_window_counter0) |
3'd4: |
begin |
Inter_H_window_0_0 <= Inter_ref_00_04;Inter_H_window_1_0 <= Inter_ref_01_04; |
Inter_H_window_2_0 <= Inter_ref_02_04;Inter_H_window_3_0 <= Inter_ref_03_04; |
Inter_H_window_4_0 <= Inter_ref_04_04;Inter_H_window_5_0 <= Inter_ref_05_04; |
|
Inter_H_window_0_1 <= Inter_ref_00_05;Inter_H_window_1_1 <= Inter_ref_01_05; |
Inter_H_window_2_1 <= Inter_ref_02_05;Inter_H_window_3_1 <= Inter_ref_03_05; |
Inter_H_window_4_1 <= Inter_ref_04_05;Inter_H_window_5_1 <= Inter_ref_05_05; |
|
Inter_H_window_0_6 <= Inter_ref_00_10;Inter_H_window_1_6 <= Inter_ref_01_10; |
Inter_H_window_2_6 <= Inter_ref_02_10;Inter_H_window_3_6 <= Inter_ref_03_10; |
Inter_H_window_4_6 <= Inter_ref_04_10;Inter_H_window_5_6 <= Inter_ref_05_10; |
|
Inter_H_window_0_7 <= Inter_ref_00_11;Inter_H_window_1_7 <= Inter_ref_01_11; |
Inter_H_window_2_7 <= Inter_ref_02_11;Inter_H_window_3_7 <= Inter_ref_03_11; |
Inter_H_window_4_7 <= Inter_ref_04_11;Inter_H_window_5_7 <= Inter_ref_05_11; |
|
Inter_H_window_0_8 <= Inter_ref_00_12;Inter_H_window_1_8 <= Inter_ref_01_12; |
Inter_H_window_2_8 <= Inter_ref_02_12;Inter_H_window_3_8 <= Inter_ref_03_12; |
Inter_H_window_4_8 <= Inter_ref_04_12;Inter_H_window_5_8 <= Inter_ref_05_12; |
end |
3'd3: |
begin |
Inter_H_window_0_0 <= Inter_ref_01_04;Inter_H_window_1_0 <= Inter_ref_02_04; |
Inter_H_window_2_0 <= Inter_ref_03_04;Inter_H_window_3_0 <= Inter_ref_04_04; |
Inter_H_window_4_0 <= Inter_ref_05_04;Inter_H_window_5_0 <= Inter_ref_06_04; |
|
Inter_H_window_0_1 <= Inter_ref_01_05;Inter_H_window_1_1 <= Inter_ref_02_05; |
Inter_H_window_2_1 <= Inter_ref_03_05;Inter_H_window_3_1 <= Inter_ref_04_05; |
Inter_H_window_4_1 <= Inter_ref_05_05;Inter_H_window_5_1 <= Inter_ref_06_05; |
|
Inter_H_window_0_6 <= Inter_ref_01_10;Inter_H_window_1_6 <= Inter_ref_02_10; |
Inter_H_window_2_6 <= Inter_ref_03_10;Inter_H_window_3_6 <= Inter_ref_04_10; |
Inter_H_window_4_6 <= Inter_ref_05_10;Inter_H_window_5_6 <= Inter_ref_06_10; |
|
Inter_H_window_0_7 <= Inter_ref_01_11;Inter_H_window_1_7 <= Inter_ref_02_11; |
Inter_H_window_2_7 <= Inter_ref_03_11;Inter_H_window_3_7 <= Inter_ref_04_11; |
Inter_H_window_4_7 <= Inter_ref_05_11;Inter_H_window_5_7 <= Inter_ref_06_11; |
|
Inter_H_window_0_8 <= Inter_ref_01_12;Inter_H_window_1_8 <= Inter_ref_02_12; |
Inter_H_window_2_8 <= Inter_ref_03_12;Inter_H_window_3_8 <= Inter_ref_04_12; |
Inter_H_window_4_8 <= Inter_ref_05_12;Inter_H_window_5_8 <= Inter_ref_06_12; |
end |
3'd2: |
begin |
Inter_H_window_0_0 <= Inter_ref_02_04;Inter_H_window_1_0 <= Inter_ref_03_04; |
Inter_H_window_2_0 <= Inter_ref_04_04;Inter_H_window_3_0 <= Inter_ref_05_04; |
Inter_H_window_4_0 <= Inter_ref_06_04;Inter_H_window_5_0 <= Inter_ref_07_04; |
|
Inter_H_window_0_1 <= Inter_ref_02_05;Inter_H_window_1_1 <= Inter_ref_03_05; |
Inter_H_window_2_1 <= Inter_ref_04_05;Inter_H_window_3_1 <= Inter_ref_05_05; |
Inter_H_window_4_1 <= Inter_ref_06_05;Inter_H_window_5_1 <= Inter_ref_07_05; |
|
Inter_H_window_0_6 <= Inter_ref_02_10;Inter_H_window_1_6 <= Inter_ref_03_10; |
Inter_H_window_2_6 <= Inter_ref_04_10;Inter_H_window_3_6 <= Inter_ref_05_10; |
Inter_H_window_4_6 <= Inter_ref_06_10;Inter_H_window_5_6 <= Inter_ref_07_10; |
|
Inter_H_window_0_7 <= Inter_ref_02_11;Inter_H_window_1_7 <= Inter_ref_03_11; |
Inter_H_window_2_7 <= Inter_ref_04_11;Inter_H_window_3_7 <= Inter_ref_05_11; |
Inter_H_window_4_7 <= Inter_ref_06_11;Inter_H_window_5_7 <= Inter_ref_07_11; |
|
Inter_H_window_0_8 <= Inter_ref_02_12;Inter_H_window_1_8 <= Inter_ref_03_12; |
Inter_H_window_2_8 <= Inter_ref_04_12;Inter_H_window_3_8 <= Inter_ref_05_12; |
Inter_H_window_4_8 <= Inter_ref_06_12;Inter_H_window_5_8 <= Inter_ref_07_12; |
end |
3'd1: |
begin |
Inter_H_window_0_0 <= Inter_ref_03_04;Inter_H_window_1_0 <= Inter_ref_04_04; |
Inter_H_window_2_0 <= Inter_ref_05_04;Inter_H_window_3_0 <= Inter_ref_06_04; |
Inter_H_window_4_0 <= Inter_ref_07_04;Inter_H_window_5_0 <= Inter_ref_08_04; |
|
Inter_H_window_0_1 <= Inter_ref_03_05;Inter_H_window_1_1 <= Inter_ref_04_05; |
Inter_H_window_2_1 <= Inter_ref_05_05;Inter_H_window_3_1 <= Inter_ref_06_05; |
Inter_H_window_4_1 <= Inter_ref_07_05;Inter_H_window_5_1 <= Inter_ref_08_05; |
|
Inter_H_window_0_6 <= Inter_ref_03_10;Inter_H_window_1_6 <= Inter_ref_04_10; |
Inter_H_window_2_6 <= Inter_ref_05_10;Inter_H_window_3_6 <= Inter_ref_06_10; |
Inter_H_window_4_6 <= Inter_ref_07_10;Inter_H_window_5_6 <= Inter_ref_08_10; |
|
Inter_H_window_0_7 <= Inter_ref_03_11;Inter_H_window_1_7 <= Inter_ref_04_11; |
Inter_H_window_2_7 <= Inter_ref_05_11;Inter_H_window_3_7 <= Inter_ref_06_11; |
Inter_H_window_4_7 <= Inter_ref_07_11;Inter_H_window_5_7 <= Inter_ref_08_11; |
|
Inter_H_window_0_8 <= Inter_ref_03_12;Inter_H_window_1_8 <= Inter_ref_04_12; |
Inter_H_window_2_8 <= Inter_ref_05_12;Inter_H_window_3_8 <= Inter_ref_06_12; |
Inter_H_window_4_8 <= Inter_ref_07_12;Inter_H_window_5_8 <= Inter_ref_08_12; |
end |
default: |
begin |
Inter_H_window_0_0 <= 0;Inter_H_window_1_0 <= 0;Inter_H_window_2_0 <= 0; |
Inter_H_window_3_0 <= 0;Inter_H_window_4_0 <= 0;Inter_H_window_5_0 <= 0; |
|
Inter_H_window_0_1 <= 0;Inter_H_window_1_1 <= 0;Inter_H_window_2_1 <= 0; |
Inter_H_window_3_1 <= 0;Inter_H_window_4_1 <= 0;Inter_H_window_5_1 <= 0; |
|
Inter_H_window_0_6 <= 0;Inter_H_window_1_6 <= 0;Inter_H_window_2_6 <= 0; |
Inter_H_window_3_6 <= 0;Inter_H_window_4_6 <= 0;Inter_H_window_5_6 <= 0; |
|
Inter_H_window_0_7 <= 0;Inter_H_window_1_7 <= 0;Inter_H_window_2_7 <= 0; |
Inter_H_window_3_7 <= 0;Inter_H_window_4_7 <= 0;Inter_H_window_5_7 <= 0; |
|
Inter_H_window_0_8 <= 0;Inter_H_window_1_8 <= 0;Inter_H_window_2_8 <= 0; |
Inter_H_window_3_8 <= 0;Inter_H_window_4_8 <= 0;Inter_H_window_5_8 <= 0; |
end |
endcase |
4'b0001: //Right bottom blk4x4 |
case (Inter_H_window_counter0) |
3'd4: |
begin |
Inter_H_window_0_0 <= Inter_ref_04_04;Inter_H_window_1_0 <= Inter_ref_05_04; |
Inter_H_window_2_0 <= Inter_ref_06_04;Inter_H_window_3_0 <= Inter_ref_07_04; |
Inter_H_window_4_0 <= Inter_ref_08_04;Inter_H_window_5_0 <= Inter_ref_09_04; |
|
Inter_H_window_0_1 <= Inter_ref_04_05;Inter_H_window_1_1 <= Inter_ref_05_05; |
Inter_H_window_2_1 <= Inter_ref_06_05;Inter_H_window_3_1 <= Inter_ref_07_05; |
Inter_H_window_4_1 <= Inter_ref_08_05;Inter_H_window_5_1 <= Inter_ref_09_05; |
|
Inter_H_window_0_6 <= Inter_ref_04_10;Inter_H_window_1_6 <= Inter_ref_05_10; |
Inter_H_window_2_6 <= Inter_ref_06_10;Inter_H_window_3_6 <= Inter_ref_07_10; |
Inter_H_window_4_6 <= Inter_ref_08_10;Inter_H_window_5_6 <= Inter_ref_09_10; |
|
Inter_H_window_0_7 <= Inter_ref_04_11;Inter_H_window_1_7 <= Inter_ref_05_11; |
Inter_H_window_2_7 <= Inter_ref_06_11;Inter_H_window_3_7 <= Inter_ref_07_11; |
Inter_H_window_4_7 <= Inter_ref_08_11;Inter_H_window_5_7 <= Inter_ref_09_11; |
|
Inter_H_window_0_8 <= Inter_ref_04_12;Inter_H_window_1_8 <= Inter_ref_05_12; |
Inter_H_window_2_8 <= Inter_ref_06_12;Inter_H_window_3_8 <= Inter_ref_07_12; |
Inter_H_window_4_8 <= Inter_ref_08_12;Inter_H_window_5_8 <= Inter_ref_09_12; |
end |
3'd3: |
begin |
Inter_H_window_0_0 <= Inter_ref_05_04;Inter_H_window_1_0 <= Inter_ref_06_04; |
Inter_H_window_2_0 <= Inter_ref_07_04;Inter_H_window_3_0 <= Inter_ref_08_04; |
Inter_H_window_4_0 <= Inter_ref_09_04;Inter_H_window_5_0 <= Inter_ref_10_04; |
|
Inter_H_window_0_1 <= Inter_ref_05_05;Inter_H_window_1_1 <= Inter_ref_06_05; |
Inter_H_window_2_1 <= Inter_ref_07_05;Inter_H_window_3_1 <= Inter_ref_08_05; |
Inter_H_window_4_1 <= Inter_ref_09_05;Inter_H_window_5_1 <= Inter_ref_10_05; |
|
Inter_H_window_0_6 <= Inter_ref_05_10;Inter_H_window_1_6 <= Inter_ref_06_10; |
Inter_H_window_2_6 <= Inter_ref_07_10;Inter_H_window_3_6 <= Inter_ref_08_10; |
Inter_H_window_4_6 <= Inter_ref_09_10;Inter_H_window_5_6 <= Inter_ref_10_10; |
|
Inter_H_window_0_7 <= Inter_ref_05_11;Inter_H_window_1_7 <= Inter_ref_06_11; |
Inter_H_window_2_7 <= Inter_ref_07_11;Inter_H_window_3_7 <= Inter_ref_08_11; |
Inter_H_window_4_7 <= Inter_ref_09_11;Inter_H_window_5_7 <= Inter_ref_10_11; |
|
Inter_H_window_0_8 <= Inter_ref_05_12;Inter_H_window_1_8 <= Inter_ref_06_12; |
Inter_H_window_2_8 <= Inter_ref_07_12;Inter_H_window_3_8 <= Inter_ref_08_12; |
Inter_H_window_4_8 <= Inter_ref_09_12;Inter_H_window_5_8 <= Inter_ref_10_12; |
end |
3'd2: |
begin |
Inter_H_window_0_0 <= Inter_ref_06_04;Inter_H_window_1_0 <= Inter_ref_07_04; |
Inter_H_window_2_0 <= Inter_ref_08_04;Inter_H_window_3_0 <= Inter_ref_09_04; |
Inter_H_window_4_0 <= Inter_ref_10_04;Inter_H_window_5_0 <= Inter_ref_11_04; |
|
Inter_H_window_0_1 <= Inter_ref_06_05;Inter_H_window_1_1 <= Inter_ref_07_05; |
Inter_H_window_2_1 <= Inter_ref_08_05;Inter_H_window_3_1 <= Inter_ref_09_05; |
Inter_H_window_4_1 <= Inter_ref_10_05;Inter_H_window_5_1 <= Inter_ref_11_05; |
|
Inter_H_window_0_6 <= Inter_ref_06_10;Inter_H_window_1_6 <= Inter_ref_07_10; |
Inter_H_window_2_6 <= Inter_ref_08_10;Inter_H_window_3_6 <= Inter_ref_09_10; |
Inter_H_window_4_6 <= Inter_ref_10_10;Inter_H_window_5_6 <= Inter_ref_11_10; |
|
Inter_H_window_0_7 <= Inter_ref_06_11;Inter_H_window_1_7 <= Inter_ref_07_11; |
Inter_H_window_2_7 <= Inter_ref_08_11;Inter_H_window_3_7 <= Inter_ref_09_11; |
Inter_H_window_4_7 <= Inter_ref_10_11;Inter_H_window_5_7 <= Inter_ref_11_11; |
|
Inter_H_window_0_8 <= Inter_ref_06_12;Inter_H_window_1_8 <= Inter_ref_07_12; |
Inter_H_window_2_8 <= Inter_ref_08_12;Inter_H_window_3_8 <= Inter_ref_09_12; |
Inter_H_window_4_8 <= Inter_ref_10_12;Inter_H_window_5_8 <= Inter_ref_11_12; |
end |
3'd1: |
begin |
Inter_H_window_0_0 <= Inter_ref_07_04;Inter_H_window_1_0 <= Inter_ref_08_04; |
Inter_H_window_2_0 <= Inter_ref_09_04;Inter_H_window_3_0 <= Inter_ref_10_04; |
Inter_H_window_4_0 <= Inter_ref_11_04;Inter_H_window_5_0 <= Inter_ref_12_04; |
|
Inter_H_window_0_1 <= Inter_ref_07_05;Inter_H_window_1_1 <= Inter_ref_08_05; |
Inter_H_window_2_1 <= Inter_ref_09_05;Inter_H_window_3_1 <= Inter_ref_10_05; |
Inter_H_window_4_1 <= Inter_ref_11_05;Inter_H_window_5_1 <= Inter_ref_12_05; |
|
Inter_H_window_0_6 <= Inter_ref_07_10;Inter_H_window_1_6 <= Inter_ref_08_10; |
Inter_H_window_2_6 <= Inter_ref_09_10;Inter_H_window_3_6 <= Inter_ref_10_10; |
Inter_H_window_4_6 <= Inter_ref_11_10;Inter_H_window_5_6 <= Inter_ref_12_10; |
|
Inter_H_window_0_7 <= Inter_ref_07_11;Inter_H_window_1_7 <= Inter_ref_08_11; |
Inter_H_window_2_7 <= Inter_ref_09_11;Inter_H_window_3_7 <= Inter_ref_10_11; |
Inter_H_window_4_7 <= Inter_ref_11_11;Inter_H_window_5_7 <= Inter_ref_12_11; |
|
Inter_H_window_0_8 <= Inter_ref_07_12;Inter_H_window_1_8 <= Inter_ref_08_12; |
Inter_H_window_2_8 <= Inter_ref_09_12;Inter_H_window_3_8 <= Inter_ref_10_12; |
Inter_H_window_4_8 <= Inter_ref_11_12;Inter_H_window_5_8 <= Inter_ref_12_12; |
end |
default: |
begin |
Inter_H_window_0_0 <= 0;Inter_H_window_1_0 <= 0;Inter_H_window_2_0 <= 0; |
Inter_H_window_3_0 <= 0;Inter_H_window_4_0 <= 0;Inter_H_window_5_0 <= 0; |
|
Inter_H_window_0_1 <= 0;Inter_H_window_1_1 <= 0;Inter_H_window_2_1 <= 0; |
Inter_H_window_3_1 <= 0;Inter_H_window_4_1 <= 0;Inter_H_window_5_1 <= 0; |
|
Inter_H_window_0_6 <= 0;Inter_H_window_1_6 <= 0;Inter_H_window_2_6 <= 0; |
Inter_H_window_3_6 <= 0;Inter_H_window_4_6 <= 0;Inter_H_window_5_6 <= 0; |
|
Inter_H_window_0_7 <= 0;Inter_H_window_1_7 <= 0;Inter_H_window_2_7 <= 0; |
Inter_H_window_3_7 <= 0;Inter_H_window_4_7 <= 0;Inter_H_window_5_7 <= 0; |
|
Inter_H_window_0_8 <= 0;Inter_H_window_1_8 <= 0;Inter_H_window_2_8 <= 0; |
Inter_H_window_3_8 <= 0;Inter_H_window_4_8 <= 0;Inter_H_window_5_8 <= 0; |
end |
endcase |
default: |
begin |
Inter_H_window_0_0 <= 0;Inter_H_window_1_0 <= 0;Inter_H_window_2_0 <= 0; |
Inter_H_window_3_0 <= 0;Inter_H_window_4_0 <= 0;Inter_H_window_5_0 <= 0; |
|
Inter_H_window_0_1 <= 0;Inter_H_window_1_1 <= 0;Inter_H_window_2_1 <= 0; |
Inter_H_window_3_1 <= 0;Inter_H_window_4_1 <= 0;Inter_H_window_5_1 <= 0; |
|
Inter_H_window_0_6 <= 0;Inter_H_window_1_6 <= 0;Inter_H_window_2_6 <= 0; |
Inter_H_window_3_6 <= 0;Inter_H_window_4_6 <= 0;Inter_H_window_5_6 <= 0; |
|
Inter_H_window_0_7 <= 0;Inter_H_window_1_7 <= 0;Inter_H_window_2_7 <= 0; |
Inter_H_window_3_7 <= 0;Inter_H_window_4_7 <= 0;Inter_H_window_5_7 <= 0; |
|
Inter_H_window_0_8 <= 0;Inter_H_window_1_8 <= 0;Inter_H_window_2_8 <= 0; |
Inter_H_window_3_8 <= 0;Inter_H_window_4_8 <= 0;Inter_H_window_5_8 <= 0; |
end |
endcase |
|
//Inter_H_window_counter1:for Inter_H_window_x_2/3/4/5 sliding window control |
reg [2:0] Inter_H_window_counter1; |
always @ (pos_FracL or blk4x4_inter_calculate_counter) |
if (((pos_FracL == `pos_b || pos_FracL == `pos_a || pos_FracL == `pos_c || pos_FracL == `pos_e || pos_FracL == `pos_g |
|| pos_FracL == `pos_p || pos_FracL == `pos_r) && blk4x4_inter_calculate_counter == 4'd4) || |
((pos_FracL == `pos_j || pos_FracL == `pos_f || pos_FracL == `pos_q) && blk4x4_inter_calculate_counter == 4'd5) || |
((pos_FracL == `pos_i || pos_FracL == `pos_k) && blk4x4_inter_calculate_counter == 4'd8)) |
Inter_H_window_counter1 <= 3'd4; |
else if (((pos_FracL == `pos_b || pos_FracL == `pos_a || pos_FracL == `pos_c || pos_FracL == `pos_e || pos_FracL == `pos_g |
|| pos_FracL == `pos_p || pos_FracL == `pos_r) && blk4x4_inter_calculate_counter == 4'd3) || |
((pos_FracL == `pos_j || pos_FracL == `pos_f || pos_FracL == `pos_q) && blk4x4_inter_calculate_counter == 4'd4) || |
((pos_FracL == `pos_i || pos_FracL == `pos_k) && blk4x4_inter_calculate_counter == 4'd6)) |
Inter_H_window_counter1 <= 3'd3; |
else if (((pos_FracL == `pos_b || pos_FracL == `pos_a || pos_FracL == `pos_c || pos_FracL == `pos_e || pos_FracL == `pos_g |
|| pos_FracL == `pos_p || pos_FracL == `pos_r) && blk4x4_inter_calculate_counter == 4'd2) || |
((pos_FracL == `pos_j || pos_FracL == `pos_f || pos_FracL == `pos_q) && blk4x4_inter_calculate_counter == 4'd3) || |
((pos_FracL == `pos_i || pos_FracL == `pos_k) && blk4x4_inter_calculate_counter == 4'd4)) |
Inter_H_window_counter1 <= 3'd2; |
else if (((pos_FracL == `pos_b || pos_FracL == `pos_a || pos_FracL == `pos_c || pos_FracL == `pos_e || pos_FracL == `pos_g |
|| pos_FracL == `pos_p || pos_FracL == `pos_r) && blk4x4_inter_calculate_counter == 4'd1) || |
((pos_FracL == `pos_j || pos_FracL == `pos_f || pos_FracL == `pos_q) && blk4x4_inter_calculate_counter == 4'd2) || |
((pos_FracL == `pos_i || pos_FracL == `pos_k) && blk4x4_inter_calculate_counter == 4'd2)) |
Inter_H_window_counter1 <= 3'd1; |
else |
Inter_H_window_counter1 <= 0; |
|
//Inter_H_window_x_2,Inter_H_window_x_3,Inter_H_window_x_4,Inter_H_window_x_5 |
always @ (Is_blk4x4_0 or Is_blk4x4_1 or Is_blk4x4_2 or Is_blk4x4_3 or pos_FracL or Inter_H_window_counter1 |
or Inter_ref_00_02 or Inter_ref_01_02 or Inter_ref_02_02 or Inter_ref_03_02 |
or Inter_ref_04_02 or Inter_ref_05_02 or Inter_ref_06_02 or Inter_ref_07_02 |
or Inter_ref_08_02 or Inter_ref_09_02 or Inter_ref_10_02 or Inter_ref_11_02 or Inter_ref_12_02 |
|
or Inter_ref_00_03 or Inter_ref_01_03 or Inter_ref_02_03 or Inter_ref_03_03 |
or Inter_ref_04_03 or Inter_ref_05_03 or Inter_ref_06_03 or Inter_ref_07_03 |
or Inter_ref_08_03 or Inter_ref_09_03 or Inter_ref_10_03 or Inter_ref_11_03 or Inter_ref_12_03 |
|
or Inter_ref_00_04 or Inter_ref_01_04 or Inter_ref_02_04 or Inter_ref_03_04 |
or Inter_ref_04_04 or Inter_ref_05_04 or Inter_ref_06_04 or Inter_ref_07_04 |
or Inter_ref_08_04 or Inter_ref_09_04 or Inter_ref_10_04 or Inter_ref_11_04 or Inter_ref_12_04 |
|
or Inter_ref_00_05 or Inter_ref_01_05 or Inter_ref_02_05 or Inter_ref_03_05 |
or Inter_ref_04_05 or Inter_ref_05_05 or Inter_ref_06_05 or Inter_ref_07_05 |
or Inter_ref_08_05 or Inter_ref_09_05 or Inter_ref_10_05 or Inter_ref_11_05 or Inter_ref_12_05 |
|
or Inter_ref_00_06 or Inter_ref_01_06 or Inter_ref_02_06 or Inter_ref_03_06 |
or Inter_ref_04_06 or Inter_ref_05_06 or Inter_ref_06_06 or Inter_ref_07_06 |
or Inter_ref_08_06 or Inter_ref_09_06 or Inter_ref_10_06 or Inter_ref_11_06 or Inter_ref_12_06 |
|
or Inter_ref_00_07 or Inter_ref_01_07 or Inter_ref_02_07 or Inter_ref_03_07 |
or Inter_ref_04_07 or Inter_ref_05_07 or Inter_ref_06_07 or Inter_ref_07_07 |
or Inter_ref_08_07 or Inter_ref_09_07 or Inter_ref_10_07 or Inter_ref_11_07 or Inter_ref_12_07 |
|
or Inter_ref_00_08 or Inter_ref_01_08 or Inter_ref_02_08 or Inter_ref_03_08 |
or Inter_ref_04_08 or Inter_ref_05_08 or Inter_ref_06_08 or Inter_ref_07_08 |
or Inter_ref_08_08 or Inter_ref_09_08 or Inter_ref_10_08 or Inter_ref_11_08 or Inter_ref_12_08 |
|
or Inter_ref_00_09 or Inter_ref_01_09 or Inter_ref_02_09 or Inter_ref_03_09 |
or Inter_ref_04_09 or Inter_ref_05_09 or Inter_ref_06_09 or Inter_ref_07_09 |
or Inter_ref_08_09 or Inter_ref_09_09 or Inter_ref_10_09 or Inter_ref_11_09 or Inter_ref_12_09 |
|
or Inter_ref_00_10 or Inter_ref_01_10 or Inter_ref_02_10 or Inter_ref_03_10 |
or Inter_ref_04_10 or Inter_ref_05_10 or Inter_ref_06_10 or Inter_ref_07_10 |
or Inter_ref_08_10 or Inter_ref_09_10 or Inter_ref_10_10 or Inter_ref_11_10 or Inter_ref_12_10 |
) |
case ({Is_blk4x4_0,Is_blk4x4_1,Is_blk4x4_2,Is_blk4x4_3}) |
4'b1000: //Left top blk4x4 |
case (Inter_H_window_counter1) |
3'd4: |
if (pos_FracL == `pos_p || pos_FracL == `pos_r) |
begin |
Inter_H_window_0_2 <= Inter_ref_00_03;Inter_H_window_1_2 <= Inter_ref_01_03; |
Inter_H_window_2_2 <= Inter_ref_02_03;Inter_H_window_3_2 <= Inter_ref_03_03; |
Inter_H_window_4_2 <= Inter_ref_04_03;Inter_H_window_5_2 <= Inter_ref_05_03; |
|
Inter_H_window_0_3 <= Inter_ref_00_04;Inter_H_window_1_3 <= Inter_ref_01_04; |
Inter_H_window_2_3 <= Inter_ref_02_04;Inter_H_window_3_3 <= Inter_ref_03_04; |
Inter_H_window_4_3 <= Inter_ref_04_04;Inter_H_window_5_3 <= Inter_ref_05_04; |
|
Inter_H_window_0_4 <= Inter_ref_00_05;Inter_H_window_1_4 <= Inter_ref_01_05; |
Inter_H_window_2_4 <= Inter_ref_02_05;Inter_H_window_3_4 <= Inter_ref_03_05; |
Inter_H_window_4_4 <= Inter_ref_04_05;Inter_H_window_5_4 <= Inter_ref_05_05; |
|
Inter_H_window_0_5 <= Inter_ref_00_06;Inter_H_window_1_5 <= Inter_ref_01_06; |
Inter_H_window_2_5 <= Inter_ref_02_06;Inter_H_window_3_5 <= Inter_ref_03_06; |
Inter_H_window_4_5 <= Inter_ref_04_06;Inter_H_window_5_5 <= Inter_ref_05_06; |
end |
else |
begin |
Inter_H_window_0_2 <= Inter_ref_00_02;Inter_H_window_1_2 <= Inter_ref_01_02; |
Inter_H_window_2_2 <= Inter_ref_02_02;Inter_H_window_3_2 <= Inter_ref_03_02; |
Inter_H_window_4_2 <= Inter_ref_04_02;Inter_H_window_5_2 <= Inter_ref_05_02; |
|
Inter_H_window_0_3 <= Inter_ref_00_03;Inter_H_window_1_3 <= Inter_ref_01_03; |
Inter_H_window_2_3 <= Inter_ref_02_03;Inter_H_window_3_3 <= Inter_ref_03_03; |
Inter_H_window_4_3 <= Inter_ref_04_03;Inter_H_window_5_3 <= Inter_ref_05_03; |
|
Inter_H_window_0_4 <= Inter_ref_00_04;Inter_H_window_1_4 <= Inter_ref_01_04; |
Inter_H_window_2_4 <= Inter_ref_02_04;Inter_H_window_3_4 <= Inter_ref_03_04; |
Inter_H_window_4_4 <= Inter_ref_04_04;Inter_H_window_5_4 <= Inter_ref_05_04; |
|
Inter_H_window_0_5 <= Inter_ref_00_05;Inter_H_window_1_5 <= Inter_ref_01_05; |
Inter_H_window_2_5 <= Inter_ref_02_05;Inter_H_window_3_5 <= Inter_ref_03_05; |
Inter_H_window_4_5 <= Inter_ref_04_05;Inter_H_window_5_5 <= Inter_ref_05_05; |
end |
3'd3: |
if (pos_FracL == `pos_p || pos_FracL == `pos_r) |
begin |
Inter_H_window_0_2 <= Inter_ref_01_03;Inter_H_window_1_2 <= Inter_ref_02_03; |
Inter_H_window_2_2 <= Inter_ref_03_03;Inter_H_window_3_2 <= Inter_ref_04_03; |
Inter_H_window_4_2 <= Inter_ref_05_03;Inter_H_window_5_2 <= Inter_ref_06_03; |
|
Inter_H_window_0_3 <= Inter_ref_01_04;Inter_H_window_1_3 <= Inter_ref_02_04; |
Inter_H_window_2_3 <= Inter_ref_03_04;Inter_H_window_3_3 <= Inter_ref_04_04; |
Inter_H_window_4_3 <= Inter_ref_05_04;Inter_H_window_5_3 <= Inter_ref_06_04; |
|
Inter_H_window_0_4 <= Inter_ref_01_05;Inter_H_window_1_4 <= Inter_ref_02_05; |
Inter_H_window_2_4 <= Inter_ref_03_05;Inter_H_window_3_4 <= Inter_ref_04_05; |
Inter_H_window_4_4 <= Inter_ref_05_05;Inter_H_window_5_4 <= Inter_ref_06_05; |
|
Inter_H_window_0_5 <= Inter_ref_01_06;Inter_H_window_1_5 <= Inter_ref_02_06; |
Inter_H_window_2_5 <= Inter_ref_03_06;Inter_H_window_3_5 <= Inter_ref_04_06; |
Inter_H_window_4_5 <= Inter_ref_05_06;Inter_H_window_5_5 <= Inter_ref_06_06; |
end |
else |
begin |
Inter_H_window_0_2 <= Inter_ref_01_02;Inter_H_window_1_2 <= Inter_ref_02_02; |
Inter_H_window_2_2 <= Inter_ref_03_02;Inter_H_window_3_2 <= Inter_ref_04_02; |
Inter_H_window_4_2 <= Inter_ref_05_02;Inter_H_window_5_2 <= Inter_ref_06_02; |
|
Inter_H_window_0_3 <= Inter_ref_01_03;Inter_H_window_1_3 <= Inter_ref_02_03; |
Inter_H_window_2_3 <= Inter_ref_03_03;Inter_H_window_3_3 <= Inter_ref_04_03; |
Inter_H_window_4_3 <= Inter_ref_05_03;Inter_H_window_5_3 <= Inter_ref_06_03; |
|
Inter_H_window_0_4 <= Inter_ref_01_04;Inter_H_window_1_4 <= Inter_ref_02_04; |
Inter_H_window_2_4 <= Inter_ref_03_04;Inter_H_window_3_4 <= Inter_ref_04_04; |
Inter_H_window_4_4 <= Inter_ref_05_04;Inter_H_window_5_4 <= Inter_ref_06_04; |
|
Inter_H_window_0_5 <= Inter_ref_01_05;Inter_H_window_1_5 <= Inter_ref_02_05; |
Inter_H_window_2_5 <= Inter_ref_03_05;Inter_H_window_3_5 <= Inter_ref_04_05; |
Inter_H_window_4_5 <= Inter_ref_05_05;Inter_H_window_5_5 <= Inter_ref_06_05; |
end |
3'd2: |
if (pos_FracL == `pos_p || pos_FracL == `pos_r) |
begin |
Inter_H_window_0_2 <= Inter_ref_02_03;Inter_H_window_1_2 <= Inter_ref_03_03; |
Inter_H_window_2_2 <= Inter_ref_04_03;Inter_H_window_3_2 <= Inter_ref_05_03; |
Inter_H_window_4_2 <= Inter_ref_06_03;Inter_H_window_5_2 <= Inter_ref_07_03; |
|
Inter_H_window_0_3 <= Inter_ref_02_04;Inter_H_window_1_3 <= Inter_ref_03_04; |
Inter_H_window_2_3 <= Inter_ref_04_04;Inter_H_window_3_3 <= Inter_ref_05_04; |
Inter_H_window_4_3 <= Inter_ref_06_04;Inter_H_window_5_3 <= Inter_ref_07_04; |
|
Inter_H_window_0_4 <= Inter_ref_02_05;Inter_H_window_1_4 <= Inter_ref_03_05; |
Inter_H_window_2_4 <= Inter_ref_04_05;Inter_H_window_3_4 <= Inter_ref_05_05; |
Inter_H_window_4_4 <= Inter_ref_06_05;Inter_H_window_5_4 <= Inter_ref_07_05; |
|
Inter_H_window_0_5 <= Inter_ref_02_06;Inter_H_window_1_5 <= Inter_ref_03_06; |
Inter_H_window_2_5 <= Inter_ref_04_06;Inter_H_window_3_5 <= Inter_ref_05_06; |
Inter_H_window_4_5 <= Inter_ref_06_06;Inter_H_window_5_5 <= Inter_ref_07_06; |
end |
else |
begin |
Inter_H_window_0_2 <= Inter_ref_02_02;Inter_H_window_1_2 <= Inter_ref_03_02; |
Inter_H_window_2_2 <= Inter_ref_04_02;Inter_H_window_3_2 <= Inter_ref_05_02; |
Inter_H_window_4_2 <= Inter_ref_06_02;Inter_H_window_5_2 <= Inter_ref_07_02; |
|
Inter_H_window_0_3 <= Inter_ref_02_03;Inter_H_window_1_3 <= Inter_ref_03_03; |
Inter_H_window_2_3 <= Inter_ref_04_03;Inter_H_window_3_3 <= Inter_ref_05_03; |
Inter_H_window_4_3 <= Inter_ref_06_03;Inter_H_window_5_3 <= Inter_ref_07_03; |
|
Inter_H_window_0_4 <= Inter_ref_02_04;Inter_H_window_1_4 <= Inter_ref_03_04; |
Inter_H_window_2_4 <= Inter_ref_04_04;Inter_H_window_3_4 <= Inter_ref_05_04; |
Inter_H_window_4_4 <= Inter_ref_06_04;Inter_H_window_5_4 <= Inter_ref_07_04; |
|
Inter_H_window_0_5 <= Inter_ref_02_05;Inter_H_window_1_5 <= Inter_ref_03_05; |
Inter_H_window_2_5 <= Inter_ref_04_05;Inter_H_window_3_5 <= Inter_ref_05_05; |
Inter_H_window_4_5 <= Inter_ref_06_05;Inter_H_window_5_5 <= Inter_ref_07_05; |
end |
3'd1: |
if (pos_FracL == `pos_p || pos_FracL == `pos_r) |
begin |
Inter_H_window_0_2 <= Inter_ref_03_03;Inter_H_window_1_2 <= Inter_ref_04_03; |
Inter_H_window_2_2 <= Inter_ref_05_03;Inter_H_window_3_2 <= Inter_ref_06_03; |
Inter_H_window_4_2 <= Inter_ref_07_03;Inter_H_window_5_2 <= Inter_ref_08_03; |
|
Inter_H_window_0_3 <= Inter_ref_03_04;Inter_H_window_1_3 <= Inter_ref_04_04; |
Inter_H_window_2_3 <= Inter_ref_05_04;Inter_H_window_3_3 <= Inter_ref_06_04; |
Inter_H_window_4_3 <= Inter_ref_07_04;Inter_H_window_5_3 <= Inter_ref_08_04; |
|
Inter_H_window_0_4 <= Inter_ref_03_05;Inter_H_window_1_4 <= Inter_ref_04_05; |
Inter_H_window_2_4 <= Inter_ref_05_05;Inter_H_window_3_4 <= Inter_ref_06_05; |
Inter_H_window_4_4 <= Inter_ref_07_05;Inter_H_window_5_4 <= Inter_ref_08_05; |
|
Inter_H_window_0_5 <= Inter_ref_03_06;Inter_H_window_1_5 <= Inter_ref_04_06; |
Inter_H_window_2_5 <= Inter_ref_05_06;Inter_H_window_3_5 <= Inter_ref_06_06; |
Inter_H_window_4_5 <= Inter_ref_07_06;Inter_H_window_5_5 <= Inter_ref_08_06; |
end |
else |
begin |
Inter_H_window_0_2 <= Inter_ref_03_02;Inter_H_window_1_2 <= Inter_ref_04_02; |
Inter_H_window_2_2 <= Inter_ref_05_02;Inter_H_window_3_2 <= Inter_ref_06_02; |
Inter_H_window_4_2 <= Inter_ref_07_02;Inter_H_window_5_2 <= Inter_ref_08_02; |
|
Inter_H_window_0_3 <= Inter_ref_03_03;Inter_H_window_1_3 <= Inter_ref_04_03; |
Inter_H_window_2_3 <= Inter_ref_05_03;Inter_H_window_3_3 <= Inter_ref_06_03; |
Inter_H_window_4_3 <= Inter_ref_07_03;Inter_H_window_5_3 <= Inter_ref_08_03; |
|
Inter_H_window_0_4 <= Inter_ref_03_04;Inter_H_window_1_4 <= Inter_ref_04_04; |
Inter_H_window_2_4 <= Inter_ref_05_04;Inter_H_window_3_4 <= Inter_ref_06_04; |
Inter_H_window_4_4 <= Inter_ref_07_04;Inter_H_window_5_4 <= Inter_ref_08_04; |
|
Inter_H_window_0_5 <= Inter_ref_03_05;Inter_H_window_1_5 <= Inter_ref_04_05; |
Inter_H_window_2_5 <= Inter_ref_05_05;Inter_H_window_3_5 <= Inter_ref_06_05; |
Inter_H_window_4_5 <= Inter_ref_07_05;Inter_H_window_5_5 <= Inter_ref_08_05; |
end |
default: |
begin |
Inter_H_window_0_2 <= 0;Inter_H_window_1_2 <= 0;Inter_H_window_2_2 <= 0; |
Inter_H_window_3_2 <= 0;Inter_H_window_4_2 <= 0;Inter_H_window_5_2 <= 0; |
|
Inter_H_window_0_3 <= 0;Inter_H_window_1_3 <= 0;Inter_H_window_2_3 <= 0; |
Inter_H_window_3_3 <= 0;Inter_H_window_4_3 <= 0;Inter_H_window_5_3 <= 0; |
|
Inter_H_window_0_4 <= 0;Inter_H_window_1_4 <= 0;Inter_H_window_2_4 <= 0; |
Inter_H_window_3_4 <= 0;Inter_H_window_4_4 <= 0;Inter_H_window_5_4 <= 0; |
|
Inter_H_window_0_5 <= 0;Inter_H_window_1_5 <= 0;Inter_H_window_2_5 <= 0; |
Inter_H_window_3_5 <= 0;Inter_H_window_4_5 <= 0;Inter_H_window_5_5 <= 0; |
end |
endcase |
4'b0100: //Right top blk4x4 |
case (Inter_H_window_counter1) |
3'd4: |
if (pos_FracL == `pos_p || pos_FracL == `pos_r) |
begin |
Inter_H_window_0_2 <= Inter_ref_04_03;Inter_H_window_1_2 <= Inter_ref_05_03; |
Inter_H_window_2_2 <= Inter_ref_06_03;Inter_H_window_3_2 <= Inter_ref_07_03; |
Inter_H_window_4_2 <= Inter_ref_08_03;Inter_H_window_5_2 <= Inter_ref_09_03; |
|
Inter_H_window_0_3 <= Inter_ref_04_04;Inter_H_window_1_3 <= Inter_ref_05_04; |
Inter_H_window_2_3 <= Inter_ref_06_04;Inter_H_window_3_3 <= Inter_ref_07_04; |
Inter_H_window_4_3 <= Inter_ref_08_04;Inter_H_window_5_3 <= Inter_ref_09_04; |
|
Inter_H_window_0_4 <= Inter_ref_04_05;Inter_H_window_1_4 <= Inter_ref_05_05; |
Inter_H_window_2_4 <= Inter_ref_06_05;Inter_H_window_3_4 <= Inter_ref_07_05; |
Inter_H_window_4_4 <= Inter_ref_08_05;Inter_H_window_5_4 <= Inter_ref_09_05; |
|
Inter_H_window_0_5 <= Inter_ref_04_06;Inter_H_window_1_5 <= Inter_ref_05_06; |
Inter_H_window_2_5 <= Inter_ref_06_06;Inter_H_window_3_5 <= Inter_ref_07_06; |
Inter_H_window_4_5 <= Inter_ref_08_06;Inter_H_window_5_5 <= Inter_ref_09_06; |
end |
else |
begin |
Inter_H_window_0_2 <= Inter_ref_04_02;Inter_H_window_1_2 <= Inter_ref_05_02; |
Inter_H_window_2_2 <= Inter_ref_06_02;Inter_H_window_3_2 <= Inter_ref_07_02; |
Inter_H_window_4_2 <= Inter_ref_08_02;Inter_H_window_5_2 <= Inter_ref_09_02; |
|
Inter_H_window_0_3 <= Inter_ref_04_03;Inter_H_window_1_3 <= Inter_ref_05_03; |
Inter_H_window_2_3 <= Inter_ref_06_03;Inter_H_window_3_3 <= Inter_ref_07_03; |
Inter_H_window_4_3 <= Inter_ref_08_03;Inter_H_window_5_3 <= Inter_ref_09_03; |
|
Inter_H_window_0_4 <= Inter_ref_04_04;Inter_H_window_1_4 <= Inter_ref_05_04; |
Inter_H_window_2_4 <= Inter_ref_06_04;Inter_H_window_3_4 <= Inter_ref_07_04; |
Inter_H_window_4_4 <= Inter_ref_08_04;Inter_H_window_5_4 <= Inter_ref_09_04; |
|
Inter_H_window_0_5 <= Inter_ref_04_05;Inter_H_window_1_5 <= Inter_ref_05_05; |
Inter_H_window_2_5 <= Inter_ref_06_05;Inter_H_window_3_5 <= Inter_ref_07_05; |
Inter_H_window_4_5 <= Inter_ref_08_05;Inter_H_window_5_5 <= Inter_ref_09_05; |
end |
3'd3: |
if (pos_FracL == `pos_p || pos_FracL == `pos_r) |
begin |
Inter_H_window_0_2 <= Inter_ref_05_03;Inter_H_window_1_2 <= Inter_ref_06_03; |
Inter_H_window_2_2 <= Inter_ref_07_03;Inter_H_window_3_2 <= Inter_ref_08_03; |
Inter_H_window_4_2 <= Inter_ref_09_03;Inter_H_window_5_2 <= Inter_ref_10_03; |
|
Inter_H_window_0_3 <= Inter_ref_05_04;Inter_H_window_1_3 <= Inter_ref_06_04; |
Inter_H_window_2_3 <= Inter_ref_07_04;Inter_H_window_3_3 <= Inter_ref_08_04; |
Inter_H_window_4_3 <= Inter_ref_09_04;Inter_H_window_5_3 <= Inter_ref_10_04; |
|
Inter_H_window_0_4 <= Inter_ref_05_05;Inter_H_window_1_4 <= Inter_ref_06_05; |
Inter_H_window_2_4 <= Inter_ref_07_05;Inter_H_window_3_4 <= Inter_ref_08_05; |
Inter_H_window_4_4 <= Inter_ref_09_05;Inter_H_window_5_4 <= Inter_ref_10_05; |
|
Inter_H_window_0_5 <= Inter_ref_05_06;Inter_H_window_1_5 <= Inter_ref_06_06; |
Inter_H_window_2_5 <= Inter_ref_07_06;Inter_H_window_3_5 <= Inter_ref_08_06; |
Inter_H_window_4_5 <= Inter_ref_09_06;Inter_H_window_5_5 <= Inter_ref_10_06; |
end |
else |
begin |
Inter_H_window_0_2 <= Inter_ref_05_02;Inter_H_window_1_2 <= Inter_ref_06_02; |
Inter_H_window_2_2 <= Inter_ref_07_02;Inter_H_window_3_2 <= Inter_ref_08_02; |
Inter_H_window_4_2 <= Inter_ref_09_02;Inter_H_window_5_2 <= Inter_ref_10_02; |
|
Inter_H_window_0_3 <= Inter_ref_05_03;Inter_H_window_1_3 <= Inter_ref_06_03; |
Inter_H_window_2_3 <= Inter_ref_07_03;Inter_H_window_3_3 <= Inter_ref_08_03; |
Inter_H_window_4_3 <= Inter_ref_09_03;Inter_H_window_5_3 <= Inter_ref_10_03; |
|
Inter_H_window_0_4 <= Inter_ref_05_04;Inter_H_window_1_4 <= Inter_ref_06_04; |
Inter_H_window_2_4 <= Inter_ref_07_04;Inter_H_window_3_4 <= Inter_ref_08_04; |
Inter_H_window_4_4 <= Inter_ref_09_04;Inter_H_window_5_4 <= Inter_ref_10_04; |
|
Inter_H_window_0_5 <= Inter_ref_05_05;Inter_H_window_1_5 <= Inter_ref_06_05; |
Inter_H_window_2_5 <= Inter_ref_07_05;Inter_H_window_3_5 <= Inter_ref_08_05; |
Inter_H_window_4_5 <= Inter_ref_09_05;Inter_H_window_5_5 <= Inter_ref_10_05; |
end |
3'd2: |
if (pos_FracL == `pos_p || pos_FracL == `pos_r) |
begin |
Inter_H_window_0_2 <= Inter_ref_06_03;Inter_H_window_1_2 <= Inter_ref_07_03; |
Inter_H_window_2_2 <= Inter_ref_08_03;Inter_H_window_3_2 <= Inter_ref_09_03; |
Inter_H_window_4_2 <= Inter_ref_10_03;Inter_H_window_5_2 <= Inter_ref_11_03; |
|
Inter_H_window_0_3 <= Inter_ref_06_04;Inter_H_window_1_3 <= Inter_ref_07_04; |
Inter_H_window_2_3 <= Inter_ref_08_04;Inter_H_window_3_3 <= Inter_ref_09_04; |
Inter_H_window_4_3 <= Inter_ref_10_04;Inter_H_window_5_3 <= Inter_ref_11_04; |
|
Inter_H_window_0_4 <= Inter_ref_06_05;Inter_H_window_1_4 <= Inter_ref_07_05; |
Inter_H_window_2_4 <= Inter_ref_08_05;Inter_H_window_3_4 <= Inter_ref_09_05; |
Inter_H_window_4_4 <= Inter_ref_10_05;Inter_H_window_5_4 <= Inter_ref_11_05; |
|
Inter_H_window_0_5 <= Inter_ref_06_06;Inter_H_window_1_5 <= Inter_ref_07_06; |
Inter_H_window_2_5 <= Inter_ref_08_06;Inter_H_window_3_5 <= Inter_ref_09_06; |
Inter_H_window_4_5 <= Inter_ref_10_06;Inter_H_window_5_5 <= Inter_ref_11_06; |
end |
else |
begin |
Inter_H_window_0_2 <= Inter_ref_06_02;Inter_H_window_1_2 <= Inter_ref_07_02; |
Inter_H_window_2_2 <= Inter_ref_08_02;Inter_H_window_3_2 <= Inter_ref_09_02; |
Inter_H_window_4_2 <= Inter_ref_10_02;Inter_H_window_5_2 <= Inter_ref_11_02; |
|
Inter_H_window_0_3 <= Inter_ref_06_03;Inter_H_window_1_3 <= Inter_ref_07_03; |
Inter_H_window_2_3 <= Inter_ref_08_03;Inter_H_window_3_3 <= Inter_ref_09_03; |
Inter_H_window_4_3 <= Inter_ref_10_03;Inter_H_window_5_3 <= Inter_ref_11_03; |
|
Inter_H_window_0_4 <= Inter_ref_06_04;Inter_H_window_1_4 <= Inter_ref_07_04; |
Inter_H_window_2_4 <= Inter_ref_08_04;Inter_H_window_3_4 <= Inter_ref_09_04; |
Inter_H_window_4_4 <= Inter_ref_10_04;Inter_H_window_5_4 <= Inter_ref_11_04; |
|
Inter_H_window_0_5 <= Inter_ref_06_05;Inter_H_window_1_5 <= Inter_ref_07_05; |
Inter_H_window_2_5 <= Inter_ref_08_05;Inter_H_window_3_5 <= Inter_ref_09_05; |
Inter_H_window_4_5 <= Inter_ref_10_05;Inter_H_window_5_5 <= Inter_ref_11_05; |
end |
3'd1: |
if (pos_FracL == `pos_p || pos_FracL == `pos_r) |
begin |
Inter_H_window_0_2 <= Inter_ref_07_03;Inter_H_window_1_2 <= Inter_ref_08_03; |
Inter_H_window_2_2 <= Inter_ref_09_03;Inter_H_window_3_2 <= Inter_ref_10_03; |
Inter_H_window_4_2 <= Inter_ref_11_03;Inter_H_window_5_2 <= Inter_ref_12_03; |
|
Inter_H_window_0_3 <= Inter_ref_07_04;Inter_H_window_1_3 <= Inter_ref_08_04; |
Inter_H_window_2_3 <= Inter_ref_09_04;Inter_H_window_3_3 <= Inter_ref_10_04; |
Inter_H_window_4_3 <= Inter_ref_11_04;Inter_H_window_5_3 <= Inter_ref_12_04; |
|
Inter_H_window_0_4 <= Inter_ref_07_05;Inter_H_window_1_4 <= Inter_ref_08_05; |
Inter_H_window_2_4 <= Inter_ref_09_05;Inter_H_window_3_4 <= Inter_ref_10_05; |
Inter_H_window_4_4 <= Inter_ref_11_05;Inter_H_window_5_4 <= Inter_ref_12_05; |
|
Inter_H_window_0_5 <= Inter_ref_07_06;Inter_H_window_1_5 <= Inter_ref_08_06; |
Inter_H_window_2_5 <= Inter_ref_09_06;Inter_H_window_3_5 <= Inter_ref_10_06; |
Inter_H_window_4_5 <= Inter_ref_11_06;Inter_H_window_5_5 <= Inter_ref_12_06; |
end |
else |
begin |
Inter_H_window_0_2 <= Inter_ref_07_02;Inter_H_window_1_2 <= Inter_ref_08_02; |
Inter_H_window_2_2 <= Inter_ref_09_02;Inter_H_window_3_2 <= Inter_ref_10_02; |
Inter_H_window_4_2 <= Inter_ref_11_02;Inter_H_window_5_2 <= Inter_ref_12_02; |
|
Inter_H_window_0_3 <= Inter_ref_07_03;Inter_H_window_1_3 <= Inter_ref_08_03; |
Inter_H_window_2_3 <= Inter_ref_09_03;Inter_H_window_3_3 <= Inter_ref_10_03; |
Inter_H_window_4_3 <= Inter_ref_11_03;Inter_H_window_5_3 <= Inter_ref_12_03; |
|
Inter_H_window_0_4 <= Inter_ref_07_04;Inter_H_window_1_4 <= Inter_ref_08_04; |
Inter_H_window_2_4 <= Inter_ref_09_04;Inter_H_window_3_4 <= Inter_ref_10_04; |
Inter_H_window_4_4 <= Inter_ref_11_04;Inter_H_window_5_4 <= Inter_ref_12_04; |
|
Inter_H_window_0_5 <= Inter_ref_07_05;Inter_H_window_1_5 <= Inter_ref_08_05; |
Inter_H_window_2_5 <= Inter_ref_09_05;Inter_H_window_3_5 <= Inter_ref_10_05; |
Inter_H_window_4_5 <= Inter_ref_11_05;Inter_H_window_5_5 <= Inter_ref_12_05; |
end |
default: |
begin |
Inter_H_window_0_2 <= 0;Inter_H_window_1_2 <= 0;Inter_H_window_2_2 <= 0; |
Inter_H_window_3_2 <= 0;Inter_H_window_4_2 <= 0;Inter_H_window_5_2 <= 0; |
|
Inter_H_window_0_3 <= 0;Inter_H_window_1_3 <= 0;Inter_H_window_2_3 <= 0; |
Inter_H_window_3_3 <= 0;Inter_H_window_4_3 <= 0;Inter_H_window_5_3 <= 0; |
|
Inter_H_window_0_4 <= 0;Inter_H_window_1_4 <= 0;Inter_H_window_2_4 <= 0; |
Inter_H_window_3_4 <= 0;Inter_H_window_4_4 <= 0;Inter_H_window_5_4 <= 0; |
|
Inter_H_window_0_5 <= 0;Inter_H_window_1_5 <= 0;Inter_H_window_2_5 <= 0; |
Inter_H_window_3_5 <= 0;Inter_H_window_4_5 <= 0;Inter_H_window_5_5 <= 0; |
end |
endcase |
4'b0010: //Left bottom blk4x4 |
case (Inter_H_window_counter1) |
3'd4: |
if (pos_FracL == `pos_p || pos_FracL == `pos_r) |
begin |
Inter_H_window_0_2 <= Inter_ref_00_07;Inter_H_window_1_2 <= Inter_ref_01_07; |
Inter_H_window_2_2 <= Inter_ref_02_07;Inter_H_window_3_2 <= Inter_ref_03_07; |
Inter_H_window_4_2 <= Inter_ref_04_07;Inter_H_window_5_2 <= Inter_ref_05_07; |
|
Inter_H_window_0_3 <= Inter_ref_00_08;Inter_H_window_1_3 <= Inter_ref_01_08; |
Inter_H_window_2_3 <= Inter_ref_02_08;Inter_H_window_3_3 <= Inter_ref_03_08; |
Inter_H_window_4_3 <= Inter_ref_04_08;Inter_H_window_5_3 <= Inter_ref_05_08; |
|
Inter_H_window_0_4 <= Inter_ref_00_09;Inter_H_window_1_4 <= Inter_ref_01_09; |
Inter_H_window_2_4 <= Inter_ref_02_09;Inter_H_window_3_4 <= Inter_ref_03_09; |
Inter_H_window_4_4 <= Inter_ref_04_09;Inter_H_window_5_4 <= Inter_ref_05_09; |
|
Inter_H_window_0_5 <= Inter_ref_00_10;Inter_H_window_1_5 <= Inter_ref_01_10; |
Inter_H_window_2_5 <= Inter_ref_02_10;Inter_H_window_3_5 <= Inter_ref_03_10; |
Inter_H_window_4_5 <= Inter_ref_04_10;Inter_H_window_5_5 <= Inter_ref_05_10; |
end |
else |
begin |
Inter_H_window_0_2 <= Inter_ref_00_06;Inter_H_window_1_2 <= Inter_ref_01_06; |
Inter_H_window_2_2 <= Inter_ref_02_06;Inter_H_window_3_2 <= Inter_ref_03_06; |
Inter_H_window_4_2 <= Inter_ref_04_06;Inter_H_window_5_2 <= Inter_ref_05_06; |
|
Inter_H_window_0_3 <= Inter_ref_00_07;Inter_H_window_1_3 <= Inter_ref_01_07; |
Inter_H_window_2_3 <= Inter_ref_02_07;Inter_H_window_3_3 <= Inter_ref_03_07; |
Inter_H_window_4_3 <= Inter_ref_04_07;Inter_H_window_5_3 <= Inter_ref_05_07; |
|
Inter_H_window_0_4 <= Inter_ref_00_08;Inter_H_window_1_4 <= Inter_ref_01_08; |
Inter_H_window_2_4 <= Inter_ref_02_08;Inter_H_window_3_4 <= Inter_ref_03_08; |
Inter_H_window_4_4 <= Inter_ref_04_08;Inter_H_window_5_4 <= Inter_ref_05_08; |
|
Inter_H_window_0_5 <= Inter_ref_00_09;Inter_H_window_1_5 <= Inter_ref_01_09; |
Inter_H_window_2_5 <= Inter_ref_02_09;Inter_H_window_3_5 <= Inter_ref_03_09; |
Inter_H_window_4_5 <= Inter_ref_04_09;Inter_H_window_5_5 <= Inter_ref_05_09; |
end |
3'd3: |
if (pos_FracL == `pos_p || pos_FracL == `pos_r) |
begin |
Inter_H_window_0_2 <= Inter_ref_01_07;Inter_H_window_1_2 <= Inter_ref_02_07; |
Inter_H_window_2_2 <= Inter_ref_03_07;Inter_H_window_3_2 <= Inter_ref_04_07; |
Inter_H_window_4_2 <= Inter_ref_05_07;Inter_H_window_5_2 <= Inter_ref_06_07; |
|
Inter_H_window_0_3 <= Inter_ref_01_08;Inter_H_window_1_3 <= Inter_ref_02_08; |
Inter_H_window_2_3 <= Inter_ref_03_08;Inter_H_window_3_3 <= Inter_ref_04_08; |
Inter_H_window_4_3 <= Inter_ref_05_08;Inter_H_window_5_3 <= Inter_ref_06_08; |
|
Inter_H_window_0_4 <= Inter_ref_01_09;Inter_H_window_1_4 <= Inter_ref_02_09; |
Inter_H_window_2_4 <= Inter_ref_03_09;Inter_H_window_3_4 <= Inter_ref_04_09; |
Inter_H_window_4_4 <= Inter_ref_05_09;Inter_H_window_5_4 <= Inter_ref_06_09; |
|
Inter_H_window_0_5 <= Inter_ref_01_10;Inter_H_window_1_5 <= Inter_ref_02_10; |
Inter_H_window_2_5 <= Inter_ref_03_10;Inter_H_window_3_5 <= Inter_ref_04_10; |
Inter_H_window_4_5 <= Inter_ref_05_10;Inter_H_window_5_5 <= Inter_ref_06_10; |
end |
else |
begin |
Inter_H_window_0_2 <= Inter_ref_01_06;Inter_H_window_1_2 <= Inter_ref_02_06; |
Inter_H_window_2_2 <= Inter_ref_03_06;Inter_H_window_3_2 <= Inter_ref_04_06; |
Inter_H_window_4_2 <= Inter_ref_05_06;Inter_H_window_5_2 <= Inter_ref_06_06; |
|
Inter_H_window_0_3 <= Inter_ref_01_07;Inter_H_window_1_3 <= Inter_ref_02_07; |
Inter_H_window_2_3 <= Inter_ref_03_07;Inter_H_window_3_3 <= Inter_ref_04_07; |
Inter_H_window_4_3 <= Inter_ref_05_07;Inter_H_window_5_3 <= Inter_ref_06_07; |
|
Inter_H_window_0_4 <= Inter_ref_01_08;Inter_H_window_1_4 <= Inter_ref_02_08; |
Inter_H_window_2_4 <= Inter_ref_03_08;Inter_H_window_3_4 <= Inter_ref_04_08; |
Inter_H_window_4_4 <= Inter_ref_05_08;Inter_H_window_5_4 <= Inter_ref_06_08; |
|
Inter_H_window_0_5 <= Inter_ref_01_09;Inter_H_window_1_5 <= Inter_ref_02_09; |
Inter_H_window_2_5 <= Inter_ref_03_09;Inter_H_window_3_5 <= Inter_ref_04_09; |
Inter_H_window_4_5 <= Inter_ref_05_09;Inter_H_window_5_5 <= Inter_ref_06_09; |
end |
3'd2: |
if (pos_FracL == `pos_p || pos_FracL == `pos_r) |
begin |
Inter_H_window_0_2 <= Inter_ref_02_07;Inter_H_window_1_2 <= Inter_ref_03_07; |
Inter_H_window_2_2 <= Inter_ref_04_07;Inter_H_window_3_2 <= Inter_ref_05_07; |
Inter_H_window_4_2 <= Inter_ref_06_07;Inter_H_window_5_2 <= Inter_ref_07_07; |
|
Inter_H_window_0_3 <= Inter_ref_02_08;Inter_H_window_1_3 <= Inter_ref_03_08; |
Inter_H_window_2_3 <= Inter_ref_04_08;Inter_H_window_3_3 <= Inter_ref_05_08; |
Inter_H_window_4_3 <= Inter_ref_06_08;Inter_H_window_5_3 <= Inter_ref_07_08; |
|
Inter_H_window_0_4 <= Inter_ref_02_09;Inter_H_window_1_4 <= Inter_ref_03_09; |
Inter_H_window_2_4 <= Inter_ref_04_09;Inter_H_window_3_4 <= Inter_ref_05_09; |
Inter_H_window_4_4 <= Inter_ref_06_09;Inter_H_window_5_4 <= Inter_ref_07_09; |
|
Inter_H_window_0_5 <= Inter_ref_02_10;Inter_H_window_1_5 <= Inter_ref_03_10; |
Inter_H_window_2_5 <= Inter_ref_04_10;Inter_H_window_3_5 <= Inter_ref_05_10; |
Inter_H_window_4_5 <= Inter_ref_06_10;Inter_H_window_5_5 <= Inter_ref_07_10; |
end |
else |
begin |
Inter_H_window_0_2 <= Inter_ref_02_06;Inter_H_window_1_2 <= Inter_ref_03_06; |
Inter_H_window_2_2 <= Inter_ref_04_06;Inter_H_window_3_2 <= Inter_ref_05_06; |
Inter_H_window_4_2 <= Inter_ref_06_06;Inter_H_window_5_2 <= Inter_ref_07_06; |
|
Inter_H_window_0_3 <= Inter_ref_02_07;Inter_H_window_1_3 <= Inter_ref_03_07; |
Inter_H_window_2_3 <= Inter_ref_04_07;Inter_H_window_3_3 <= Inter_ref_05_07; |
Inter_H_window_4_3 <= Inter_ref_06_07;Inter_H_window_5_3 <= Inter_ref_07_07; |
|
Inter_H_window_0_4 <= Inter_ref_02_08;Inter_H_window_1_4 <= Inter_ref_03_08; |
Inter_H_window_2_4 <= Inter_ref_04_08;Inter_H_window_3_4 <= Inter_ref_05_08; |
Inter_H_window_4_4 <= Inter_ref_06_08;Inter_H_window_5_4 <= Inter_ref_07_08; |
|
Inter_H_window_0_5 <= Inter_ref_02_09;Inter_H_window_1_5 <= Inter_ref_03_09; |
Inter_H_window_2_5 <= Inter_ref_04_09;Inter_H_window_3_5 <= Inter_ref_05_09; |
Inter_H_window_4_5 <= Inter_ref_06_09;Inter_H_window_5_5 <= Inter_ref_07_09; |
end |
3'd1: |
if (pos_FracL == `pos_p || pos_FracL == `pos_r) |
begin |
Inter_H_window_0_2 <= Inter_ref_03_07;Inter_H_window_1_2 <= Inter_ref_04_07; |
Inter_H_window_2_2 <= Inter_ref_05_07;Inter_H_window_3_2 <= Inter_ref_06_07; |
Inter_H_window_4_2 <= Inter_ref_07_07;Inter_H_window_5_2 <= Inter_ref_08_07; |
|
Inter_H_window_0_3 <= Inter_ref_03_08;Inter_H_window_1_3 <= Inter_ref_04_08; |
Inter_H_window_2_3 <= Inter_ref_05_08;Inter_H_window_3_3 <= Inter_ref_06_08; |
Inter_H_window_4_3 <= Inter_ref_07_08;Inter_H_window_5_3 <= Inter_ref_08_08; |
|
Inter_H_window_0_4 <= Inter_ref_03_09;Inter_H_window_1_4 <= Inter_ref_04_09; |
Inter_H_window_2_4 <= Inter_ref_05_09;Inter_H_window_3_4 <= Inter_ref_06_09; |
Inter_H_window_4_4 <= Inter_ref_07_09;Inter_H_window_5_4 <= Inter_ref_08_09; |
|
Inter_H_window_0_5 <= Inter_ref_03_10;Inter_H_window_1_5 <= Inter_ref_04_10; |
Inter_H_window_2_5 <= Inter_ref_05_10;Inter_H_window_3_5 <= Inter_ref_06_10; |
Inter_H_window_4_5 <= Inter_ref_07_10;Inter_H_window_5_5 <= Inter_ref_08_10; |
end |
else |
begin |
Inter_H_window_0_2 <= Inter_ref_03_06;Inter_H_window_1_2 <= Inter_ref_04_06; |
Inter_H_window_2_2 <= Inter_ref_05_06;Inter_H_window_3_2 <= Inter_ref_06_06; |
Inter_H_window_4_2 <= Inter_ref_07_06;Inter_H_window_5_2 <= Inter_ref_08_06; |
|
Inter_H_window_0_3 <= Inter_ref_03_07;Inter_H_window_1_3 <= Inter_ref_04_07; |
Inter_H_window_2_3 <= Inter_ref_05_07;Inter_H_window_3_3 <= Inter_ref_06_07; |
Inter_H_window_4_3 <= Inter_ref_07_07;Inter_H_window_5_3 <= Inter_ref_08_07; |
|
Inter_H_window_0_4 <= Inter_ref_03_08;Inter_H_window_1_4 <= Inter_ref_04_08; |
Inter_H_window_2_4 <= Inter_ref_05_08;Inter_H_window_3_4 <= Inter_ref_06_08; |
Inter_H_window_4_4 <= Inter_ref_07_08;Inter_H_window_5_4 <= Inter_ref_08_08; |
|
Inter_H_window_0_5 <= Inter_ref_03_09;Inter_H_window_1_5 <= Inter_ref_04_09; |
Inter_H_window_2_5 <= Inter_ref_05_09;Inter_H_window_3_5 <= Inter_ref_06_09; |
Inter_H_window_4_5 <= Inter_ref_07_09;Inter_H_window_5_5 <= Inter_ref_08_09; |
end |
default: |
begin |
Inter_H_window_0_2 <= 0;Inter_H_window_1_2 <= 0;Inter_H_window_2_2 <= 0; |
Inter_H_window_3_2 <= 0;Inter_H_window_4_2 <= 0;Inter_H_window_5_2 <= 0; |
|
Inter_H_window_0_3 <= 0;Inter_H_window_1_3 <= 0;Inter_H_window_2_3 <= 0; |
Inter_H_window_3_3 <= 0;Inter_H_window_4_3 <= 0;Inter_H_window_5_3 <= 0; |
|
Inter_H_window_0_4 <= 0;Inter_H_window_1_4 <= 0;Inter_H_window_2_4 <= 0; |
Inter_H_window_3_4 <= 0;Inter_H_window_4_4 <= 0;Inter_H_window_5_4 <= 0; |
|
Inter_H_window_0_5 <= 0;Inter_H_window_1_5 <= 0;Inter_H_window_2_5 <= 0; |
Inter_H_window_3_5 <= 0;Inter_H_window_4_5 <= 0;Inter_H_window_5_5 <= 0; |
end |
endcase |
4'b0001: //Right bottom blk4x4 |
case (Inter_H_window_counter1) |
3'd4: |
if (pos_FracL == `pos_p || pos_FracL == `pos_r) |
begin |
Inter_H_window_0_2 <= Inter_ref_04_07;Inter_H_window_1_2 <= Inter_ref_05_07; |
Inter_H_window_2_2 <= Inter_ref_06_07;Inter_H_window_3_2 <= Inter_ref_07_07; |
Inter_H_window_4_2 <= Inter_ref_08_07;Inter_H_window_5_2 <= Inter_ref_09_07; |
|
Inter_H_window_0_3 <= Inter_ref_04_08;Inter_H_window_1_3 <= Inter_ref_05_08; |
Inter_H_window_2_3 <= Inter_ref_06_08;Inter_H_window_3_3 <= Inter_ref_07_08; |
Inter_H_window_4_3 <= Inter_ref_08_08;Inter_H_window_5_3 <= Inter_ref_09_08; |
|
Inter_H_window_0_4 <= Inter_ref_04_09;Inter_H_window_1_4 <= Inter_ref_05_09; |
Inter_H_window_2_4 <= Inter_ref_06_09;Inter_H_window_3_4 <= Inter_ref_07_09; |
Inter_H_window_4_4 <= Inter_ref_08_09;Inter_H_window_5_4 <= Inter_ref_09_09; |
|
Inter_H_window_0_5 <= Inter_ref_04_10;Inter_H_window_1_5 <= Inter_ref_05_10; |
Inter_H_window_2_5 <= Inter_ref_06_10;Inter_H_window_3_5 <= Inter_ref_07_10; |
Inter_H_window_4_5 <= Inter_ref_08_10;Inter_H_window_5_5 <= Inter_ref_09_10; |
end |
else |
begin |
Inter_H_window_0_2 <= Inter_ref_04_06;Inter_H_window_1_2 <= Inter_ref_05_06; |
Inter_H_window_2_2 <= Inter_ref_06_06;Inter_H_window_3_2 <= Inter_ref_07_06; |
Inter_H_window_4_2 <= Inter_ref_08_06;Inter_H_window_5_2 <= Inter_ref_09_06; |
|
Inter_H_window_0_3 <= Inter_ref_04_07;Inter_H_window_1_3 <= Inter_ref_05_07; |
Inter_H_window_2_3 <= Inter_ref_06_07;Inter_H_window_3_3 <= Inter_ref_07_07; |
Inter_H_window_4_3 <= Inter_ref_08_07;Inter_H_window_5_3 <= Inter_ref_09_07; |
|
Inter_H_window_0_4 <= Inter_ref_04_08;Inter_H_window_1_4 <= Inter_ref_05_08; |
Inter_H_window_2_4 <= Inter_ref_06_08;Inter_H_window_3_4 <= Inter_ref_07_08; |
Inter_H_window_4_4 <= Inter_ref_08_08;Inter_H_window_5_4 <= Inter_ref_09_08; |
|
Inter_H_window_0_5 <= Inter_ref_04_09;Inter_H_window_1_5 <= Inter_ref_05_09; |
Inter_H_window_2_5 <= Inter_ref_06_09;Inter_H_window_3_5 <= Inter_ref_07_09; |
Inter_H_window_4_5 <= Inter_ref_08_09;Inter_H_window_5_5 <= Inter_ref_09_09; |
end |
3'd3: |
if (pos_FracL == `pos_p || pos_FracL == `pos_r) |
begin |
Inter_H_window_0_2 <= Inter_ref_05_07;Inter_H_window_1_2 <= Inter_ref_06_07; |
Inter_H_window_2_2 <= Inter_ref_07_07;Inter_H_window_3_2 <= Inter_ref_08_07; |
Inter_H_window_4_2 <= Inter_ref_09_07;Inter_H_window_5_2 <= Inter_ref_10_07; |
|
Inter_H_window_0_3 <= Inter_ref_05_08;Inter_H_window_1_3 <= Inter_ref_06_08; |
Inter_H_window_2_3 <= Inter_ref_07_08;Inter_H_window_3_3 <= Inter_ref_08_08; |
Inter_H_window_4_3 <= Inter_ref_09_08;Inter_H_window_5_3 <= Inter_ref_10_08; |
|
Inter_H_window_0_4 <= Inter_ref_05_09;Inter_H_window_1_4 <= Inter_ref_06_09; |
Inter_H_window_2_4 <= Inter_ref_07_09;Inter_H_window_3_4 <= Inter_ref_08_09; |
Inter_H_window_4_4 <= Inter_ref_09_09;Inter_H_window_5_4 <= Inter_ref_10_09; |
|
Inter_H_window_0_5 <= Inter_ref_05_10;Inter_H_window_1_5 <= Inter_ref_06_10; |
Inter_H_window_2_5 <= Inter_ref_07_10;Inter_H_window_3_5 <= Inter_ref_08_10; |
Inter_H_window_4_5 <= Inter_ref_09_10;Inter_H_window_5_5 <= Inter_ref_10_10; |
end |
else |
begin |
Inter_H_window_0_2 <= Inter_ref_05_06;Inter_H_window_1_2 <= Inter_ref_06_06; |
Inter_H_window_2_2 <= Inter_ref_07_06;Inter_H_window_3_2 <= Inter_ref_08_06; |
Inter_H_window_4_2 <= Inter_ref_09_06;Inter_H_window_5_2 <= Inter_ref_10_06; |
|
Inter_H_window_0_3 <= Inter_ref_05_07;Inter_H_window_1_3 <= Inter_ref_06_07; |
Inter_H_window_2_3 <= Inter_ref_07_07;Inter_H_window_3_3 <= Inter_ref_08_07; |
Inter_H_window_4_3 <= Inter_ref_09_07;Inter_H_window_5_3 <= Inter_ref_10_07; |
|
Inter_H_window_0_4 <= Inter_ref_05_08;Inter_H_window_1_4 <= Inter_ref_06_08; |
Inter_H_window_2_4 <= Inter_ref_07_08;Inter_H_window_3_4 <= Inter_ref_08_08; |
Inter_H_window_4_4 <= Inter_ref_09_08;Inter_H_window_5_4 <= Inter_ref_10_08; |
|
Inter_H_window_0_5 <= Inter_ref_05_09;Inter_H_window_1_5 <= Inter_ref_06_09; |
Inter_H_window_2_5 <= Inter_ref_07_09;Inter_H_window_3_5 <= Inter_ref_08_09; |
Inter_H_window_4_5 <= Inter_ref_09_09;Inter_H_window_5_5 <= Inter_ref_10_09; |
end |
3'd2: |
if (pos_FracL == `pos_p || pos_FracL == `pos_r) |
begin |
Inter_H_window_0_2 <= Inter_ref_06_07;Inter_H_window_1_2 <= Inter_ref_07_07; |
Inter_H_window_2_2 <= Inter_ref_08_07;Inter_H_window_3_2 <= Inter_ref_09_07; |
Inter_H_window_4_2 <= Inter_ref_10_07;Inter_H_window_5_2 <= Inter_ref_11_07; |
|
Inter_H_window_0_3 <= Inter_ref_06_08;Inter_H_window_1_3 <= Inter_ref_07_08; |
Inter_H_window_2_3 <= Inter_ref_08_08;Inter_H_window_3_3 <= Inter_ref_09_08; |
Inter_H_window_4_3 <= Inter_ref_10_08;Inter_H_window_5_3 <= Inter_ref_11_08; |
|
Inter_H_window_0_4 <= Inter_ref_06_09;Inter_H_window_1_4 <= Inter_ref_07_09; |
Inter_H_window_2_4 <= Inter_ref_08_09;Inter_H_window_3_4 <= Inter_ref_09_09; |
Inter_H_window_4_4 <= Inter_ref_10_09;Inter_H_window_5_4 <= Inter_ref_11_09; |
|
Inter_H_window_0_5 <= Inter_ref_06_10;Inter_H_window_1_5 <= Inter_ref_07_10; |
Inter_H_window_2_5 <= Inter_ref_08_10;Inter_H_window_3_5 <= Inter_ref_09_10; |
Inter_H_window_4_5 <= Inter_ref_10_10;Inter_H_window_5_5 <= Inter_ref_11_10; |
end |
else |
begin |
Inter_H_window_0_2 <= Inter_ref_06_06;Inter_H_window_1_2 <= Inter_ref_07_06; |
Inter_H_window_2_2 <= Inter_ref_08_06;Inter_H_window_3_2 <= Inter_ref_09_06; |
Inter_H_window_4_2 <= Inter_ref_10_06;Inter_H_window_5_2 <= Inter_ref_11_06; |
|
Inter_H_window_0_3 <= Inter_ref_06_07;Inter_H_window_1_3 <= Inter_ref_07_07; |
Inter_H_window_2_3 <= Inter_ref_08_07;Inter_H_window_3_3 <= Inter_ref_09_07; |
Inter_H_window_4_3 <= Inter_ref_10_07;Inter_H_window_5_3 <= Inter_ref_11_07; |
|
Inter_H_window_0_4 <= Inter_ref_06_08;Inter_H_window_1_4 <= Inter_ref_07_08; |
Inter_H_window_2_4 <= Inter_ref_08_08;Inter_H_window_3_4 <= Inter_ref_09_08; |
Inter_H_window_4_4 <= Inter_ref_10_08;Inter_H_window_5_4 <= Inter_ref_11_08; |
|
Inter_H_window_0_5 <= Inter_ref_06_09;Inter_H_window_1_5 <= Inter_ref_07_09; |
Inter_H_window_2_5 <= Inter_ref_08_09;Inter_H_window_3_5 <= Inter_ref_09_09; |
Inter_H_window_4_5 <= Inter_ref_10_09;Inter_H_window_5_5 <= Inter_ref_11_09; |
end |
3'd1: |
if (pos_FracL == `pos_p || pos_FracL == `pos_r) |
begin |
Inter_H_window_0_2 <= Inter_ref_07_07;Inter_H_window_1_2 <= Inter_ref_08_07; |
Inter_H_window_2_2 <= Inter_ref_09_07;Inter_H_window_3_2 <= Inter_ref_10_07; |
Inter_H_window_4_2 <= Inter_ref_11_07;Inter_H_window_5_2 <= Inter_ref_12_07; |
|
Inter_H_window_0_3 <= Inter_ref_07_08;Inter_H_window_1_3 <= Inter_ref_08_08; |
Inter_H_window_2_3 <= Inter_ref_09_08;Inter_H_window_3_3 <= Inter_ref_10_08; |
Inter_H_window_4_3 <= Inter_ref_11_08;Inter_H_window_5_3 <= Inter_ref_12_08; |
|
Inter_H_window_0_4 <= Inter_ref_07_09;Inter_H_window_1_4 <= Inter_ref_08_09; |
Inter_H_window_2_4 <= Inter_ref_09_09;Inter_H_window_3_4 <= Inter_ref_10_09; |
Inter_H_window_4_4 <= Inter_ref_11_09;Inter_H_window_5_4 <= Inter_ref_12_09; |
|
Inter_H_window_0_5 <= Inter_ref_07_10;Inter_H_window_1_5 <= Inter_ref_08_10; |
Inter_H_window_2_5 <= Inter_ref_09_10;Inter_H_window_3_5 <= Inter_ref_10_10; |
Inter_H_window_4_5 <= Inter_ref_11_10;Inter_H_window_5_5 <= Inter_ref_12_10; |
end |
else |
begin |
Inter_H_window_0_2 <= Inter_ref_07_06;Inter_H_window_1_2 <= Inter_ref_08_06; |
Inter_H_window_2_2 <= Inter_ref_09_06;Inter_H_window_3_2 <= Inter_ref_10_06; |
Inter_H_window_4_2 <= Inter_ref_11_06;Inter_H_window_5_2 <= Inter_ref_12_06; |
|
Inter_H_window_0_3 <= Inter_ref_07_07;Inter_H_window_1_3 <= Inter_ref_08_07; |
Inter_H_window_2_3 <= Inter_ref_09_07;Inter_H_window_3_3 <= Inter_ref_10_07; |
Inter_H_window_4_3 <= Inter_ref_11_07;Inter_H_window_5_3 <= Inter_ref_12_07; |
|
Inter_H_window_0_4 <= Inter_ref_07_08;Inter_H_window_1_4 <= Inter_ref_08_08; |
Inter_H_window_2_4 <= Inter_ref_09_08;Inter_H_window_3_4 <= Inter_ref_10_08; |
Inter_H_window_4_4 <= Inter_ref_11_08;Inter_H_window_5_4 <= Inter_ref_12_08; |
|
Inter_H_window_0_5 <= Inter_ref_07_09;Inter_H_window_1_5 <= Inter_ref_08_09; |
Inter_H_window_2_5 <= Inter_ref_09_09;Inter_H_window_3_5 <= Inter_ref_10_09; |
Inter_H_window_4_5 <= Inter_ref_11_09;Inter_H_window_5_5 <= Inter_ref_12_09; |
end |
default: |
begin |
Inter_H_window_0_2 <= 0;Inter_H_window_1_2 <= 0;Inter_H_window_2_2 <= 0; |
Inter_H_window_3_2 <= 0;Inter_H_window_4_2 <= 0;Inter_H_window_5_2 <= 0; |
|
Inter_H_window_0_3 <= 0;Inter_H_window_1_3 <= 0;Inter_H_window_2_3 <= 0; |
Inter_H_window_3_3 <= 0;Inter_H_window_4_3 <= 0;Inter_H_window_5_3 <= 0; |
|
Inter_H_window_0_4 <= 0;Inter_H_window_1_4 <= 0;Inter_H_window_2_4 <= 0; |
Inter_H_window_3_4 <= 0;Inter_H_window_4_4 <= 0;Inter_H_window_5_4 <= 0; |
|
Inter_H_window_0_5 <= 0;Inter_H_window_1_5 <= 0;Inter_H_window_2_5 <= 0; |
Inter_H_window_3_5 <= 0;Inter_H_window_4_5 <= 0;Inter_H_window_5_5 <= 0; |
end |
endcase |
default: |
begin |
Inter_H_window_0_2 <= 0;Inter_H_window_1_2 <= 0;Inter_H_window_2_2 <= 0; |
Inter_H_window_3_2 <= 0;Inter_H_window_4_2 <= 0;Inter_H_window_5_2 <= 0; |
|
Inter_H_window_0_3 <= 0;Inter_H_window_1_3 <= 0;Inter_H_window_2_3 <= 0; |
Inter_H_window_3_3 <= 0;Inter_H_window_4_3 <= 0;Inter_H_window_5_3 <= 0; |
|
Inter_H_window_0_4 <= 0;Inter_H_window_1_4 <= 0;Inter_H_window_2_4 <= 0; |
Inter_H_window_3_4 <= 0;Inter_H_window_4_4 <= 0;Inter_H_window_5_4 <= 0; |
|
Inter_H_window_0_5 <= 0;Inter_H_window_1_5 <= 0;Inter_H_window_2_5 <= 0; |
Inter_H_window_3_5 <= 0;Inter_H_window_4_5 <= 0;Inter_H_window_5_5 <= 0; |
end |
endcase |
|
//Inter_V_window_counter:for Inter_V_window_0 ~ Inter_V_window_8 |
reg [2:0] Inter_V_window_counter; |
always @ (pos_FracL or blk4x4_inter_calculate_counter) |
if (((pos_FracL == `pos_h || pos_FracL == `pos_d || pos_FracL == `pos_n || pos_FracL == `pos_e || pos_FracL == `pos_g |
|| pos_FracL == `pos_p || pos_FracL == `pos_r) && blk4x4_inter_calculate_counter == 4'd4) || |
((pos_FracL == `pos_i || pos_FracL == `pos_k) && blk4x4_inter_calculate_counter == 4'd8)) |
Inter_V_window_counter <= 3'd4; |
else if (((pos_FracL == `pos_h || pos_FracL == `pos_d || pos_FracL == `pos_n || pos_FracL == `pos_e || pos_FracL == `pos_g |
|| pos_FracL == `pos_p || pos_FracL == `pos_r) && blk4x4_inter_calculate_counter == 4'd3) || |
((pos_FracL == `pos_i || pos_FracL == `pos_k) && blk4x4_inter_calculate_counter == 4'd6)) |
Inter_V_window_counter <= 3'd3; |
else if (((pos_FracL == `pos_h || pos_FracL == `pos_d || pos_FracL == `pos_n || pos_FracL == `pos_e || pos_FracL == `pos_g |
|| pos_FracL == `pos_p || pos_FracL == `pos_r) && blk4x4_inter_calculate_counter == 4'd2) || |
((pos_FracL == `pos_i || pos_FracL == `pos_k) && blk4x4_inter_calculate_counter == 4'd4)) |
Inter_V_window_counter <= 3'd2; |
else if (((pos_FracL == `pos_h || pos_FracL == `pos_d || pos_FracL == `pos_n || pos_FracL == `pos_e || pos_FracL == `pos_g |
|| pos_FracL == `pos_p || pos_FracL == `pos_r) && blk4x4_inter_calculate_counter == 4'd1) || |
((pos_FracL == `pos_i || pos_FracL == `pos_k) && blk4x4_inter_calculate_counter == 4'd2)) |
Inter_V_window_counter <= 3'd1; |
else |
Inter_V_window_counter <= 0; |
|
//Inter_V_window_0 ~ Inter_V_window_8 |
always @ (Is_blk4x4_0 or Is_blk4x4_1 or Is_blk4x4_2 or Is_blk4x4_3 or pos_FracL or Inter_V_window_counter |
or Inter_ref_02_00 or Inter_ref_02_01 or Inter_ref_02_02 or Inter_ref_02_03 or Inter_ref_02_04 |
or Inter_ref_02_05 or Inter_ref_02_06 or Inter_ref_02_07 or Inter_ref_02_08 or Inter_ref_02_09 |
or Inter_ref_02_10 or Inter_ref_02_11 or Inter_ref_02_12 |
|
or Inter_ref_03_00 or Inter_ref_03_01 or Inter_ref_03_02 or Inter_ref_03_03 or Inter_ref_03_04 |
or Inter_ref_03_05 or Inter_ref_03_06 or Inter_ref_03_07 or Inter_ref_03_08 or Inter_ref_03_09 |
or Inter_ref_03_10 or Inter_ref_03_11 or Inter_ref_03_12 |
|
or Inter_ref_04_00 or Inter_ref_04_01 or Inter_ref_04_02 or Inter_ref_04_03 or Inter_ref_04_04 |
or Inter_ref_04_05 or Inter_ref_04_06 or Inter_ref_04_07 or Inter_ref_04_08 or Inter_ref_04_09 |
or Inter_ref_04_10 or Inter_ref_04_11 or Inter_ref_04_12 |
|
or Inter_ref_05_00 or Inter_ref_05_01 or Inter_ref_05_02 or Inter_ref_05_03 or Inter_ref_05_04 |
or Inter_ref_05_05 or Inter_ref_05_06 or Inter_ref_05_07 or Inter_ref_05_08 or Inter_ref_05_09 |
or Inter_ref_05_10 or Inter_ref_05_11 or Inter_ref_05_12 |
|
or Inter_ref_06_00 or Inter_ref_06_01 or Inter_ref_06_02 or Inter_ref_06_03 or Inter_ref_06_04 |
or Inter_ref_06_05 or Inter_ref_06_06 or Inter_ref_06_07 or Inter_ref_06_08 or Inter_ref_06_09 |
or Inter_ref_06_10 or Inter_ref_06_11 or Inter_ref_06_12 |
|
or Inter_ref_07_00 or Inter_ref_07_01 or Inter_ref_07_02 or Inter_ref_07_03 or Inter_ref_07_04 |
or Inter_ref_07_05 or Inter_ref_07_06 or Inter_ref_07_07 or Inter_ref_07_08 or Inter_ref_07_09 |
or Inter_ref_07_10 or Inter_ref_07_11 or Inter_ref_07_12 |
|
or Inter_ref_08_00 or Inter_ref_08_01 or Inter_ref_08_02 or Inter_ref_08_03 or Inter_ref_08_04 |
or Inter_ref_08_05 or Inter_ref_08_06 or Inter_ref_08_07 or Inter_ref_08_08 or Inter_ref_08_09 |
or Inter_ref_08_10 or Inter_ref_08_11 or Inter_ref_08_12 |
|
or Inter_ref_09_00 or Inter_ref_09_01 or Inter_ref_09_02 or Inter_ref_09_03 or Inter_ref_09_04 |
or Inter_ref_09_05 or Inter_ref_09_06 or Inter_ref_09_07 or Inter_ref_09_08 or Inter_ref_09_09 |
or Inter_ref_09_10 or Inter_ref_09_11 or Inter_ref_09_12 |
|
or Inter_ref_10_00 or Inter_ref_10_01 or Inter_ref_10_02 or Inter_ref_10_03 or Inter_ref_10_04 |
or Inter_ref_10_05 or Inter_ref_10_06 or Inter_ref_10_07 or Inter_ref_10_08 or Inter_ref_10_09 |
or Inter_ref_10_10 or Inter_ref_10_11 or Inter_ref_10_12 |
) |
case ({Is_blk4x4_0,Is_blk4x4_1,Is_blk4x4_2,Is_blk4x4_3}) |
4'b1000: //Left top blk4x4 |
case (Inter_V_window_counter) |
3'd4: |
if (pos_FracL == `pos_g || pos_FracL == `pos_r || pos_FracL == `pos_k) |
begin |
Inter_V_window_0 <= Inter_ref_03_00;Inter_V_window_1 <= Inter_ref_03_01; |
Inter_V_window_2 <= Inter_ref_03_02;Inter_V_window_3 <= Inter_ref_03_03; |
Inter_V_window_4 <= Inter_ref_03_04;Inter_V_window_5 <= Inter_ref_03_05; |
Inter_V_window_6 <= Inter_ref_03_06;Inter_V_window_7 <= Inter_ref_03_07; |
Inter_V_window_8 <= Inter_ref_03_08; |
end |
else |
begin |
Inter_V_window_0 <= Inter_ref_02_00;Inter_V_window_1 <= Inter_ref_02_01; |
Inter_V_window_2 <= Inter_ref_02_02;Inter_V_window_3 <= Inter_ref_02_03; |
Inter_V_window_4 <= Inter_ref_02_04;Inter_V_window_5 <= Inter_ref_02_05; |
Inter_V_window_6 <= Inter_ref_02_06;Inter_V_window_7 <= Inter_ref_02_07; |
Inter_V_window_8 <= Inter_ref_02_08; |
end |
3'd3: |
if (pos_FracL == `pos_g || pos_FracL == `pos_r || pos_FracL == `pos_k) |
begin |
Inter_V_window_0 <= Inter_ref_04_00;Inter_V_window_1 <= Inter_ref_04_01; |
Inter_V_window_2 <= Inter_ref_04_02;Inter_V_window_3 <= Inter_ref_04_03; |
Inter_V_window_4 <= Inter_ref_04_04;Inter_V_window_5 <= Inter_ref_04_05; |
Inter_V_window_6 <= Inter_ref_04_06;Inter_V_window_7 <= Inter_ref_04_07; |
Inter_V_window_8 <= Inter_ref_04_08; |
end |
else |
begin |
Inter_V_window_0 <= Inter_ref_03_00;Inter_V_window_1 <= Inter_ref_03_01; |
Inter_V_window_2 <= Inter_ref_03_02;Inter_V_window_3 <= Inter_ref_03_03; |
Inter_V_window_4 <= Inter_ref_03_04;Inter_V_window_5 <= Inter_ref_03_05; |
Inter_V_window_6 <= Inter_ref_03_06;Inter_V_window_7 <= Inter_ref_03_07; |
Inter_V_window_8 <= Inter_ref_03_08; |
end |
3'd2: |
if (pos_FracL == `pos_g || pos_FracL == `pos_r || pos_FracL == `pos_k) |
begin |
Inter_V_window_0 <= Inter_ref_05_00;Inter_V_window_1 <= Inter_ref_05_01; |
Inter_V_window_2 <= Inter_ref_05_02;Inter_V_window_3 <= Inter_ref_05_03; |
Inter_V_window_4 <= Inter_ref_05_04;Inter_V_window_5 <= Inter_ref_05_05; |
Inter_V_window_6 <= Inter_ref_05_06;Inter_V_window_7 <= Inter_ref_05_07; |
Inter_V_window_8 <= Inter_ref_05_08; |
end |
else |
begin |
Inter_V_window_0 <= Inter_ref_04_00;Inter_V_window_1 <= Inter_ref_04_01; |
Inter_V_window_2 <= Inter_ref_04_02;Inter_V_window_3 <= Inter_ref_04_03; |
Inter_V_window_4 <= Inter_ref_04_04;Inter_V_window_5 <= Inter_ref_04_05; |
Inter_V_window_6 <= Inter_ref_04_06;Inter_V_window_7 <= Inter_ref_04_07; |
Inter_V_window_8 <= Inter_ref_04_08; |
end |
3'd1: |
if (pos_FracL == `pos_g || pos_FracL == `pos_r || pos_FracL == `pos_k) |
begin |
Inter_V_window_0 <= Inter_ref_06_00;Inter_V_window_1 <= Inter_ref_06_01; |
Inter_V_window_2 <= Inter_ref_06_02;Inter_V_window_3 <= Inter_ref_06_03; |
Inter_V_window_4 <= Inter_ref_06_04;Inter_V_window_5 <= Inter_ref_06_05; |
Inter_V_window_6 <= Inter_ref_06_06;Inter_V_window_7 <= Inter_ref_06_07; |
Inter_V_window_8 <= Inter_ref_06_08; |
end |
else |
begin |
Inter_V_window_0 <= Inter_ref_05_00;Inter_V_window_1 <= Inter_ref_05_01; |
Inter_V_window_2 <= Inter_ref_05_02;Inter_V_window_3 <= Inter_ref_05_03; |
Inter_V_window_4 <= Inter_ref_05_04;Inter_V_window_5 <= Inter_ref_05_05; |
Inter_V_window_6 <= Inter_ref_05_06;Inter_V_window_7 <= Inter_ref_05_07; |
Inter_V_window_8 <= Inter_ref_05_08; |
end |
default: |
begin |
Inter_V_window_0 <= 0;Inter_V_window_1 <= 0;Inter_V_window_2 <= 0; |
Inter_V_window_3 <= 0;Inter_V_window_4 <= 0;Inter_V_window_5 <= 0; |
Inter_V_window_6 <= 0;Inter_V_window_7 <= 0;Inter_V_window_8 <= 0; |
end |
endcase |
4'b0100: //Right top blk4x4 |
case (Inter_V_window_counter) |
3'd4: |
if (pos_FracL == `pos_g || pos_FracL == `pos_r || pos_FracL == `pos_k) |
begin |
Inter_V_window_0 <= Inter_ref_07_00;Inter_V_window_1 <= Inter_ref_07_01; |
Inter_V_window_2 <= Inter_ref_07_02;Inter_V_window_3 <= Inter_ref_07_03; |
Inter_V_window_4 <= Inter_ref_07_04;Inter_V_window_5 <= Inter_ref_07_05; |
Inter_V_window_6 <= Inter_ref_07_06;Inter_V_window_7 <= Inter_ref_07_07; |
Inter_V_window_8 <= Inter_ref_07_08; |
end |
else |
begin |
Inter_V_window_0 <= Inter_ref_06_00;Inter_V_window_1 <= Inter_ref_06_01; |
Inter_V_window_2 <= Inter_ref_06_02;Inter_V_window_3 <= Inter_ref_06_03; |
Inter_V_window_4 <= Inter_ref_06_04;Inter_V_window_5 <= Inter_ref_06_05; |
Inter_V_window_6 <= Inter_ref_06_06;Inter_V_window_7 <= Inter_ref_06_07; |
Inter_V_window_8 <= Inter_ref_06_08; |
end |
3'd3: |
if (pos_FracL == `pos_g || pos_FracL == `pos_r || pos_FracL == `pos_k) |
begin |
Inter_V_window_0 <= Inter_ref_08_00;Inter_V_window_1 <= Inter_ref_08_01; |
Inter_V_window_2 <= Inter_ref_08_02;Inter_V_window_3 <= Inter_ref_08_03; |
Inter_V_window_4 <= Inter_ref_08_04;Inter_V_window_5 <= Inter_ref_08_05; |
Inter_V_window_6 <= Inter_ref_08_06;Inter_V_window_7 <= Inter_ref_08_07; |
Inter_V_window_8 <= Inter_ref_08_08; |
end |
else |
begin |
Inter_V_window_0 <= Inter_ref_07_00;Inter_V_window_1 <= Inter_ref_07_01; |
Inter_V_window_2 <= Inter_ref_07_02;Inter_V_window_3 <= Inter_ref_07_03; |
Inter_V_window_4 <= Inter_ref_07_04;Inter_V_window_5 <= Inter_ref_07_05; |
Inter_V_window_6 <= Inter_ref_07_06;Inter_V_window_7 <= Inter_ref_07_07; |
Inter_V_window_8 <= Inter_ref_07_08; |
end |
3'd2: |
if (pos_FracL == `pos_g || pos_FracL == `pos_r || pos_FracL == `pos_k) |
begin |
Inter_V_window_0 <= Inter_ref_09_00;Inter_V_window_1 <= Inter_ref_09_01; |
Inter_V_window_2 <= Inter_ref_09_02;Inter_V_window_3 <= Inter_ref_09_03; |
Inter_V_window_4 <= Inter_ref_09_04;Inter_V_window_5 <= Inter_ref_09_05; |
Inter_V_window_6 <= Inter_ref_09_06;Inter_V_window_7 <= Inter_ref_09_07; |
Inter_V_window_8 <= Inter_ref_09_08; |
end |
else |
begin |
Inter_V_window_0 <= Inter_ref_08_00;Inter_V_window_1 <= Inter_ref_08_01; |
Inter_V_window_2 <= Inter_ref_08_02;Inter_V_window_3 <= Inter_ref_08_03; |
Inter_V_window_4 <= Inter_ref_08_04;Inter_V_window_5 <= Inter_ref_08_05; |
Inter_V_window_6 <= Inter_ref_08_06;Inter_V_window_7 <= Inter_ref_08_07; |
Inter_V_window_8 <= Inter_ref_08_08; |
end |
3'd1: |
if (pos_FracL == `pos_g || pos_FracL == `pos_r || pos_FracL == `pos_k) |
begin |
Inter_V_window_0 <= Inter_ref_10_00;Inter_V_window_1 <= Inter_ref_10_01; |
Inter_V_window_2 <= Inter_ref_10_02;Inter_V_window_3 <= Inter_ref_10_03; |
Inter_V_window_4 <= Inter_ref_10_04;Inter_V_window_5 <= Inter_ref_10_05; |
Inter_V_window_6 <= Inter_ref_10_06;Inter_V_window_7 <= Inter_ref_10_07; |
Inter_V_window_8 <= Inter_ref_10_08; |
end |
else |
begin |
Inter_V_window_0 <= Inter_ref_09_00;Inter_V_window_1 <= Inter_ref_09_01; |
Inter_V_window_2 <= Inter_ref_09_02;Inter_V_window_3 <= Inter_ref_09_03; |
Inter_V_window_4 <= Inter_ref_09_04;Inter_V_window_5 <= Inter_ref_09_05; |
Inter_V_window_6 <= Inter_ref_09_06;Inter_V_window_7 <= Inter_ref_09_07; |
Inter_V_window_8 <= Inter_ref_09_08; |
end |
default: |
begin |
Inter_V_window_0 <= 0;Inter_V_window_1 <= 0;Inter_V_window_2 <= 0; |
Inter_V_window_3 <= 0;Inter_V_window_4 <= 0;Inter_V_window_5 <= 0; |
Inter_V_window_6 <= 0;Inter_V_window_7 <= 0;Inter_V_window_8 <= 0; |
end |
endcase |
4'b0010: //Left bottom blk4x4 |
case (Inter_V_window_counter) |
3'd4: |
if (pos_FracL == `pos_g || pos_FracL == `pos_r || pos_FracL == `pos_k) |
begin |
Inter_V_window_0 <= Inter_ref_03_04;Inter_V_window_1 <= Inter_ref_03_05; |
Inter_V_window_2 <= Inter_ref_03_06;Inter_V_window_3 <= Inter_ref_03_07; |
Inter_V_window_4 <= Inter_ref_03_08;Inter_V_window_5 <= Inter_ref_03_09; |
Inter_V_window_6 <= Inter_ref_03_10;Inter_V_window_7 <= Inter_ref_03_11; |
Inter_V_window_8 <= Inter_ref_03_12; |
end |
else |
begin |
Inter_V_window_0 <= Inter_ref_02_04;Inter_V_window_1 <= Inter_ref_02_05; |
Inter_V_window_2 <= Inter_ref_02_06;Inter_V_window_3 <= Inter_ref_02_07; |
Inter_V_window_4 <= Inter_ref_02_08;Inter_V_window_5 <= Inter_ref_02_09; |
Inter_V_window_6 <= Inter_ref_02_10;Inter_V_window_7 <= Inter_ref_02_11; |
Inter_V_window_8 <= Inter_ref_02_12; |
end |
3'd3: |
if (pos_FracL == `pos_g || pos_FracL == `pos_r || pos_FracL == `pos_k) |
begin |
Inter_V_window_0 <= Inter_ref_04_04;Inter_V_window_1 <= Inter_ref_04_05; |
Inter_V_window_2 <= Inter_ref_04_06;Inter_V_window_3 <= Inter_ref_04_07; |
Inter_V_window_4 <= Inter_ref_04_08;Inter_V_window_5 <= Inter_ref_04_09; |
Inter_V_window_6 <= Inter_ref_04_10;Inter_V_window_7 <= Inter_ref_04_11; |
Inter_V_window_8 <= Inter_ref_04_12; |
end |
else |
begin |
Inter_V_window_0 <= Inter_ref_03_04;Inter_V_window_1 <= Inter_ref_03_05; |
Inter_V_window_2 <= Inter_ref_03_06;Inter_V_window_3 <= Inter_ref_03_07; |
Inter_V_window_4 <= Inter_ref_03_08;Inter_V_window_5 <= Inter_ref_03_09; |
Inter_V_window_6 <= Inter_ref_03_10;Inter_V_window_7 <= Inter_ref_03_11; |
Inter_V_window_8 <= Inter_ref_03_12; |
end |
3'd2: |
if (pos_FracL == `pos_g || pos_FracL == `pos_r || pos_FracL == `pos_k) |
begin |
Inter_V_window_0 <= Inter_ref_05_04;Inter_V_window_1 <= Inter_ref_05_05; |
Inter_V_window_2 <= Inter_ref_05_06;Inter_V_window_3 <= Inter_ref_05_07; |
Inter_V_window_4 <= Inter_ref_05_08;Inter_V_window_5 <= Inter_ref_05_09; |
Inter_V_window_6 <= Inter_ref_05_10;Inter_V_window_7 <= Inter_ref_05_11; |
Inter_V_window_8 <= Inter_ref_05_12; |
end |
else |
begin |
Inter_V_window_0 <= Inter_ref_04_04;Inter_V_window_1 <= Inter_ref_04_05; |
Inter_V_window_2 <= Inter_ref_04_06;Inter_V_window_3 <= Inter_ref_04_07; |
Inter_V_window_4 <= Inter_ref_04_08;Inter_V_window_5 <= Inter_ref_04_09; |
Inter_V_window_6 <= Inter_ref_04_10;Inter_V_window_7 <= Inter_ref_04_11; |
Inter_V_window_8 <= Inter_ref_04_12; |
end |
3'd1: |
if (pos_FracL == `pos_g || pos_FracL == `pos_r || pos_FracL == `pos_k) |
begin |
Inter_V_window_0 <= Inter_ref_06_04;Inter_V_window_1 <= Inter_ref_06_05; |
Inter_V_window_2 <= Inter_ref_06_06;Inter_V_window_3 <= Inter_ref_06_07; |
Inter_V_window_4 <= Inter_ref_06_08;Inter_V_window_5 <= Inter_ref_06_09; |
Inter_V_window_6 <= Inter_ref_06_10;Inter_V_window_7 <= Inter_ref_06_11; |
Inter_V_window_8 <= Inter_ref_06_12; |
end |
else |
begin |
Inter_V_window_0 <= Inter_ref_05_04;Inter_V_window_1 <= Inter_ref_05_05; |
Inter_V_window_2 <= Inter_ref_05_06;Inter_V_window_3 <= Inter_ref_05_07; |
Inter_V_window_4 <= Inter_ref_05_08;Inter_V_window_5 <= Inter_ref_05_09; |
Inter_V_window_6 <= Inter_ref_05_10;Inter_V_window_7 <= Inter_ref_05_11; |
Inter_V_window_8 <= Inter_ref_05_12; |
end |
default: |
begin |
Inter_V_window_0 <= 0;Inter_V_window_1 <= 0;Inter_V_window_2 <= 0; |
Inter_V_window_3 <= 0;Inter_V_window_4 <= 0;Inter_V_window_5 <= 0; |
Inter_V_window_6 <= 0;Inter_V_window_7 <= 0;Inter_V_window_8 <= 0; |
end |
endcase |
4'b0001: //Right bottom blk4x4 |
case (Inter_V_window_counter) |
3'd4: |
if (pos_FracL == `pos_g || pos_FracL == `pos_r || pos_FracL == `pos_k) |
begin |
Inter_V_window_0 <= Inter_ref_07_04;Inter_V_window_1 <= Inter_ref_07_05; |
Inter_V_window_2 <= Inter_ref_07_06;Inter_V_window_3 <= Inter_ref_07_07; |
Inter_V_window_4 <= Inter_ref_07_08;Inter_V_window_5 <= Inter_ref_07_09; |
Inter_V_window_6 <= Inter_ref_07_10;Inter_V_window_7 <= Inter_ref_07_11; |
Inter_V_window_8 <= Inter_ref_07_12; |
end |
else |
begin |
Inter_V_window_0 <= Inter_ref_06_04;Inter_V_window_1 <= Inter_ref_06_05; |
Inter_V_window_2 <= Inter_ref_06_06;Inter_V_window_3 <= Inter_ref_06_07; |
Inter_V_window_4 <= Inter_ref_06_08;Inter_V_window_5 <= Inter_ref_06_09; |
Inter_V_window_6 <= Inter_ref_06_10;Inter_V_window_7 <= Inter_ref_06_11; |
Inter_V_window_8 <= Inter_ref_06_12; |
end |
3'd3: |
if (pos_FracL == `pos_g || pos_FracL == `pos_r || pos_FracL == `pos_k) |
begin |
Inter_V_window_0 <= Inter_ref_08_04;Inter_V_window_1 <= Inter_ref_08_05; |
Inter_V_window_2 <= Inter_ref_08_06;Inter_V_window_3 <= Inter_ref_08_07; |
Inter_V_window_4 <= Inter_ref_08_08;Inter_V_window_5 <= Inter_ref_08_09; |
Inter_V_window_6 <= Inter_ref_08_10;Inter_V_window_7 <= Inter_ref_08_11; |
Inter_V_window_8 <= Inter_ref_08_12; |
end |
else |
begin |
Inter_V_window_0 <= Inter_ref_07_04;Inter_V_window_1 <= Inter_ref_07_05; |
Inter_V_window_2 <= Inter_ref_07_06;Inter_V_window_3 <= Inter_ref_07_07; |
Inter_V_window_4 <= Inter_ref_07_08;Inter_V_window_5 <= Inter_ref_07_09; |
Inter_V_window_6 <= Inter_ref_07_10;Inter_V_window_7 <= Inter_ref_07_11; |
Inter_V_window_8 <= Inter_ref_07_12; |
end |
3'd2: |
if (pos_FracL == `pos_g || pos_FracL == `pos_r || pos_FracL == `pos_k) |
begin |
Inter_V_window_0 <= Inter_ref_09_04;Inter_V_window_1 <= Inter_ref_09_05; |
Inter_V_window_2 <= Inter_ref_09_06;Inter_V_window_3 <= Inter_ref_09_07; |
Inter_V_window_4 <= Inter_ref_09_08;Inter_V_window_5 <= Inter_ref_09_09; |
Inter_V_window_6 <= Inter_ref_09_10;Inter_V_window_7 <= Inter_ref_09_11; |
Inter_V_window_8 <= Inter_ref_09_12; |
end |
else |
begin |
Inter_V_window_0 <= Inter_ref_08_04;Inter_V_window_1 <= Inter_ref_08_05; |
Inter_V_window_2 <= Inter_ref_08_06;Inter_V_window_3 <= Inter_ref_08_07; |
Inter_V_window_4 <= Inter_ref_08_08;Inter_V_window_5 <= Inter_ref_08_09; |
Inter_V_window_6 <= Inter_ref_08_10;Inter_V_window_7 <= Inter_ref_08_11; |
Inter_V_window_8 <= Inter_ref_08_12; |
end |
3'd1: |
if (pos_FracL == `pos_g || pos_FracL == `pos_r || pos_FracL == `pos_k) |
begin |
Inter_V_window_0 <= Inter_ref_10_04;Inter_V_window_1 <= Inter_ref_10_05; |
Inter_V_window_2 <= Inter_ref_10_06;Inter_V_window_3 <= Inter_ref_10_07; |
Inter_V_window_4 <= Inter_ref_10_08;Inter_V_window_5 <= Inter_ref_10_09; |
Inter_V_window_6 <= Inter_ref_10_10;Inter_V_window_7 <= Inter_ref_10_11; |
Inter_V_window_8 <= Inter_ref_10_12; |
end |
else |
begin |
Inter_V_window_0 <= Inter_ref_09_04;Inter_V_window_1 <= Inter_ref_09_05; |
Inter_V_window_2 <= Inter_ref_09_06;Inter_V_window_3 <= Inter_ref_09_07; |
Inter_V_window_4 <= Inter_ref_09_08;Inter_V_window_5 <= Inter_ref_09_09; |
Inter_V_window_6 <= Inter_ref_09_10;Inter_V_window_7 <= Inter_ref_09_11; |
Inter_V_window_8 <= Inter_ref_09_12; |
end |
default: |
begin |
Inter_V_window_0 <= 0;Inter_V_window_1 <= 0;Inter_V_window_2 <= 0; |
Inter_V_window_3 <= 0;Inter_V_window_4 <= 0;Inter_V_window_5 <= 0; |
Inter_V_window_6 <= 0;Inter_V_window_7 <= 0;Inter_V_window_8 <= 0; |
end |
endcase |
default: |
begin |
Inter_V_window_0 <= 0;Inter_V_window_1 <= 0;Inter_V_window_2 <= 0; |
Inter_V_window_3 <= 0;Inter_V_window_4 <= 0;Inter_V_window_5 <= 0; |
Inter_V_window_6 <= 0;Inter_V_window_7 <= 0;Inter_V_window_8 <= 0; |
end |
endcase |
|
//Luma bilinear window |
always @ (Is_blk4x4_0 or Is_blk4x4_1 or Is_blk4x4_2 or Is_blk4x4_3 or pos_FracL or blk4x4_inter_calculate_counter |
or Inter_ref_02_02 or Inter_ref_03_02 or Inter_ref_04_02 or Inter_ref_05_02 or Inter_ref_06_02 |
or Inter_ref_07_02 or Inter_ref_08_02 or Inter_ref_09_02 or Inter_ref_10_02 |
or Inter_ref_02_03 or Inter_ref_03_03 or Inter_ref_04_03 or Inter_ref_05_03 or Inter_ref_06_03 |
or Inter_ref_07_03 or Inter_ref_08_03 or Inter_ref_09_03 or Inter_ref_10_03 |
or Inter_ref_02_04 or Inter_ref_03_04 or Inter_ref_04_04 or Inter_ref_05_04 or Inter_ref_06_04 |
or Inter_ref_07_04 or Inter_ref_08_04 or Inter_ref_09_04 or Inter_ref_10_04 |
or Inter_ref_02_05 or Inter_ref_03_05 or Inter_ref_04_05 or Inter_ref_05_05 or Inter_ref_06_05 |
or Inter_ref_07_05 or Inter_ref_08_05 or Inter_ref_09_05 or Inter_ref_10_05 |
or Inter_ref_02_06 or Inter_ref_03_06 or Inter_ref_04_06 or Inter_ref_05_06 or Inter_ref_06_06 |
or Inter_ref_07_06 or Inter_ref_08_06 or Inter_ref_09_06 or Inter_ref_10_06 |
or Inter_ref_02_07 or Inter_ref_03_07 or Inter_ref_04_07 or Inter_ref_05_07 or Inter_ref_06_07 |
or Inter_ref_07_07 or Inter_ref_08_07 or Inter_ref_09_07 or Inter_ref_10_07 |
or Inter_ref_02_08 or Inter_ref_03_08 or Inter_ref_04_08 or Inter_ref_05_08 or Inter_ref_06_08 |
or Inter_ref_07_08 or Inter_ref_08_08 or Inter_ref_09_08 or Inter_ref_10_08 |
or Inter_ref_02_09 or Inter_ref_03_09 or Inter_ref_04_09 or Inter_ref_05_09 or Inter_ref_06_09 |
or Inter_ref_07_09 or Inter_ref_08_09 or Inter_ref_09_09 or Inter_ref_10_09 |
or Inter_ref_02_10 or Inter_ref_03_10 or Inter_ref_04_10 or Inter_ref_05_10 or Inter_ref_06_10 |
or Inter_ref_07_10 or Inter_ref_08_10 or Inter_ref_09_10) |
case ({Is_blk4x4_0,Is_blk4x4_1,Is_blk4x4_2,Is_blk4x4_3}) |
4'b1000: //Left top blk4x4 |
case (pos_FracL) |
pos_a,pos_d: |
case (blk4x4_inter_calculate_counter) |
4'd4:begin Inter_bi_window_0 <= Inter_ref_02_02;Inter_bi_window_1 <= Inter_ref_02_03; |
Inter_bi_window_2 <= Inter_ref_02_04;Inter_bi_window_3 <= Inter_ref_02_05; end |
4'd3:begin Inter_bi_window_0 <= Inter_ref_03_02;Inter_bi_window_1 <= Inter_ref_03_03; |
Inter_bi_window_2 <= Inter_ref_03_04;Inter_bi_window_3 <= Inter_ref_03_05; end |
4'd2:begin Inter_bi_window_0 <= Inter_ref_04_02;Inter_bi_window_1 <= Inter_ref_04_03; |
Inter_bi_window_2 <= Inter_ref_04_04;Inter_bi_window_3 <= Inter_ref_04_05; end |
4'd1:begin Inter_bi_window_0 <= Inter_ref_05_02;Inter_bi_window_1 <= Inter_ref_05_03; |
Inter_bi_window_2 <= Inter_ref_05_04;Inter_bi_window_3 <= Inter_ref_05_05; end |
default:begin Inter_bi_window_0 <= 0;Inter_bi_window_1 <= 0; |
Inter_bi_window_2 <= 0;Inter_bi_window_3 <= 0; end |
endcase |
pos_c: |
case (blk4x4_inter_calculate_counter) |
4'd4:begin Inter_bi_window_0 <= Inter_ref_03_02;Inter_bi_window_1 <= Inter_ref_03_03; |
Inter_bi_window_2 <= Inter_ref_03_04;Inter_bi_window_3 <= Inter_ref_03_05; end |
4'd3:begin Inter_bi_window_0 <= Inter_ref_04_02;Inter_bi_window_1 <= Inter_ref_04_03; |
Inter_bi_window_2 <= Inter_ref_04_04;Inter_bi_window_3 <= Inter_ref_04_05; end |
4'd2:begin Inter_bi_window_0 <= Inter_ref_05_02;Inter_bi_window_1 <= Inter_ref_05_03; |
Inter_bi_window_2 <= Inter_ref_05_04;Inter_bi_window_3 <= Inter_ref_05_05; end |
4'd1:begin Inter_bi_window_0 <= Inter_ref_06_02;Inter_bi_window_1 <= Inter_ref_06_03; |
Inter_bi_window_2 <= Inter_ref_06_04;Inter_bi_window_3 <= Inter_ref_06_05; end |
default:begin Inter_bi_window_0 <= 0;Inter_bi_window_1 <= 0; |
Inter_bi_window_2 <= 0;Inter_bi_window_3 <= 0; end |
endcase |
pos_n: |
case (blk4x4_inter_calculate_counter) |
4'd4:begin Inter_bi_window_0 <= Inter_ref_02_03;Inter_bi_window_1 <= Inter_ref_02_04; |
Inter_bi_window_2 <= Inter_ref_02_05;Inter_bi_window_3 <= Inter_ref_02_06; end |
4'd3:begin Inter_bi_window_0 <= Inter_ref_03_03;Inter_bi_window_1 <= Inter_ref_03_04; |
Inter_bi_window_2 <= Inter_ref_03_05;Inter_bi_window_3 <= Inter_ref_03_06; end |
4'd2:begin Inter_bi_window_0 <= Inter_ref_04_03;Inter_bi_window_1 <= Inter_ref_04_04; |
Inter_bi_window_2 <= Inter_ref_04_05;Inter_bi_window_3 <= Inter_ref_04_06; end |
4'd1:begin Inter_bi_window_0 <= Inter_ref_05_03;Inter_bi_window_1 <= Inter_ref_05_04; |
Inter_bi_window_2 <= Inter_ref_05_05;Inter_bi_window_3 <= Inter_ref_05_06; end |
default:begin Inter_bi_window_0 <= 0;Inter_bi_window_1 <= 0; |
Inter_bi_window_2 <= 0;Inter_bi_window_3 <= 0; end |
endcase |
default: |
begin Inter_bi_window_0 <= 0;Inter_bi_window_1 <= 0; |
Inter_bi_window_2 <= 0;Inter_bi_window_3 <= 0; end |
endcase |
4'b0100: //Right top blk4x4 |
case (pos_FracL) |
pos_a,pos_d: |
case (blk4x4_inter_calculate_counter) |
4'd4:begin Inter_bi_window_0 <= Inter_ref_06_02;Inter_bi_window_1 <= Inter_ref_06_03; |
Inter_bi_window_2 <= Inter_ref_06_04;Inter_bi_window_3 <= Inter_ref_06_05; end |
4'd3:begin Inter_bi_window_0 <= Inter_ref_07_02;Inter_bi_window_1 <= Inter_ref_07_03; |
Inter_bi_window_2 <= Inter_ref_07_04;Inter_bi_window_3 <= Inter_ref_07_05; end |
4'd2:begin Inter_bi_window_0 <= Inter_ref_08_02;Inter_bi_window_1 <= Inter_ref_08_03; |
Inter_bi_window_2 <= Inter_ref_08_04;Inter_bi_window_3 <= Inter_ref_08_05; end |
4'd1:begin Inter_bi_window_0 <= Inter_ref_09_02;Inter_bi_window_1 <= Inter_ref_09_03; |
Inter_bi_window_2 <= Inter_ref_09_04;Inter_bi_window_3 <= Inter_ref_09_05; end |
default:begin Inter_bi_window_0 <= 0;Inter_bi_window_1 <= 0; |
Inter_bi_window_2 <= 0;Inter_bi_window_3 <= 0; end |
endcase |
pos_c: |
case (blk4x4_inter_calculate_counter) |
4'd4:begin Inter_bi_window_0 <= Inter_ref_07_02;Inter_bi_window_1 <= Inter_ref_07_03; |
Inter_bi_window_2 <= Inter_ref_07_04;Inter_bi_window_3 <= Inter_ref_07_05; end |
4'd3:begin Inter_bi_window_0 <= Inter_ref_08_02;Inter_bi_window_1 <= Inter_ref_08_03; |
Inter_bi_window_2 <= Inter_ref_08_04;Inter_bi_window_3 <= Inter_ref_08_05; end |
4'd2:begin Inter_bi_window_0 <= Inter_ref_09_02;Inter_bi_window_1 <= Inter_ref_09_03; |
Inter_bi_window_2 <= Inter_ref_09_04;Inter_bi_window_3 <= Inter_ref_09_05; end |
4'd1:begin Inter_bi_window_0 <= Inter_ref_10_02;Inter_bi_window_1 <= Inter_ref_10_03; |
Inter_bi_window_2 <= Inter_ref_10_04;Inter_bi_window_3 <= Inter_ref_10_05; end |
default:begin Inter_bi_window_0 <= 0;Inter_bi_window_1 <= 0; |
Inter_bi_window_2 <= 0;Inter_bi_window_3 <= 0; end |
endcase |
pos_n: |
case (blk4x4_inter_calculate_counter) |
4'd4:begin Inter_bi_window_0 <= Inter_ref_06_03;Inter_bi_window_1 <= Inter_ref_06_04; |
Inter_bi_window_2 <= Inter_ref_06_05;Inter_bi_window_3 <= Inter_ref_06_06; end |
4'd3:begin Inter_bi_window_0 <= Inter_ref_07_03;Inter_bi_window_1 <= Inter_ref_07_04; |
Inter_bi_window_2 <= Inter_ref_07_05;Inter_bi_window_3 <= Inter_ref_07_06; end |
4'd2:begin Inter_bi_window_0 <= Inter_ref_08_03;Inter_bi_window_1 <= Inter_ref_08_04; |
Inter_bi_window_2 <= Inter_ref_08_05;Inter_bi_window_3 <= Inter_ref_08_06; end |
4'd1:begin Inter_bi_window_0 <= Inter_ref_09_03;Inter_bi_window_1 <= Inter_ref_09_04; |
Inter_bi_window_2 <= Inter_ref_09_05;Inter_bi_window_3 <= Inter_ref_09_06; end |
default:begin Inter_bi_window_0 <= 0;Inter_bi_window_1 <= 0; |
Inter_bi_window_2 <= 0;Inter_bi_window_3 <= 0; end |
endcase |
default: |
begin Inter_bi_window_0 <= 0;Inter_bi_window_1 <= 0; |
Inter_bi_window_2 <= 0;Inter_bi_window_3 <= 0; end |
endcase |
4'b0010: //Left bottom blk4x4 |
case (pos_FracL) |
pos_a,pos_d: |
case (blk4x4_inter_calculate_counter) |
4'd4:begin Inter_bi_window_0 <= Inter_ref_02_06;Inter_bi_window_1 <= Inter_ref_02_07; |
Inter_bi_window_2 <= Inter_ref_02_08;Inter_bi_window_3 <= Inter_ref_02_09; end |
4'd3:begin Inter_bi_window_0 <= Inter_ref_03_06;Inter_bi_window_1 <= Inter_ref_03_07; |
Inter_bi_window_2 <= Inter_ref_03_08;Inter_bi_window_3 <= Inter_ref_03_09; end |
4'd2:begin Inter_bi_window_0 <= Inter_ref_04_06;Inter_bi_window_1 <= Inter_ref_04_07; |
Inter_bi_window_2 <= Inter_ref_04_08;Inter_bi_window_3 <= Inter_ref_04_09; end |
4'd1:begin Inter_bi_window_0 <= Inter_ref_05_06;Inter_bi_window_1 <= Inter_ref_05_07; |
Inter_bi_window_2 <= Inter_ref_05_08;Inter_bi_window_3 <= Inter_ref_05_09; end |
default:begin Inter_bi_window_0 <= 0;Inter_bi_window_1 <= 0; |
Inter_bi_window_2 <= 0;Inter_bi_window_3 <= 0; end |
endcase |
pos_c: |
case (blk4x4_inter_calculate_counter) |
4'd4:begin Inter_bi_window_0 <= Inter_ref_03_06;Inter_bi_window_1 <= Inter_ref_03_07; |
Inter_bi_window_2 <= Inter_ref_03_08;Inter_bi_window_3 <= Inter_ref_03_09; end |
4'd3:begin Inter_bi_window_0 <= Inter_ref_04_06;Inter_bi_window_1 <= Inter_ref_04_07; |
Inter_bi_window_2 <= Inter_ref_04_08;Inter_bi_window_3 <= Inter_ref_04_09; end |
4'd2:begin Inter_bi_window_0 <= Inter_ref_05_06;Inter_bi_window_1 <= Inter_ref_05_07; |
Inter_bi_window_2 <= Inter_ref_05_08;Inter_bi_window_3 <= Inter_ref_05_09; end |
4'd1:begin Inter_bi_window_0 <= Inter_ref_06_06;Inter_bi_window_1 <= Inter_ref_06_07; |
Inter_bi_window_2 <= Inter_ref_06_08;Inter_bi_window_3 <= Inter_ref_06_09; end |
default:begin Inter_bi_window_0 <= 0;Inter_bi_window_1 <= 0; |
Inter_bi_window_2 <= 0;Inter_bi_window_3 <= 0; end |
endcase |
pos_n: |
case (blk4x4_inter_calculate_counter) |
4'd4:begin Inter_bi_window_0 <= Inter_ref_02_07;Inter_bi_window_1 <= Inter_ref_02_08; |
Inter_bi_window_2 <= Inter_ref_02_09;Inter_bi_window_3 <= Inter_ref_02_10; end |
4'd3:begin Inter_bi_window_0 <= Inter_ref_03_07;Inter_bi_window_1 <= Inter_ref_03_08; |
Inter_bi_window_2 <= Inter_ref_03_09;Inter_bi_window_3 <= Inter_ref_03_10; end |
4'd2:begin Inter_bi_window_0 <= Inter_ref_04_07;Inter_bi_window_1 <= Inter_ref_04_08; |
Inter_bi_window_2 <= Inter_ref_04_09;Inter_bi_window_3 <= Inter_ref_04_10; end |
4'd1:begin Inter_bi_window_0 <= Inter_ref_05_07;Inter_bi_window_1 <= Inter_ref_05_08; |
Inter_bi_window_2 <= Inter_ref_05_09;Inter_bi_window_3 <= Inter_ref_05_10; end |
default:begin Inter_bi_window_0 <= 0;Inter_bi_window_1 <= 0; |
Inter_bi_window_2 <= 0;Inter_bi_window_3 <= 0; end |
endcase |
default: |
begin Inter_bi_window_0 <= 0;Inter_bi_window_1 <= 0; |
Inter_bi_window_2 <= 0;Inter_bi_window_3 <= 0; end |
endcase |
4'b0001: //Right bottom blk4x4 |
case (pos_FracL) |
pos_a,pos_d: |
case (blk4x4_inter_calculate_counter) |
4'd4:begin Inter_bi_window_0 <= Inter_ref_06_06;Inter_bi_window_1 <= Inter_ref_06_07; |
Inter_bi_window_2 <= Inter_ref_06_08;Inter_bi_window_3 <= Inter_ref_06_09; end |
4'd3:begin Inter_bi_window_0 <= Inter_ref_07_06;Inter_bi_window_1 <= Inter_ref_07_07; |
Inter_bi_window_2 <= Inter_ref_07_08;Inter_bi_window_3 <= Inter_ref_07_09; end |
4'd2:begin Inter_bi_window_0 <= Inter_ref_08_06;Inter_bi_window_1 <= Inter_ref_08_07; |
Inter_bi_window_2 <= Inter_ref_08_08;Inter_bi_window_3 <= Inter_ref_08_09; end |
4'd1:begin Inter_bi_window_0 <= Inter_ref_09_06;Inter_bi_window_1 <= Inter_ref_09_07; |
Inter_bi_window_2 <= Inter_ref_09_08;Inter_bi_window_3 <= Inter_ref_09_09; end |
default:begin Inter_bi_window_0 <= 0;Inter_bi_window_1 <= 0; |
Inter_bi_window_2 <= 0;Inter_bi_window_3 <= 0; end |
endcase |
pos_c: |
case (blk4x4_inter_calculate_counter) |
4'd4:begin Inter_bi_window_0 <= Inter_ref_07_06;Inter_bi_window_1 <= Inter_ref_07_07; |
Inter_bi_window_2 <= Inter_ref_07_08;Inter_bi_window_3 <= Inter_ref_07_09; end |
4'd3:begin Inter_bi_window_0 <= Inter_ref_08_06;Inter_bi_window_1 <= Inter_ref_08_07; |
Inter_bi_window_2 <= Inter_ref_08_08;Inter_bi_window_3 <= Inter_ref_08_09; end |
4'd2:begin Inter_bi_window_0 <= Inter_ref_09_06;Inter_bi_window_1 <= Inter_ref_09_07; |
Inter_bi_window_2 <= Inter_ref_09_08;Inter_bi_window_3 <= Inter_ref_09_09; end |
4'd1:begin Inter_bi_window_0 <= Inter_ref_10_06;Inter_bi_window_1 <= Inter_ref_10_07; |
Inter_bi_window_2 <= Inter_ref_10_08;Inter_bi_window_3 <= Inter_ref_10_09; end |
default:begin Inter_bi_window_0 <= 0;Inter_bi_window_1 <= 0; |
Inter_bi_window_2 <= 0;Inter_bi_window_3 <= 0; end |
endcase |
pos_n: |
case (blk4x4_inter_calculate_counter) |
4'd4:begin Inter_bi_window_0 <= Inter_ref_06_07;Inter_bi_window_1 <= Inter_ref_06_08; |
Inter_bi_window_2 <= Inter_ref_06_09;Inter_bi_window_3 <= Inter_ref_06_10; end |
4'd3:begin Inter_bi_window_0 <= Inter_ref_07_07;Inter_bi_window_1 <= Inter_ref_07_08; |
Inter_bi_window_2 <= Inter_ref_07_09;Inter_bi_window_3 <= Inter_ref_07_10; end |
4'd2:begin Inter_bi_window_0 <= Inter_ref_08_07;Inter_bi_window_1 <= Inter_ref_08_08; |
Inter_bi_window_2 <= Inter_ref_08_09;Inter_bi_window_3 <= Inter_ref_08_10; end |
4'd1:begin Inter_bi_window_0 <= Inter_ref_09_07;Inter_bi_window_1 <= Inter_ref_09_08; |
Inter_bi_window_2 <= Inter_ref_09_09;Inter_bi_window_3 <= Inter_ref_09_10; end |
default:begin Inter_bi_window_0 <= 0;Inter_bi_window_1 <= 0; |
Inter_bi_window_2 <= 0;Inter_bi_window_3 <= 0; end |
endcase |
default: |
begin Inter_bi_window_0 <= 0;Inter_bi_window_1 <= 0; |
Inter_bi_window_2 <= 0;Inter_bi_window_3 <= 0; end |
endcase |
default: |
begin Inter_bi_window_0 <= 0;Inter_bi_window_1 <= 0; |
Inter_bi_window_2 <= 0;Inter_bi_window_3 <= 0; end |
endcase |
|
//chroma sliding window:Inter_C_window_0 ~ Inter_C_window_3 |
always @ (IsInterChroma or blk4x4_inter_calculate_counter or mv_below8x8_curr |
or Inter_ref_00_00 or Inter_ref_01_00 or Inter_ref_02_00 or Inter_ref_03_00 or Inter_ref_04_00 |
or Inter_ref_00_01 or Inter_ref_01_01 or Inter_ref_02_01 or Inter_ref_03_01 or Inter_ref_04_01 |
or Inter_ref_00_02 or Inter_ref_01_02 or Inter_ref_02_02 or Inter_ref_03_02 or Inter_ref_04_02 |
or Inter_ref_00_03 or Inter_ref_01_03 or Inter_ref_02_03 or Inter_ref_03_03 or Inter_ref_04_03 |
or Inter_ref_00_04 or Inter_ref_01_04 or Inter_ref_02_04 or Inter_ref_03_04 or Inter_ref_04_04 |
) |
if (IsInterChroma && mv_below8x8_curr == 1'b0) |
case (blk4x4_inter_calculate_counter) |
4'd4: |
begin |
Inter_C_window_0_0 <= Inter_ref_00_00; Inter_C_window_1_0 <= Inter_ref_01_00; |
Inter_C_window_2_0 <= Inter_ref_02_00; |
Inter_C_window_0_1 <= Inter_ref_00_01; Inter_C_window_1_1 <= Inter_ref_01_01; |
Inter_C_window_2_1 <= Inter_ref_02_01; |
Inter_C_window_0_2 <= Inter_ref_00_02; Inter_C_window_1_2 <= Inter_ref_01_02; |
Inter_C_window_2_2 <= Inter_ref_02_02; |
end |
4'd3: |
begin |
Inter_C_window_0_0 <= Inter_ref_02_00; Inter_C_window_1_0 <= Inter_ref_03_00; |
Inter_C_window_2_0 <= Inter_ref_04_00; |
Inter_C_window_0_1 <= Inter_ref_02_01; Inter_C_window_1_1 <= Inter_ref_03_01; |
Inter_C_window_2_1 <= Inter_ref_04_01; |
Inter_C_window_0_2 <= Inter_ref_02_02; Inter_C_window_1_2 <= Inter_ref_03_02; |
Inter_C_window_2_2 <= Inter_ref_04_02; |
end |
4'd2: |
begin |
Inter_C_window_0_0 <= Inter_ref_00_02; Inter_C_window_1_0 <= Inter_ref_01_02; |
Inter_C_window_2_0 <= Inter_ref_02_02; |
Inter_C_window_0_1 <= Inter_ref_00_03; Inter_C_window_1_1 <= Inter_ref_01_03; |
Inter_C_window_2_1 <= Inter_ref_02_03; |
Inter_C_window_0_2 <= Inter_ref_00_04; Inter_C_window_1_2 <= Inter_ref_01_04; |
Inter_C_window_2_2 <= Inter_ref_02_04; |
end |
4'd1: |
begin |
Inter_C_window_0_0 <= Inter_ref_02_02; Inter_C_window_1_0 <= Inter_ref_03_02; |
Inter_C_window_2_0 <= Inter_ref_04_02; |
Inter_C_window_0_1 <= Inter_ref_02_03; Inter_C_window_1_1 <= Inter_ref_03_03; |
Inter_C_window_2_1 <= Inter_ref_04_03; |
Inter_C_window_0_2 <= Inter_ref_02_04; Inter_C_window_1_2 <= Inter_ref_03_04; |
Inter_C_window_2_2 <= Inter_ref_04_04; |
end |
default: |
begin |
Inter_C_window_0_0 <= 0; Inter_C_window_1_0 <= 0;Inter_C_window_2_0 <= 0; |
Inter_C_window_0_1 <= 0; Inter_C_window_1_1 <= 0;Inter_C_window_2_1 <= 0; |
Inter_C_window_0_2 <= 0; Inter_C_window_1_2 <= 0;Inter_C_window_2_2 <= 0; |
end |
endcase |
else if (IsInterChroma && mv_below8x8_curr == 1'b1) |
case (blk4x4_inter_calculate_counter) |
4'd1: |
begin |
Inter_C_window_0_0 <= Inter_ref_00_00; Inter_C_window_1_0 <= Inter_ref_01_00; |
Inter_C_window_2_0 <= Inter_ref_02_00; |
Inter_C_window_0_1 <= Inter_ref_00_01; Inter_C_window_1_1 <= Inter_ref_01_01; |
Inter_C_window_2_1 <= Inter_ref_02_01; |
Inter_C_window_0_2 <= Inter_ref_00_02; Inter_C_window_1_2 <= Inter_ref_01_02; |
Inter_C_window_2_2 <= Inter_ref_02_02; |
end |
default: |
begin |
Inter_C_window_0_0 <= 0; Inter_C_window_1_0 <= 0;Inter_C_window_2_0 <= 0; |
Inter_C_window_0_1 <= 0; Inter_C_window_1_1 <= 0;Inter_C_window_2_1 <= 0; |
Inter_C_window_0_2 <= 0; Inter_C_window_1_2 <= 0;Inter_C_window_2_2 <= 0; |
end |
endcase |
else |
begin |
Inter_C_window_0_0 <= 0; Inter_C_window_1_0 <= 0;Inter_C_window_2_0 <= 0; |
Inter_C_window_0_1 <= 0; Inter_C_window_1_1 <= 0;Inter_C_window_2_1 <= 0; |
Inter_C_window_0_2 <= 0; Inter_C_window_1_2 <= 0;Inter_C_window_2_2 <= 0; |
end |
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endmodule |
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