URL
https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk
Subversion Repositories open8_urisc
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- from Rev 274 to Rev 275
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Rev 274 → Rev 275
/open8_urisc/trunk/VHDL/o8_trig_delay.vhd
35,7 → 35,7
-- 0x3 AAAAAAAA Pulse Width Byte 0 (RW) |
-- 0x4 AAAAAAAA Pulse Width Byte 1 (RW) |
-- 0x5 AAAAAAAA Pulse Width Byte 2 (RW) |
-- 0x6 EDCBAA-- Time Configuration (RW*) |
-- 0x6 EDCBAA-- Timer Configuration (RW*) |
-- A: Interrupt Select |
-- 00 - Disabled |
-- 01 - Interrupt on trigger event |