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Subversion Repositories open8_urisc
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/open8_urisc/trunk/VHDL
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Rev 156 → Rev 155
/Open8.vhd
78,8 → 78,6
-- corruption issues. |
-- Seth Henry 07/26/11 Optimized logic in ALU, stack pointer, and data path |
-- sections. |
-- Seth Henry 07/27/11 Optimized logic for timing, merged blocks into |
-- single entity. |
|
library ieee; |
use ieee.std_logic_1164.all; |
112,11 → 110,645
Wr_Enable : out std_logic ); |
end entity; |
|
architecture behave of Open8_CPU is |
|
architecture rtl of Open8_CPU is |
subtype OPCODE_TYPE is std_logic_vector(4 downto 0); |
subtype SUBOP_TYPE is std_logic_vector(2 downto 0); |
|
-- Most of the ALU instructions are the same as their Opcode equivalents with |
-- three exceptions (for IDLE, UPP2, and MUL2) |
constant ALU_INC : OPCODE_TYPE := "00000"; -- x"00" |
constant ALU_ADC : OPCODE_TYPE := "00001"; -- x"01" |
constant ALU_TX0 : OPCODE_TYPE := "00010"; -- x"02" |
constant ALU_OR : OPCODE_TYPE := "00011"; -- x"03" |
constant ALU_AND : OPCODE_TYPE := "00100"; -- x"04" |
constant ALU_XOR : OPCODE_TYPE := "00101"; -- x"05" |
constant ALU_ROL : OPCODE_TYPE := "00110"; -- x"06" |
constant ALU_ROR : OPCODE_TYPE := "00111"; -- x"07" |
constant ALU_DEC : OPCODE_TYPE := "01000"; -- x"08" |
constant ALU_SBC : OPCODE_TYPE := "01001"; -- x"09" |
constant ALU_ADD : OPCODE_TYPE := "01010"; -- x"0A" |
constant ALU_STP : OPCODE_TYPE := "01011"; -- x"0B" |
constant ALU_BTT : OPCODE_TYPE := "01100"; -- x"0C" |
constant ALU_CLP : OPCODE_TYPE := "01101"; -- x"0D" |
constant ALU_T0X : OPCODE_TYPE := "01110"; -- x"0E" |
constant ALU_CMP : OPCODE_TYPE := "01111"; -- x"0F" |
constant ALU_POP : OPCODE_TYPE := "10001"; -- x"11" |
constant ALU_MUL : OPCODE_TYPE := "10110"; -- x"16" |
constant ALU_UPP : OPCODE_TYPE := "11000"; -- x"18" |
constant ALU_LDI : OPCODE_TYPE := "11100"; -- x"1C" |
constant ALU_LDX : OPCODE_TYPE := "11110"; -- x"1E" |
|
constant ALU_IDLE : OPCODE_TYPE := "10000"; -- x"10" |
constant ALU_UPP2 : OPCODE_TYPE := "10010"; -- x"12" |
constant ALU_RFLG : OPCODE_TYPE := "10011"; -- x"13" |
|
constant FL_ZERO : integer := 0; |
constant FL_CARRY : integer := 1; |
constant FL_NEG : integer := 2; |
constant FL_INT_EN : integer := 3; |
constant FL_GP1 : integer := 4; |
constant FL_GP2 : integer := 5; |
constant FL_GP3 : integer := 6; |
constant FL_GP4 : integer := 7; |
|
type ALU_CTRL_TYPE is record |
Oper : OPCODE_TYPE; |
Reg : SUBOP_TYPE; |
Data : DATA_TYPE; |
end record; |
|
constant ACCUM : SUBOP_TYPE := "000"; |
constant INT_FLAG : SUBOP_TYPE := "011"; |
|
-- There are only 8 byte-wide registers - and the write register is always 0, |
-- so there is little point in making a RAM out of this |
type REGFILE_TYPE is array (0 to 7) of DATA_TYPE; |
|
subtype FLAG_TYPE is DATA_TYPE; |
|
type PC_MODES is ( PC_IDLE, PC_REV1, PC_REV2, PC_INCR, PC_LOAD ); |
|
type PC_CTRL_TYPE is record |
Oper : PC_MODES; |
Offset : DATA_TYPE; |
Addr : ADDRESS_TYPE; |
end record; |
|
type SP_MODES is ( SP_IDLE, SP_RSET, SP_POP, SP_PUSH ); |
|
type SP_CTRL_TYPE is record |
Oper : SP_MODES; |
Addr : ADDRESS_TYPE; |
end record; |
|
type INT_CTRL_TYPE is record |
Mask_Set : std_logic; |
Mask_Data : DATA_TYPE; |
Soft_Ints : INTERRUPT_BUNDLE; |
Incr_ISR : std_logic; |
end record; |
|
type AS_MODES is ( ADDR_PC, ADDR_SP, ADDR_IMM, ADDR_ISR); |
|
type ADDR_CTRL_TYPE is record |
Src : AS_MODES; |
end record; |
|
type DP_MODES is ( DATA_IDLE, DATA_REG, DATA_FLAG, DATA_PC ); |
|
type DATA_CTRL_TYPE is record |
Src : DP_MODES; |
Reg : SUBOP_TYPE; |
end record; |
|
signal Halt : std_logic; |
signal ALU_Ctrl : ALU_CTRL_TYPE; |
signal ALU_Regs : REGFILE_TYPE; |
signal ALU_Flags : FLAG_TYPE; |
signal PC_Ctrl : PC_CTRL_TYPE; |
signal SP_Ctrl : SP_CTRL_TYPE; |
signal AS_Ctrl : ADDR_CTRL_TYPE; |
signal DP_Ctrl : DATA_CTRL_TYPE; |
signal INT_Ctrl : INT_CTRL_TYPE; |
signal Int_Req, Int_Ack : std_logic; |
signal Int_RTI : std_logic; |
signal Int_Mask : DATA_TYPE; |
signal PC : ADDRESS_TYPE; |
signal SP : ADDRESS_TYPE; |
signal ISR : ADDRESS_TYPE; |
signal IMM : ADDRESS_TYPE; |
begin |
|
Halt_Disabled_fn: if( not Enable_CPU_Halt )generate |
Halt <= '0'; |
end generate; |
|
Halt_Enabled_fn: if( Enable_CPU_Halt )generate |
Halt <= CPU_Halt; |
end generate; |
|
------------------------------------------------------------------------------- |
-- ALU (Arithmetic / Logic Unit) |
-- Notes: |
-- 1) Infers a multiplier in Xilinx/Altera parts - should be checked in others |
------------------------------------------------------------------------------- |
|
Open8_ALU : block is |
-- Preinitialization is for simulation only - check actual reset conditions |
signal Regfile : REGFILE_TYPE := (others => (others => '0') ); |
signal Flags : FLAG_TYPE := (others => '0'); |
signal Mult : ADDRESS_TYPE := (others => '0'); |
begin |
|
ALU_Regs <= Regfile; |
ALU_Flags <= Flags; |
|
-- We need to infer a hardware multipler, so we create a special clocked |
-- process with no reset or clock enable |
Multiplier: process( Clock ) |
begin |
if( rising_edge(Clock) )then |
Mult <= Regfile(0) * |
Regfile(conv_integer(ALU_Ctrl.Reg)); |
end if; |
end process; |
|
ALU: process( Reset, Clock ) |
variable Sum : std_logic_vector(8 downto 0) := "000000000"; |
variable Index : integer range 0 to 7 := 0; |
variable Temp : std_logic_vector(8 downto 0); |
begin |
if( Reset = Reset_Level )then |
for i in 0 to 7 loop |
Regfile(i) <= (others => '0'); |
end loop; |
Flags <= x"00"; |
elsif( rising_edge(Clock) )then |
Temp := (others => '0'); |
Index := conv_integer(ALU_Ctrl.Reg); |
if( Halt = '0' )then |
case ALU_Ctrl.Oper is |
when ALU_INC | ALU_UPP => -- Rn = Rn + 1 : Flags N,C,Z |
Sum := ("0" & x"01") + |
("0" & Regfile(Index)); |
Flags(FL_CARRY) <= Sum(8); |
Regfile(Index) <= Sum(7 downto 0); |
-- ALU_INC and ALU_UPP are essentially the same, except that ALU_UPP |
-- doesn't set the N or Z flags. Note that the MSB can be used to |
-- distinguish between the two ALU modes. |
if( ALU_Ctrl.Oper(4) = '0' )then |
Flags(FL_ZERO) <= '0'; |
if( Sum(7 downto 0) = 0 )then |
Flags(FL_ZERO)<= '1'; |
end if; |
Flags(FL_NEG) <= Sum(7); |
end if; |
|
when ALU_UPP2 => -- Rn = Rn + C |
Sum := ("0" & x"00") + |
("0" & Regfile(Index)) + |
Flags(FL_CARRY); |
Flags(FL_CARRY) <= Sum(8); |
Regfile(Index) <= Sum(7 downto 0); |
|
when ALU_ADC => -- R0 = R0 + Rn + C : Flags N,C,Z |
Sum := ("0" & Regfile(0)) + |
("0" & Regfile(Index)) + |
Flags(FL_CARRY); |
Flags(FL_ZERO) <= '0'; |
if( Sum(7 downto 0) = 0 )then |
Flags(FL_ZERO) <= '1'; |
end if; |
Flags(FL_CARRY) <= Sum(8); |
Flags(FL_NEG) <= Sum(7); |
Regfile(0) <= Sum(7 downto 0); |
|
when ALU_TX0 => -- R0 = Rn : Flags N,Z |
Temp := "0" & Regfile(Index); |
Flags(FL_ZERO) <= '0'; |
if( Temp(7 downto 0) = 0 )then |
Flags(FL_ZERO) <= '1'; |
end if; |
Flags(FL_NEG) <= Temp(7); |
Regfile(0) <= Temp(7 downto 0); |
|
when ALU_OR => -- R0 = R0 | Rn : Flags N,Z |
Temp(7 downto 0) := Regfile(0) or Regfile(Index); |
Flags(FL_ZERO) <= '0'; |
if( Temp(7 downto 0) = 0 )then |
Flags(FL_ZERO) <= '1'; |
end if; |
Flags(FL_NEG) <= Temp(7); |
Regfile(0) <= Temp(7 downto 0); |
|
when ALU_AND => -- R0 = R0 & Rn : Flags N,Z |
Temp(7 downto 0) := Regfile(0) and Regfile(Index); |
Flags(FL_ZERO) <= '0'; |
if( Temp(7 downto 0) = 0 )then |
Flags(FL_ZERO) <= '1'; |
end if; |
Flags(FL_NEG) <= Temp(7); |
Regfile(0) <= Temp(7 downto 0); |
|
when ALU_XOR => -- R0 = R0 ^ Rn : Flags N,Z |
Temp(7 downto 0) := Regfile(0) xor Regfile(Index); |
Flags(FL_ZERO) <= '0'; |
if( Temp(7 downto 0) = 0 )then |
Flags(FL_ZERO) <= '1'; |
end if; |
Flags(FL_NEG) <= Temp(7); |
Regfile(0) <= Temp(7 downto 0); |
|
when ALU_ROL => -- Rn = Rn<<1,C : Flags N,C,Z |
Temp := Regfile(Index) & Flags(FL_CARRY); |
Flags(FL_ZERO) <= '0'; |
if( Temp(7 downto 0) = 0 )then |
Flags(FL_ZERO) <= '1'; |
end if; |
Flags(FL_CARRY) <= Temp(8); |
Flags(FL_NEG) <= Temp(7); |
Regfile(Index) <= Temp(7 downto 0); |
|
when ALU_ROR => -- Rn = C,Rn>>1 : Flags N,C,Z |
Temp := Regfile(Index)(0) & Flags(FL_CARRY) & |
Regfile(Index)(7 downto 1); |
Flags(FL_ZERO) <= '0'; |
if( Temp(7 downto 0) = 0 )then |
Flags(FL_ZERO) <= '1'; |
end if; |
Flags(FL_CARRY) <= Temp(8); |
Flags(FL_NEG) <= Temp(7); |
Regfile(Index) <= Temp(7 downto 0); |
|
when ALU_DEC => -- Rn = Rn - 1 : Flags N,C,Z |
Sum := ("0" & Regfile(Index)) + |
("0" & x"FF"); |
Flags(FL_ZERO) <= '0'; |
if( Sum(7 downto 0) = 0 )then |
Flags(FL_ZERO) <= '1'; |
end if; |
Flags(FL_CARRY) <= Sum(8); |
Flags(FL_NEG) <= Sum(7); |
Regfile(Index) <= Sum(7 downto 0); |
|
when ALU_SBC => -- Rn = R0 - Rn - C : Flags N,C,Z |
Sum := ("0" & Regfile(0)) + |
("0" & (not Regfile(Index))) + |
Flags(FL_CARRY); |
Flags(FL_ZERO) <= '0'; |
if( Sum(7 downto 0) = 0 )then |
Flags(FL_ZERO) <= '1'; |
end if; |
Flags(FL_CARRY) <= Sum(8); |
Flags(FL_NEG) <= Sum(7); |
Regfile(0) <= Sum(7 downto 0); |
|
when ALU_ADD => -- R0 = R0 + Rn : Flags N,C,Z |
Sum := ("0" & Regfile(0)) + |
("0" & Regfile(Index)); |
Flags(FL_CARRY) <= Sum(8); |
Regfile(0) <= Sum(7 downto 0); |
Flags(FL_ZERO) <= '0'; |
if( Sum(7 downto 0) = 0 )then |
Flags(FL_ZERO) <= '1'; |
end if; |
Flags(FL_NEG) <= Sum(7); |
|
when ALU_STP => -- Sets bit(n) in the Flags register |
Flags(Index) <= '1'; |
|
when ALU_BTT => -- Z = !R0(N), N = R0(7) |
Flags(FL_ZERO) <= not Regfile(0)(Index); |
Flags(FL_NEG) <= Regfile(0)(7); |
|
when ALU_CLP => -- Clears bit(n) in the Flags register |
Flags(Index) <= '0'; |
|
when ALU_T0X => -- Rn = R0 : Flags N,Z |
Temp := "0" & Regfile(0); |
Flags(FL_ZERO) <= '0'; |
if( Temp(7 downto 0) = 0 )then |
Flags(FL_ZERO) <= '1'; |
end if; |
Flags(FL_NEG) <= Temp(7); |
Regfile(Index) <= Temp(7 downto 0); |
|
when ALU_CMP => -- Sets Flags on R0 - Rn : Flags N,C,Z |
Sum := ("0" & Regfile(0)) + |
("0" & (not Regfile(Index))) + |
'1'; |
Flags(FL_ZERO) <= '0'; |
if( Sum(7 downto 0) = 0 )then |
Flags(FL_ZERO) <= '1'; |
end if; |
Flags(FL_CARRY) <= Sum(8); |
Flags(FL_NEG) <= Sum(7); |
|
when ALU_MUL => -- Stage 1 of 2 {R1:R0} = R0 * Rn : Flags Z |
Regfile(0) <= Mult(7 downto 0); |
Regfile(1) <= Mult(15 downto 8); |
Flags(FL_ZERO) <= '0'; |
if( Mult = 0 )then |
Flags(FL_ZERO) <= '1'; |
end if; |
|
when ALU_LDI | ALU_POP => -- Rn <= Data : Flags N,Z |
-- The POP instruction doesn't alter the flags, so we need to check |
if( ALU_Ctrl.Oper = ALU_LDI )then |
Flags(FL_ZERO) <= '0'; |
if( ALU_Ctrl.Data = 0 )then |
Flags(FL_ZERO) <= '1'; |
end if; |
Flags(FL_NEG) <= ALU_Ctrl.Data(7); |
end if; |
Regfile(Index) <= ALU_Ctrl.Data; |
|
when ALU_LDX => -- R0 <= Data : Flags N,Z |
Flags(FL_ZERO) <= '0'; |
if( ALU_Ctrl.Data = 0 )then |
Flags(FL_ZERO) <= '1'; |
end if; |
Flags(FL_NEG) <= ALU_Ctrl.Data(7); |
Regfile(0) <= ALU_Ctrl.Data; |
|
when ALU_RFLG => |
Flags <= ALU_Ctrl.Data; |
|
when others => null; |
end case; |
end if; |
end if; |
end process; |
|
end block; |
|
------------------------------------------------------------------------------- |
-- Program Counter |
------------------------------------------------------------------------------- |
|
Open8_PC : block is |
-- Preinitialization is for simulation only - check actual reset conditions |
signal PC_Q : ADDRESS_TYPE := (others => '0'); |
begin |
|
PC <= PC_Q; |
|
Program_Counter: process( Reset, Clock ) |
variable PC_Offset_SX : ADDRESS_TYPE := x"0000"; |
begin |
if( Reset = Reset_Level )then |
PC_Q <= Program_Start_Addr; |
elsif( rising_edge(Clock) )then |
PC_Offset_SX(15 downto 8):= (others => PC_Ctrl.Offset(7)); |
PC_Offset_SX(7 downto 0) := PC_Ctrl.Offset; |
if( Halt = '0' )then |
case PC_Ctrl.Oper is |
when PC_IDLE => |
null; |
when PC_REV1 => |
PC_Q <= PC_Q - 1; |
when PC_REV2 => |
PC_Q <= PC_Q - 2; |
when PC_INCR => |
PC_Q <= PC_Q + PC_Offset_SX - 2; |
when PC_LOAD => |
PC_Q <= PC_Ctrl.Addr; |
end case; |
end if; |
end if; |
end process; |
|
end block; |
|
------------------------------------------------------------------------------- |
-- Stack Pointer |
------------------------------------------------------------------------------- |
|
Open8_SP : block is |
-- Preinitialization is for simulation only - check actual reset conditions |
signal SP_Q : ADDRESS_TYPE := (others => '0'); |
begin |
|
SP <= SP_Q; |
|
Stack_Pointer: process( Reset, Clock ) |
begin |
if( Reset = Reset_Level )then |
SP_Q <= Stack_Start_Addr; |
elsif( rising_edge(Clock) )then |
if( Halt = '0' )then |
case SP_Ctrl.Oper is |
when SP_IDLE => null; |
when SP_RSET => SP_Q <= SP_Ctrl.Addr; |
when SP_POP => SP_Q <= SP_Q + 1; |
when SP_PUSH => SP_Q <= SP_Q - 1; |
end case; |
end if; |
end if; |
end process; |
|
end block; |
|
------------------------------------------------------------------------------- |
-- Address Source Mux |
------------------------------------------------------------------------------- |
|
Open8_AS : block is |
begin |
|
Address_Select: process( AS_Ctrl, PC, SP, IMM, ISR ) |
begin |
Address <= (others => '0'); |
case AS_Ctrl.Src is |
when ADDR_PC => |
Address <= PC; |
when ADDR_SP => |
Address <= SP; |
when ADDR_IMM => |
Address <= IMM; |
when ADDR_ISR => |
Address <= ISR; |
end case; |
end process; |
|
end block; |
|
------------------------------------------------------------------------------- |
-- (Write) Data Path |
------------------------------------------------------------------------------- |
|
Open8_DP : block is |
begin |
|
Data_Path: process( Reset, Clock ) |
begin |
if( Reset = Reset_Level )then |
Wr_Data <= (others => '0'); |
Wr_Enable <= '0'; |
Rd_Enable <= '1'; |
elsif( rising_edge(Clock) )then |
if( Halt = '0' )then |
Wr_Enable <= '0'; |
Rd_Enable <= '1'; |
case DP_Ctrl.Src is |
when DATA_IDLE => |
null; |
when DATA_REG => |
Wr_Enable <= '1'; |
Rd_Enable <= '0'; |
Wr_Data <= ALU_Regs(conv_integer(DP_Ctrl.Reg)); |
when DATA_FLAG => |
Wr_Enable <= '1'; |
Rd_Enable <= '0'; |
Wr_Data <= ALU_Flags; |
when DATA_PC => |
Wr_Enable <= '1'; |
Rd_Enable <= '0'; |
Wr_Data <= PC(15 downto 8); |
if( DP_Ctrl.Reg = ACCUM )then |
Wr_Data <= PC(7 downto 0); |
end if; |
when others => null; |
end case; |
end if; |
end if; |
end process; |
|
end block; |
|
------------------------------------------------------------------------------- |
-- Interrupt Controller |
------------------------------------------------------------------------------- |
|
Open8_INT : block is |
|
-- Preinitialization is for simulation only - check actual reset conditions |
constant INT_VECTOR_0 : ADDRESS_TYPE := ISR_Start_Addr; |
constant INT_VECTOR_1 : ADDRESS_TYPE := ISR_Start_Addr+2; |
constant INT_VECTOR_2 : ADDRESS_TYPE := ISR_Start_Addr+4; |
constant INT_VECTOR_3 : ADDRESS_TYPE := ISR_Start_Addr+6; |
constant INT_VECTOR_4 : ADDRESS_TYPE := ISR_Start_Addr+8; |
constant INT_VECTOR_5 : ADDRESS_TYPE := ISR_Start_Addr+10; |
constant INT_VECTOR_6 : ADDRESS_TYPE := ISR_Start_Addr+12; |
constant INT_VECTOR_7 : ADDRESS_TYPE := ISR_Start_Addr+14; |
|
signal i_Ints : INTERRUPT_BUNDLE := (others => '0'); |
signal Pending_D : INTERRUPT_BUNDLE := (others => '0'); |
signal Pending : INTERRUPT_BUNDLE := (others => '0'); |
signal Wait_for_FSM : std_logic := '0'; |
signal ISR_D, ISR_Q : ADDRESS_TYPE := (others => '0'); |
|
type INT_HIST is array (0 to 8) of integer range 0 to 7; |
signal History : INT_HIST := (others => 0); |
signal Int_Trig : std_logic := '0'; |
signal Hist_Level : integer range 0 to 7 := 0; |
signal Hist_Ptr : integer range 0 to 8 := 0; |
|
begin |
|
ISR <= ISR_Q; |
|
Int_Mask_proc: process( Int_Mask, Interrupts, INT_Ctrl ) |
variable S_Mask : std_logic_vector(7 downto 0); |
begin |
S_Mask := Int_Mask; |
for i in 0 to 7 loop |
i_Ints(i) <= (Interrupts(i) or INT_Ctrl.Soft_Ints(i)) |
and S_Mask(i); |
end loop; |
end process; |
|
Int_Ctrl_proc: process( i_Ints, Pending, Wait_for_FSM, ISR_Q, INT_Ctrl, |
History, Hist_Ptr ) |
begin |
ISR_D <= ISR_Q; |
Pending_D <= Pending; |
Int_Trig <= '0'; |
Hist_Level <= 0; |
|
-- Record any incoming interrupts to the pending buffer |
if( i_Ints > 0 )then |
Pending_D <= i_Ints; |
end if; |
|
-- Incr_ISR allows the CPU Core to advance the vector address to pop the |
-- lower half of the address. |
if( INT_Ctrl.Incr_ISR = '1' )then |
ISR_D <= ISR_Q + 1; |
end if; |
|
-- Only mess with interrupt signals while the CPU core is not currently |
-- working with the ISR address (ie, not loading a new service vector) |
if( Wait_for_FSM = '0' and Pending > 0 )then |
if( Pending(0) = '1' and (Hist_Ptr = 0 or History(Hist_Ptr) > 0) )then |
ISR_D <= INT_VECTOR_0; |
Pending_D(0) <= '0'; |
Hist_Level <= 0; |
Int_Trig <= '1'; |
elsif( Pending(1) = '1' and (Hist_Ptr = 0 or History(Hist_Ptr) > 1) )then |
ISR_D <= INT_VECTOR_1; |
Pending_D(1) <= '0'; |
Hist_Level <= 1; |
Int_Trig <= '1'; |
elsif( Pending(2) = '1' and (Hist_Ptr = 0 or History(Hist_Ptr) > 2) )then |
ISR_D <= INT_VECTOR_2; |
Pending_D(2) <= '0'; |
Hist_Level <= 2; |
Int_Trig <= '1'; |
elsif( Pending(3) = '1' and (Hist_Ptr = 0 or History(Hist_Ptr) > 3) )then |
ISR_D <= INT_VECTOR_3; |
Pending_D(3) <= '0'; |
Hist_Level <= 3; |
Int_Trig <= '1'; |
elsif( Pending(4) = '1' and (Hist_Ptr = 0 or History(Hist_Ptr) > 4) )then |
ISR_D <= INT_VECTOR_4; |
Pending_D(4) <= '0'; |
Hist_Level <= 4; |
Int_Trig <= '1'; |
elsif( Pending(5) = '1' and (Hist_Ptr = 0 or History(Hist_Ptr) > 5) )then |
ISR_D <= INT_VECTOR_5; |
Pending_D(5) <= '0'; |
Hist_Level <= 5; |
Int_Trig <= '1'; |
elsif( Pending(6) = '1' and (Hist_Ptr = 0 or History(Hist_Ptr) > 6) )then |
ISR_D <= INT_VECTOR_6; |
Pending_D(6) <= '0'; |
Hist_Level <= 6; |
Int_Trig <= '1'; |
elsif( Pending(7) = '1' and (Hist_Ptr = 0 or History(Hist_Ptr) > 7) )then |
ISR_D <= INT_VECTOR_7; |
Pending_D(7) <= '0'; |
Hist_Level <= 7; |
Int_Trig <= '1'; |
end if; |
end if; |
end process; |
|
S_Regs: process( Reset, Clock ) |
begin |
if( Reset = Reset_Level )then |
Int_Req <= '0'; |
Pending <= x"00"; |
Wait_for_FSM <= '0'; |
Int_Mask <= Default_Interrupt_Mask(7 downto 1) & '1'; |
ISR_Q <= INT_VECTOR_0; |
for i in 0 to 8 loop |
History(i) <= 0; |
end loop; |
Hist_Ptr <= 0; |
elsif( rising_edge(Clock) )then |
if( Halt = '0' )then |
Int_Req <= Wait_for_FSM and (not Int_Ack); |
Pending <= Pending_D; |
-- Reset the Wait_for_FSM flag on Int_Ack |
if( Int_Ack = '1' )then |
Wait_for_FSM <= '0'; |
-- Set the Wait_for_FSM flag on Int_Trig |
elsif( Int_Trig = '1' )then |
Wait_for_FSM <= '1'; |
end if; |
if( INT_Ctrl.Mask_Set = '1' )then |
Int_Mask <= INT_Ctrl.Mask_Data(7 downto 1) & '1'; |
end if; |
ISR_Q <= ISR_D; |
if( Int_Trig = '1' )then |
History(Hist_Ptr+1) <= Hist_Level; |
Hist_Ptr <= Hist_Ptr + 1; |
elsif( Int_RTI = '1' and Hist_Ptr > 0 )then |
Hist_Ptr <= Hist_Ptr - 1; |
end if; |
end if; |
end if; |
end process; |
|
end block; |
|
------------------------------------------------------------------------------- |
-- State Logic / Instruction Decoding & Execution |
------------------------------------------------------------------------------- |
|
Open8_FSM : block is |
|
-- These are all the primary instructions/op-codes (upper 5-bits) |
constant OP_INC : OPCODE_TYPE := "00000"; |
constant OP_ADC : OPCODE_TYPE := "00001"; |
181,157 → 813,34
-- Debugging |
BRK_C1 ); |
|
type CACHE_MODES is (CACHE_IDLE, CACHE_INSTR, CACHE_OPER1, CACHE_OPER2, |
CACHE_PREFETCH ); |
|
type PC_MODES is ( PC_IDLE, PC_REV1, PC_REV2, PC_INCR, PC_LOAD ); |
|
type PC_CTRL_TYPE is record |
Oper : PC_MODES; |
Offset : DATA_TYPE; |
Addr : ADDRESS_TYPE; |
end record; |
|
type SP_MODES is ( SP_IDLE, SP_RSET, SP_POP, SP_PUSH ); |
|
type SP_CTRL_TYPE is record |
Oper : SP_MODES; |
Addr : ADDRESS_TYPE; |
end record; |
|
type DP_MODES is ( DATA_IDLE, DATA_REG, DATA_FLAG, DATA_PC ); |
|
type DATA_CTRL_TYPE is record |
Src : DP_MODES; |
Reg : SUBOP_TYPE; |
end record; |
|
-- Preinitialization is for simulation only - check actual reset conditions |
constant INT_VECTOR_0 : ADDRESS_TYPE := ISR_Start_Addr; |
constant INT_VECTOR_1 : ADDRESS_TYPE := ISR_Start_Addr+2; |
constant INT_VECTOR_2 : ADDRESS_TYPE := ISR_Start_Addr+4; |
constant INT_VECTOR_3 : ADDRESS_TYPE := ISR_Start_Addr+6; |
constant INT_VECTOR_4 : ADDRESS_TYPE := ISR_Start_Addr+8; |
constant INT_VECTOR_5 : ADDRESS_TYPE := ISR_Start_Addr+10; |
constant INT_VECTOR_6 : ADDRESS_TYPE := ISR_Start_Addr+12; |
constant INT_VECTOR_7 : ADDRESS_TYPE := ISR_Start_Addr+14; |
|
type INT_CTRL_TYPE is record |
Mask_Set : std_logic; |
Soft_Ints : INTERRUPT_BUNDLE; |
Incr_ISR : std_logic; |
end record; |
|
type INT_HIST is array (0 to 8) of integer range 0 to 7; |
|
-- Most of the ALU instructions are the same as their Opcode equivalents with |
-- three exceptions (for IDLE, UPP2, and MUL2) |
constant ALU_INC : OPCODE_TYPE := "00000"; -- x"00" |
constant ALU_ADC : OPCODE_TYPE := "00001"; -- x"01" |
constant ALU_TX0 : OPCODE_TYPE := "00010"; -- x"02" |
constant ALU_OR : OPCODE_TYPE := "00011"; -- x"03" |
constant ALU_AND : OPCODE_TYPE := "00100"; -- x"04" |
constant ALU_XOR : OPCODE_TYPE := "00101"; -- x"05" |
constant ALU_ROL : OPCODE_TYPE := "00110"; -- x"06" |
constant ALU_ROR : OPCODE_TYPE := "00111"; -- x"07" |
constant ALU_DEC : OPCODE_TYPE := "01000"; -- x"08" |
constant ALU_SBC : OPCODE_TYPE := "01001"; -- x"09" |
constant ALU_ADD : OPCODE_TYPE := "01010"; -- x"0A" |
constant ALU_STP : OPCODE_TYPE := "01011"; -- x"0B" |
constant ALU_BTT : OPCODE_TYPE := "01100"; -- x"0C" |
constant ALU_CLP : OPCODE_TYPE := "01101"; -- x"0D" |
constant ALU_T0X : OPCODE_TYPE := "01110"; -- x"0E" |
constant ALU_CMP : OPCODE_TYPE := "01111"; -- x"0F" |
constant ALU_POP : OPCODE_TYPE := "10001"; -- x"11" |
constant ALU_MUL : OPCODE_TYPE := "10110"; -- x"16" |
constant ALU_UPP : OPCODE_TYPE := "11000"; -- x"18" |
constant ALU_LDI : OPCODE_TYPE := "11100"; -- x"1C" |
constant ALU_LDX : OPCODE_TYPE := "11110"; -- x"1E" |
|
constant ALU_IDLE : OPCODE_TYPE := "10000"; -- x"10" |
constant ALU_UPP2 : OPCODE_TYPE := "10010"; -- x"12" |
constant ALU_RFLG : OPCODE_TYPE := "10011"; -- x"13" |
|
constant FL_ZERO : integer := 0; |
constant FL_CARRY : integer := 1; |
constant FL_NEG : integer := 2; |
constant FL_INT_EN : integer := 3; |
constant FL_GP1 : integer := 4; |
constant FL_GP2 : integer := 5; |
constant FL_GP3 : integer := 6; |
constant FL_GP4 : integer := 7; |
|
type ALU_CTRL_TYPE is record |
Oper : OPCODE_TYPE; |
Reg : SUBOP_TYPE; |
Data : DATA_TYPE; |
end record; |
|
constant ACCUM : SUBOP_TYPE := "000"; |
constant INT_FLAG : SUBOP_TYPE := "011"; |
|
type REGFILE_TYPE is array (0 to 7) of DATA_TYPE; |
|
subtype FLAG_TYPE is DATA_TYPE; |
|
signal Halt : std_logic; |
|
signal CPU_Next_State : CPU_STATES := PIPE_FILL_0; |
signal CPU_State : CPU_STATES := PIPE_FILL_0; |
|
type CACHE_MODES is (CACHE_IDLE, CACHE_INSTR, CACHE_OPER1, CACHE_OPER2, |
CACHE_PREFETCH ); |
signal Cache_Ctrl : CACHE_MODES := CACHE_IDLE; |
|
signal Opcode : OPCODE_TYPE := (others => '0'); |
signal SubOp, SubOp_p1 : SUBOP_TYPE := (others => '0'); |
-- synthesis translate_off |
signal Instruction : DATA_TYPE := (others => '0'); |
-- synthesis translate_on |
signal Prefetch : DATA_TYPE := (others => '0'); |
signal Operand1, Operand2 : DATA_TYPE := (others => '0'); |
|
signal Prefetch : DATA_TYPE := x"00"; |
signal Operand1, Operand2 : DATA_TYPE := x"00"; |
|
signal Instr_Prefetch : std_logic := '0'; |
|
signal PC_Ctrl : PC_CTRL_TYPE; |
signal Program_Ctr : ADDRESS_TYPE := x"0000"; |
|
signal SP_Ctrl : SP_CTRL_TYPE; |
signal Stack_Ptr : ADDRESS_TYPE := x"0000"; |
|
signal DP_Ctrl : DATA_CTRL_TYPE; |
|
signal INT_Ctrl : INT_CTRL_TYPE; |
signal Ack_D, Ack_Q, Ack_Q1: std_logic := '0'; |
signal Int_RTI_D, Int_RTI : std_logic := '0'; |
signal Int_Req, Int_Ack : std_logic := '0'; |
signal Int_Mask : DATA_TYPE := x"00"; |
signal ISR_Addr : ADDRESS_TYPE := x"0000"; |
signal i_Ints : INTERRUPT_BUNDLE := x"00"; |
signal Pending : INTERRUPT_BUNDLE := x"00"; |
signal Wait_for_FSM : std_logic := '0'; |
signal History : INT_HIST := (others => 0); |
signal Hst_Ptr : integer range 0 to 8 := 0; |
signal Int_RTI_D : std_logic := '0'; |
|
signal ALU_Ctrl : ALU_CTRL_TYPE; |
signal Regfile : REGFILE_TYPE; |
signal Flags : FLAG_TYPE; |
signal Mult : ADDRESS_TYPE := x"0000"; |
|
begin |
|
Halt_Disabled_fn: if( not Enable_CPU_Halt )generate |
Halt <= '0'; |
end generate; |
-- synthesis translate_off |
Instruction <= Opcode & SubOp; |
-- synthesis translate_on |
|
Halt_Enabled_fn: if( Enable_CPU_Halt )generate |
Halt <= CPU_Halt; |
end generate; |
|
------------------------------------------------------------------------------- |
-- State Logic / Instruction Decoding & Execution |
-- Combinatorial portion of CPU finite state machine |
------------------------------------------------------------------------------- |
|
State_Logic: process(CPU_State, Regfile, Flags, Int_Mask, Opcode, |
SubOp , SubOp_p1, Operand1, Operand2, Int_Req, |
Program_Ctr, Stack_Ptr, ISR_Addr ) |
State_Logic: process(CPU_State, ALU_Regs, ALU_Flags, Int_Mask, Opcode, |
SubOp , SubOp_p1, Operand1, Operand2, Int_Req ) |
variable Reg, Reg_1 : integer range 0 to 7 := 0; |
variable Offset_SX : ADDRESS_TYPE; |
begin |
343,12 → 852,14
ALU_Ctrl.Data <= x"00"; |
-- |
PC_Ctrl.Oper <= PC_IDLE; |
|
PC_Ctrl.Offset <= x"03"; |
PC_Ctrl.Addr <= x"0000"; |
-- |
SP_Ctrl.Oper <= SP_IDLE; |
-- |
Address <= Program_Ctr; |
AS_Ctrl.Src <= ADDR_PC; |
IMM <= x"0000"; |
-- |
DP_Ctrl.Src <= DATA_IDLE; |
DP_Ctrl.Reg <= ACCUM; |
497,15 → 1008,16
when OP_LDX => |
CPU_Next_State <= LDX_C1; |
PC_Ctrl.Oper <= PC_REV2; |
AS_Ctrl.Src <= ADDR_IMM; |
-- If auto-increment is disabled, use the specified register pair, |
-- otherwise, for an odd:even pair, and issue the first half of |
-- a UPP instruction to the ALU |
if( not Enable_Auto_Increment )then |
Address <= Regfile(Reg_1) & Regfile(Reg); |
IMM <= ALU_Regs(Reg_1) & ALU_Regs(Reg); |
else |
Reg := conv_integer(SubOp(2 downto 1) & '0'); |
Reg_1 := conv_integer(SubOp(2 downto 1) & '1'); |
Address <= Regfile(Reg_1) & Regfile(Reg); |
IMM <= ALU_Regs(Reg_1) & ALU_Regs(Reg); |
if( SubOp(0) = '1' )then |
ALU_Ctrl.Oper<= ALU_UPP; |
ALU_Ctrl.Reg <= SubOp(2 downto 1) & '0'; |
545,7 → 1057,7
CPU_Next_State <= INSTR_DECODE; |
Cache_Ctrl <= CACHE_INSTR; |
PC_Ctrl.Oper <= PC_INCR; |
if( Flags(Reg) = Opcode(0) )then |
if( ALU_Flags(Reg) = Opcode(0) )then |
CPU_Next_State <= PIPE_FILL_0; |
Cache_Ctrl <= CACHE_IDLE; |
PC_Ctrl.Offset <= Operand1; |
555,7 → 1067,7
CPU_Next_State <= INSTR_DECODE; |
Cache_Ctrl <= CACHE_INSTR; |
PC_Ctrl.Oper <= PC_INCR; |
if( Flags(FL_ZERO) = '0' )then |
if( ALU_Flags(FL_ZERO) = '0' )then |
CPU_Next_State <= PIPE_FILL_0; |
Cache_Ctrl <= CACHE_IDLE; |
PC_Ctrl.Offset <= Operand1; |
580,7 → 1092,8
|
when LDA_C2 => |
CPU_Next_State <= LDA_C3; |
Address <= Operand2 & Operand1; |
AS_Ctrl.Src <= ADDR_IMM; |
IMM <= Operand2 & Operand1; |
|
when LDA_C3 => |
CPU_Next_State <= LDA_C4; |
601,17 → 1114,18
|
when LDO_C1 => |
CPU_Next_State <= LDX_C1; |
AS_Ctrl.Src <= ADDR_IMM; |
PC_Ctrl.Oper <= PC_INCR; |
if( Enable_Auto_Increment )then |
Reg := conv_integer(SubOp(2 downto 1) & '0'); |
Reg_1 := conv_integer(SubOp(2 downto 1) & '1'); |
Address <= (Regfile(Reg_1) & Regfile(Reg)) + Offset_SX; |
IMM <= (ALU_Regs(Reg_1) & ALU_Regs(Reg)) + Offset_SX; |
if( SubOp(0) = '1' )then |
ALU_Ctrl.Oper<= ALU_UPP; |
ALU_Ctrl.Reg <= SubOp(2 downto 1) & '0'; |
end if; |
else |
Address <= (Regfile(Reg_1) & Regfile(Reg)) + Offset_SX; |
IMM <= (ALU_Regs(Reg_1) & ALU_Regs(Reg)) + Offset_SX; |
end if; |
|
when LDX_C1 => |
642,21 → 1156,23
|
when STA_C2 => |
CPU_Next_State <= STA_C3; |
Address <= Operand2 & Operand1; |
AS_Ctrl.Src <= ADDR_IMM; |
IMM <= Operand2 & Operand1; |
PC_Ctrl.Oper <= PC_INCR; |
|
when STA_C3 => |
CPU_Next_State <= PIPE_FILL_2; |
Cache_Ctrl <= CACHE_PREFETCH; |
PC_Ctrl.Oper <= PC_INCR; |
PC_Ctrl.Oper <= PC_INCR; |
|
when STO_C1 => |
Cache_Ctrl <= CACHE_PREFETCH; |
PC_Ctrl.Oper <= PC_INCR; |
AS_Ctrl.Src <= ADDR_IMM; |
-- If auto-increment is disabled, just load the registers normally |
if( not Enable_Auto_Increment )then |
CPU_Next_State <= PIPE_FILL_1; |
Address <= (Regfile(Reg_1) & Regfile(Reg)) + Offset_SX; |
IMM <= (ALU_Regs(Reg_1) & ALU_Regs(Reg)) + Offset_SX; |
-- Otherwise, enforce the even register rule, and check the LSB to see |
-- if we should perform the auto-increment on the register pair |
else |
663,7 → 1179,7
CPU_Next_State <= PIPE_FILL_0; |
Reg := conv_integer(SubOp(2 downto 1) & '0'); |
Reg_1 := conv_integer(SubOp(2 downto 1) & '1'); |
Address <= (Regfile(Reg_1) & Regfile(Reg)) + Offset_SX; |
IMM <= (ALU_Regs(Reg_1) & ALU_Regs(Reg)) + Offset_SX; |
if( SubOp(0) = '1' )then |
CPU_Next_State <= STO_C2; |
ALU_Ctrl.Oper <= ALU_UPP; |
679,10 → 1195,11
|
when STX_C1 => |
PC_Ctrl.Oper <= PC_INCR; |
AS_Ctrl.Src <= ADDR_IMM; |
-- If auto-increment is disabled, just load the registers normally |
if( not Enable_Auto_Increment )then |
CPU_Next_State <= PIPE_FILL_1; |
Address <= (Regfile(Reg_1) & Regfile(Reg)); |
IMM <= (ALU_Regs(Reg_1) & ALU_Regs(Reg)); |
-- Otherwise, enforce the even register rule, and check the LSB to see |
-- if we should perform the auto-increment on the register pair |
else |
689,7 → 1206,7
CPU_Next_State <= PIPE_FILL_1; |
Reg := conv_integer(SubOp(2 downto 1) & '0'); |
Reg_1 := conv_integer(SubOp(2 downto 1) & '1'); |
Address <= (Regfile(Reg_1) & Regfile(Reg)); |
IMM <= (ALU_Regs(Reg_1) & ALU_Regs(Reg)); |
if( SubOp(0) = '1' )then |
CPU_Next_State <= STX_C2; |
ALU_Ctrl.Oper <= ALU_UPP; |
725,12 → 1242,12
------------------------------------------------------------------------------- |
when PSH_C1 => |
CPU_Next_State <= PIPE_FILL_1; |
Address <= Stack_Ptr; |
AS_Ctrl.Src <= ADDR_SP; |
SP_Ctrl.Oper <= SP_PUSH; |
|
when POP_C1 => |
CPU_Next_State <= POP_C2; |
Address <= Stack_Ptr; |
AS_Ctrl.Src <= ADDR_SP; |
|
when POP_C2 => |
CPU_Next_State <= POP_C3; |
752,23 → 1269,23
------------------------------------------------------------------------------- |
-- Subroutines & Interrupts (RTS, JSR) |
------------------------------------------------------------------------------- |
when WAIT_FOR_INT => -- For soft interrupts only, halt the Program_Ctr |
when WAIT_FOR_INT => -- For soft interrupts only, halt the PC |
CPU_Next_State <= WAIT_FOR_INT; |
|
when ISR_C1 => |
CPU_Next_State <= ISR_C2; |
Address <= ISR_Addr; |
AS_Ctrl.Src <= ADDR_ISR; |
INT_Ctrl.Incr_ISR <= '1'; |
|
when ISR_C2 => |
CPU_Next_State <= ISR_C3; |
Address <= ISR_Addr; |
AS_Ctrl.Src <= ADDR_ISR; |
DP_Ctrl.Src <= DATA_FLAG; |
|
when ISR_C3 => |
CPU_Next_State <= JSR_C1; |
Cache_Ctrl <= CACHE_OPER1; |
Address <= Stack_Ptr; |
AS_Ctrl.Src <= ADDR_SP; |
SP_Ctrl.Oper <= SP_PUSH; |
DP_Ctrl.Src <= DATA_PC; |
DP_Ctrl.Reg <= ACCUM+1; |
779,7 → 1296,7
when JSR_C1 => |
CPU_Next_State <= JSR_C2; |
Cache_Ctrl <= CACHE_OPER2; |
Address <= Stack_Ptr; |
AS_Ctrl.Src <= ADDR_SP; |
SP_Ctrl.Oper <= SP_PUSH; |
DP_Ctrl.Src <= DATA_PC; |
DP_Ctrl.Reg <= ACCUM; |
786,7 → 1303,7
|
when JSR_C2 => |
CPU_Next_State <= PIPE_FILL_0; |
Address <= Stack_Ptr; |
AS_Ctrl.Src <= ADDR_SP; |
SP_Ctrl.Oper <= SP_PUSH; |
PC_Ctrl.Oper <= PC_LOAD; |
PC_Ctrl.Addr <= Operand2 & Operand1; |
793,12 → 1310,12
|
when RTS_C1 => |
CPU_Next_State <= RTS_C2; |
Address <= Stack_Ptr; |
AS_Ctrl.Src <= ADDR_SP; |
SP_Ctrl.Oper <= SP_POP; |
|
when RTS_C2 => |
CPU_Next_State <= RTS_C3; |
Address <= Stack_Ptr; |
AS_Ctrl.Src <= ADDR_SP; |
-- if this is an RTI, then we need to POP the flags |
if( SubOp = SOP_RTI )then |
SP_Ctrl.Oper <= SP_POP; |
809,7 → 1326,7
Cache_Ctrl <= CACHE_OPER1; |
-- It doesn't really matter what is on the address bus for RTS, while |
-- it does for RTI, so we make this the default |
Address <= Stack_Ptr; |
AS_Ctrl.Src <= ADDR_SP; |
|
when RTS_C4 => |
CPU_Next_State <= RTS_C5; |
829,6 → 1346,7
PC_Ctrl.Oper <= PC_INCR; |
ALU_Ctrl.Oper <= ALU_RFLG; |
ALU_Ctrl.Data <= Operand1; |
PC_Ctrl.Oper <= PC_INCR; |
Int_RTI_D <= '1'; |
|
------------------------------------------------------------------------------- |
837,8 → 1355,7
when BRK_C1 => |
CPU_Next_State <= PIPE_FILL_0; |
|
when others => |
null; |
when others => null; |
end case; |
|
-- Interrupt service routines can only begin during the decode and wait |
862,26 → 1379,8
|
end process; |
|
-- We need to infer a hardware multipler, so we create a special clocked |
-- process with no reset or clock enable |
Multiplier_proc: process( Clock ) |
S_Regs: process( Reset, Clock ) |
begin |
if( rising_edge(Clock) )then |
Mult <= Regfile(0) * |
Regfile(conv_integer(ALU_Ctrl.Reg)); |
end if; |
end process; |
|
------------------------------------------------------------------------------- |
-- Registered portion of CPU finite state machine |
------------------------------------------------------------------------------- |
CPU_Regs: process( Reset, Clock ) |
variable Offset_SX : ADDRESS_TYPE; |
variable i_Ints : INTERRUPT_BUNDLE := (others => '0'); |
variable Sum : std_logic_vector(8 downto 0) := "000000000"; |
variable Index : integer range 0 to 7 := 0; |
variable Temp : std_logic_vector(8 downto 0); |
begin |
if( Reset = Reset_Level )then |
CPU_State <= PIPE_FILL_0; |
Opcode <= OP_INC; |
892,42 → 1391,13
Instr_Prefetch <= '0'; |
Prefetch <= x"00"; |
|
Wr_Data <= (others => '0'); |
Wr_Enable <= '0'; |
Rd_Enable <= '1'; |
|
Program_Ctr <= Program_Start_Addr; |
Stack_Ptr <= Stack_Start_Addr; |
|
Ack_Q <= '0'; |
Ack_Q1 <= '0'; |
Int_Ack <= '0'; |
Int_RTI <= '0'; |
|
Int_Req <= '0'; |
Pending <= x"00"; |
Wait_for_FSM <= '0'; |
Int_Mask <= Default_Interrupt_Mask(7 downto 1) & '1'; |
ISR_Addr <= INT_VECTOR_0; |
for i in 0 to 8 loop |
History(i) <= 0; |
end loop; |
Hst_Ptr <= 0; |
|
for i in 0 to 7 loop |
Regfile(i) <= (others => '0'); |
end loop; |
Flags <= x"00"; |
|
elsif( rising_edge(Clock) )then |
Wr_Enable <= '0'; |
Rd_Enable <= '0'; |
|
if( Halt = '0' )then |
Rd_Enable <= '1'; |
------------------------------------------------------------------------------- |
-- Instruction/Operand caching for pipelined memory access |
------------------------------------------------------------------------------- |
CPU_State <= CPU_Next_State; |
case Cache_Ctrl is |
when CACHE_INSTR => |
940,395 → 1410,47
SubOp_p1 <= Prefetch(2 downto 0) + 1; |
Instr_Prefetch <= '0'; |
end if; |
|
when CACHE_OPER1 => |
Operand1 <= Rd_Data; |
|
when CACHE_OPER2 => |
Operand2 <= Rd_Data; |
|
when CACHE_PREFETCH => |
Prefetch <= Rd_Data; |
Instr_Prefetch <= '1'; |
|
when CACHE_IDLE => |
null; |
end case; |
|
------------------------------------------------------------------------------- |
-- Program Counter |
------------------------------------------------------------------------------- |
Offset_SX(15 downto 8) := (others => PC_Ctrl.Offset(7)); |
Offset_SX(7 downto 0) := PC_Ctrl.Offset; |
-- Interrupt signalling registers |
Ack_Q <= Ack_D; |
Ack_Q1 <= Ack_Q; |
Int_Ack <= Ack_Q1; |
Int_RTI <= Int_RTI_D; |
end if; |
end if; |
end process; |
|
case PC_Ctrl.Oper is |
when PC_IDLE => |
null; |
|
when PC_REV1 => |
Program_Ctr <= Program_Ctr - 1; |
|
when PC_REV2 => |
Program_Ctr <= Program_Ctr - 2; |
|
when PC_INCR => |
Program_Ctr <= Program_Ctr + Offset_SX - 2; |
|
when PC_LOAD => |
Program_Ctr <= PC_Ctrl.Addr; |
|
when others => |
null; |
end case; |
|
------------------------------------------------------------------------------- |
-- (Write) Data Path |
-- Fixed in-line statements for the interrupt mask, and stack pointer address |
------------------------------------------------------------------------------- |
case DP_Ctrl.Src is |
when DATA_IDLE => |
null; |
|
when DATA_REG => |
Wr_Enable <= '1'; |
Rd_Enable <= '0'; |
Wr_Data <= Regfile(conv_integer(DP_Ctrl.Reg)); |
-- The interrupt control mask is always sourced out of R0 |
INT_Ctrl.Mask_Data <= ALU_Regs(conv_integer(ACCUM)); |
|
when DATA_FLAG => |
Wr_Enable <= '1'; |
Rd_Enable <= '0'; |
Wr_Data <= Flags; |
|
when DATA_PC => |
Wr_Enable <= '1'; |
Rd_Enable <= '0'; |
Wr_Data <= Program_Ctr(15 downto 8); |
if( DP_Ctrl.Reg = ACCUM )then |
Wr_Data <= Program_Ctr(7 downto 0); |
end if; |
|
when others => |
null; |
end case; |
|
------------------------------------------------------------------------------- |
-- Stack Pointer |
------------------------------------------------------------------------------- |
case SP_Ctrl.Oper is |
when SP_IDLE => |
null; |
|
when SP_RSET => |
-- The original RSP instruction simply reset the stack pointer to the preset |
-- address set at compile time. However, with little extra effort, we can |
-- modify the instruction to allow the stack pointer to be moved anywhere in |
-- the memory map. Since RSP can't have an sub-opcode, R1:R0 was chosen as |
-- a fixed source |
Stack_Ptr <= Stack_Start_Addr; |
if( Allow_Stack_Address_Move )then |
Stack_Ptr <= Regfile(1) & Regfile(0); |
end if; |
|
when SP_POP => |
Stack_Ptr <= Stack_Ptr + 1; |
Prog_Stack_Addr_Move_fn: if( Allow_Stack_Address_Move )generate |
SP_Ctrl.Addr <= ALU_Regs(1) & ALU_Regs(0); |
end generate; |
|
when SP_PUSH => |
Stack_Ptr <= Stack_Ptr - 1; |
Normal_Stack_Reset_fn: if( not Allow_Stack_Address_Move )generate |
SP_Ctrl.Addr <= Stack_Start_Addr; |
end generate; |
|
when others => |
null; |
end block; |
|
end case; |
|
------------------------------------------------------------------------------- |
-- Interrupt Controller |
------------------------------------------------------------------------------- |
-- The interrupt control mask is always sourced out of R0 |
if( INT_Ctrl.Mask_Set = '1' )then |
Int_Mask <= Regfile(conv_integer(ACCUM))(7 downto 1) & '1'; |
end if; |
|
-- Combine external and internal interrupts, and mask the OR or the two |
-- with the mask. Record any incoming interrupts to the pending buffer |
i_Ints := (Interrupts or INT_Ctrl.Soft_Ints) and |
Int_Mask; |
if( i_Ints > 0 )then |
Pending <= i_Ints; |
end if; |
|
-- Only mess with interrupt signals while the CPU core is not currently |
-- working with, or loading, an ISR address |
if( Wait_for_FSM = '0' and Pending > 0 )then |
if( Pending(0) = '1' and (Hst_Ptr = 0 or History(Hst_Ptr) > 0))then |
ISR_Addr <= INT_VECTOR_0; |
Pending(0) <= '0'; |
History(Hst_Ptr+1) <= 0; |
Hst_Ptr <= Hst_Ptr + 1; |
Wait_for_FSM <= '1'; |
elsif(Pending(1) = '1' and (Hst_Ptr = 0 or History(Hst_Ptr) > 1))then |
ISR_Addr <= INT_VECTOR_1; |
Pending(1) <= '0'; |
History(Hst_Ptr+1) <= 1; |
Hst_Ptr <= Hst_Ptr + 1; |
Wait_for_FSM <= '1'; |
elsif(Pending(2) = '1' and (Hst_Ptr = 0 or History(Hst_Ptr) > 2))then |
ISR_Addr <= INT_VECTOR_2; |
Pending(2) <= '0'; |
History(Hst_Ptr+1) <= 1; |
Hst_Ptr <= Hst_Ptr + 1; |
Wait_for_FSM <= '1'; |
elsif(Pending(3) = '1' and (Hst_Ptr = 0 or History(Hst_Ptr) > 3))then |
ISR_Addr <= INT_VECTOR_3; |
Pending(3) <= '0'; |
History(Hst_Ptr+1) <= 3; |
Hst_Ptr <= Hst_Ptr + 1; |
Wait_for_FSM <= '1'; |
elsif(Pending(4) = '1' and (Hst_Ptr = 0 or History(Hst_Ptr) > 4))then |
ISR_Addr <= INT_VECTOR_4; |
Pending(4) <= '0'; |
History(Hst_Ptr+1) <= 4; |
Hst_Ptr <= Hst_Ptr + 1; |
Wait_for_FSM <= '1'; |
elsif(Pending(5) = '1' and (Hst_Ptr = 0 or History(Hst_Ptr) > 5))then |
ISR_Addr <= INT_VECTOR_5; |
Pending(5) <= '0'; |
History(Hst_Ptr+1) <= 5; |
Hst_Ptr <= Hst_Ptr + 1; |
Wait_for_FSM <= '1'; |
elsif(Pending(6) = '1' and (Hst_Ptr = 0 or History(Hst_Ptr) > 6))then |
ISR_Addr <= INT_VECTOR_6; |
Pending(6) <= '0'; |
History(Hst_Ptr+1) <= 6; |
Hst_Ptr <= Hst_Ptr + 1; |
Wait_for_FSM <= '1'; |
elsif(Pending(7) = '1' and (Hst_Ptr = 0 or History(Hst_Ptr) > 7))then |
ISR_Addr <= INT_VECTOR_7; |
Pending(7) <= '0'; |
History(Hst_Ptr+1) <= 7; |
Hst_Ptr <= Hst_Ptr + 1; |
Wait_for_FSM <= '1'; |
end if; |
end if; |
|
-- Reset the Wait_for_FSM flag on Int_Ack |
Ack_Q <= Ack_D; |
Ack_Q1 <= Ack_Q; |
Int_Ack <= Ack_Q1; |
if( Int_Ack = '1' )then |
Wait_for_FSM <= '0'; |
end if; |
|
Int_Req <= Wait_for_FSM and (not Int_Ack); |
|
Int_RTI <= Int_RTI_D; |
if( Int_RTI = '1' and Hst_Ptr > 0 )then |
Hst_Ptr <= Hst_Ptr - 1; |
end if; |
|
-- Incr_ISR allows the CPU Core to advance the vector address to pop the |
-- lower half of the address. |
if( INT_Ctrl.Incr_ISR = '1' )then |
ISR_Addr <= ISR_Addr + 1; |
end if; |
|
------------------------------------------------------------------------------- |
-- ALU (Arithmetic / Logic Unit) |
------------------------------------------------------------------------------- |
Temp := (others => '0'); |
Index := conv_integer(ALU_Ctrl.Reg); |
|
case ALU_Ctrl.Oper is |
when ALU_INC | ALU_UPP => -- Rn = Rn + 1 : Flags N,C,Z |
Sum := ("0" & x"01") + |
("0" & Regfile(Index)); |
Flags(FL_CARRY) <= Sum(8); |
Regfile(Index) <= Sum(7 downto 0); |
-- ALU_INC and ALU_UPP are essentially the same, except that ALU_UPP |
-- doesn't set the N or Z flags. Note that the MSB can be used to |
-- distinguish between the two ALU modes. |
if( ALU_Ctrl.Oper(4) = '0' )then |
Flags(FL_ZERO) <= '0'; |
if( Sum(7 downto 0) = 0 )then |
Flags(FL_ZERO)<= '1'; |
end if; |
Flags(FL_NEG) <= Sum(7); |
end if; |
|
when ALU_UPP2 => -- Rn = Rn + C |
Sum := ("0" & x"00") + |
("0" & Regfile(Index)) + |
Flags(FL_CARRY); |
Flags(FL_CARRY) <= Sum(8); |
Regfile(Index) <= Sum(7 downto 0); |
|
when ALU_ADC => -- R0 = R0 + Rn + C : Flags N,C,Z |
Sum := ("0" & Regfile(0)) + |
("0" & Regfile(Index)) + |
Flags(FL_CARRY); |
Flags(FL_ZERO) <= '0'; |
if( Sum(7 downto 0) = 0 )then |
Flags(FL_ZERO) <= '1'; |
end if; |
Flags(FL_CARRY) <= Sum(8); |
Flags(FL_NEG) <= Sum(7); |
Regfile(0) <= Sum(7 downto 0); |
|
when ALU_TX0 => -- R0 = Rn : Flags N,Z |
Temp := "0" & Regfile(Index); |
Flags(FL_ZERO) <= '0'; |
if( Temp(7 downto 0) = 0 )then |
Flags(FL_ZERO) <= '1'; |
end if; |
Flags(FL_NEG) <= Temp(7); |
Regfile(0) <= Temp(7 downto 0); |
|
when ALU_OR => -- R0 = R0 | Rn : Flags N,Z |
Temp(7 downto 0) := Regfile(0) or Regfile(Index); |
Flags(FL_ZERO) <= '0'; |
if( Temp(7 downto 0) = 0 )then |
Flags(FL_ZERO) <= '1'; |
end if; |
Flags(FL_NEG) <= Temp(7); |
Regfile(0) <= Temp(7 downto 0); |
|
when ALU_AND => -- R0 = R0 & Rn : Flags N,Z |
Temp(7 downto 0) := Regfile(0) and Regfile(Index); |
Flags(FL_ZERO) <= '0'; |
if( Temp(7 downto 0) = 0 )then |
Flags(FL_ZERO) <= '1'; |
end if; |
Flags(FL_NEG) <= Temp(7); |
Regfile(0) <= Temp(7 downto 0); |
|
when ALU_XOR => -- R0 = R0 ^ Rn : Flags N,Z |
Temp(7 downto 0) := Regfile(0) xor Regfile(Index); |
Flags(FL_ZERO) <= '0'; |
if( Temp(7 downto 0) = 0 )then |
Flags(FL_ZERO) <= '1'; |
end if; |
Flags(FL_NEG) <= Temp(7); |
Regfile(0) <= Temp(7 downto 0); |
|
when ALU_ROL => -- Rn = Rn<<1,C : Flags N,C,Z |
Temp := Regfile(Index) & Flags(FL_CARRY); |
Flags(FL_ZERO) <= '0'; |
if( Temp(7 downto 0) = 0 )then |
Flags(FL_ZERO) <= '1'; |
end if; |
Flags(FL_CARRY) <= Temp(8); |
Flags(FL_NEG) <= Temp(7); |
Regfile(Index) <= Temp(7 downto 0); |
|
when ALU_ROR => -- Rn = C,Rn>>1 : Flags N,C,Z |
Temp := Regfile(Index)(0) & Flags(FL_CARRY) & |
Regfile(Index)(7 downto 1); |
Flags(FL_ZERO) <= '0'; |
if( Temp(7 downto 0) = 0 )then |
Flags(FL_ZERO) <= '1'; |
end if; |
Flags(FL_CARRY) <= Temp(8); |
Flags(FL_NEG) <= Temp(7); |
Regfile(Index) <= Temp(7 downto 0); |
|
when ALU_DEC => -- Rn = Rn - 1 : Flags N,C,Z |
Sum := ("0" & Regfile(Index)) + |
("0" & x"FF"); |
Flags(FL_ZERO) <= '0'; |
if( Sum(7 downto 0) = 0 )then |
Flags(FL_ZERO) <= '1'; |
end if; |
Flags(FL_CARRY) <= Sum(8); |
Flags(FL_NEG) <= Sum(7); |
Regfile(Index) <= Sum(7 downto 0); |
|
when ALU_SBC => -- Rn = R0 - Rn - C : Flags N,C,Z |
Sum := ("0" & Regfile(0)) + |
("0" & (not Regfile(Index))) + |
Flags(FL_CARRY); |
Flags(FL_ZERO) <= '0'; |
if( Sum(7 downto 0) = 0 )then |
Flags(FL_ZERO) <= '1'; |
end if; |
Flags(FL_CARRY) <= Sum(8); |
Flags(FL_NEG) <= Sum(7); |
Regfile(0) <= Sum(7 downto 0); |
|
when ALU_ADD => -- R0 = R0 + Rn : Flags N,C,Z |
Sum := ("0" & Regfile(0)) + |
("0" & Regfile(Index)); |
Flags(FL_CARRY) <= Sum(8); |
Regfile(0) <= Sum(7 downto 0); |
Flags(FL_ZERO) <= '0'; |
if( Sum(7 downto 0) = 0 )then |
Flags(FL_ZERO) <= '1'; |
end if; |
Flags(FL_NEG) <= Sum(7); |
|
when ALU_STP => -- Sets bit(n) in the Flags register |
Flags(Index) <= '1'; |
|
when ALU_BTT => -- Z = !R0(N), N = R0(7) |
Flags(FL_ZERO) <= not Regfile(0)(Index); |
Flags(FL_NEG) <= Regfile(0)(7); |
|
when ALU_CLP => -- Clears bit(n) in the Flags register |
Flags(Index) <= '0'; |
|
when ALU_T0X => -- Rn = R0 : Flags N,Z |
Temp := "0" & Regfile(0); |
Flags(FL_ZERO) <= '0'; |
if( Temp(7 downto 0) = 0 )then |
Flags(FL_ZERO) <= '1'; |
end if; |
Flags(FL_NEG) <= Temp(7); |
Regfile(Index) <= Temp(7 downto 0); |
|
when ALU_CMP => -- Sets Flags on R0 - Rn : Flags N,C,Z |
Sum := ("0" & Regfile(0)) + |
("0" & (not Regfile(Index))) + |
'1'; |
Flags(FL_ZERO) <= '0'; |
if( Sum(7 downto 0) = 0 )then |
Flags(FL_ZERO) <= '1'; |
end if; |
Flags(FL_CARRY) <= Sum(8); |
Flags(FL_NEG) <= Sum(7); |
|
when ALU_MUL => -- Stage 1 of 2 {R1:R0} = R0 * Rn : Flags Z |
Regfile(0) <= Mult(7 downto 0); |
Regfile(1) <= Mult(15 downto 8); |
Flags(FL_ZERO) <= '0'; |
if( Mult = 0 )then |
Flags(FL_ZERO) <= '1'; |
end if; |
|
when ALU_LDI | ALU_POP => -- Rn <= Data : Flags N,Z |
-- The POP instruction doesn't alter the flags, so we need to check |
if( ALU_Ctrl.Oper = ALU_LDI )then |
Flags(FL_ZERO) <= '0'; |
if( ALU_Ctrl.Data = 0 )then |
Flags(FL_ZERO) <= '1'; |
end if; |
Flags(FL_NEG) <= ALU_Ctrl.Data(7); |
end if; |
Regfile(Index) <= ALU_Ctrl.Data; |
|
when ALU_LDX => -- R0 <= Data : Flags N,Z |
Flags(FL_ZERO) <= '0'; |
if( ALU_Ctrl.Data = 0 )then |
Flags(FL_ZERO) <= '1'; |
end if; |
Flags(FL_NEG) <= ALU_Ctrl.Data(7); |
Regfile(0) <= ALU_Ctrl.Data; |
|
when ALU_RFLG => |
Flags <= ALU_Ctrl.Data; |
|
when others => |
null; |
end case; |
|
end if; |
end if; |
end process; |
|
end architecture; |
end rtl; |