URL
https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk
Subversion Repositories open8_urisc
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- This comparison shows the changes necessary to convert path
/open8_urisc/trunk/VHDL
- from Rev 206 to Rev 207
- ↔ Reverse comparison
Rev 206 → Rev 207
/async_ser_rx.vhd
0,0 → 1,194
-- Copyright (c)2006, 2016, 2019 Jeremy Seth Henry |
-- All rights reserved. |
-- |
-- Redistribution and use in source and binary forms, with or without |
-- modification, are permitted provided that the following conditions are met: |
-- * Redistributions of source code must retain the above copyright |
-- notice, this list of conditions and the following disclaimer. |
-- * Redistributions in binary form must reproduce the above copyright |
-- notice, this list of conditions and the following disclaimer in the |
-- documentation and/or other materials provided with the distribution, |
-- where applicable (as part of a user interface, debugging port, etc.) |
-- |
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY |
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY |
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
-- |
-- VHDL Units : async_ser_rx |
-- Description: Asynchronous receiver wired for 8[N/E/O]1 data. Parity mode |
-- and bit rate are set with generics. |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_unsigned.all; |
use ieee.std_logic_arith.all; |
use ieee.std_logic_misc.all; |
|
library work; |
use work.open8_pkg.all; |
|
entity async_ser_rx is |
generic( |
Reset_Level : std_logic; |
Enable_Parity : boolean; |
Parity_Odd_Even_n : std_logic; |
Clock_Divider : integer |
); |
port( |
Clock : in std_logic; |
Reset : in std_logic; |
-- |
Rx_In : in std_logic; |
-- |
Rx_Data : out std_logic_vector(7 downto 0); |
Rx_Valid : out std_logic; |
Rx_PErr : out std_logic |
); |
end entity; |
|
architecture behave of async_ser_rx is |
|
-- The ceil_log2 function returns the minimum register width required to |
-- hold the supplied integer. |
function ceil_log2 (x : in natural) return natural is |
variable retval : natural; |
begin |
retval := 1; |
while ((2**retval) - 1) < x loop |
retval := retval + 1; |
end loop; |
return retval; |
end ceil_log2; |
|
-- Period of each bit in sub-clocks (subtract one to account for zero) |
constant Half_Per_i : integer := (Clock_Divider / 2) - 1; |
constant Full_Per_i : integer := Clock_Divider - 1; |
constant Baud_Bits : integer := ceil_log2(Full_Per_i); |
|
constant HALF_PERIOD : std_logic_vector(Baud_Bits - 1 downto 0) := |
conv_std_logic_vector(Half_Per_i, Baud_Bits); |
constant FULL_PERIOD : std_logic_vector(Baud_Bits - 1 downto 0) := |
conv_std_logic_vector(Full_Per_i, Baud_Bits); |
|
signal Rx_Baud_Cntr : std_logic_vector(Baud_Bits - 1 downto 0); |
|
signal Rx_In_SR : std_logic_vector(3 downto 0); |
alias Rx_In_Q is Rx_In_SR(3); |
|
signal Rx_Buffer : std_logic_vector(7 downto 0); |
signal Rx_Parity : std_logic; |
signal Rx_PErr_int : std_logic; |
|
signal Rx_State : std_logic_vector(3 downto 0); |
alias Rx_Bit_Sel is Rx_State(2 downto 0); |
|
-- State machine definitions |
constant IO_RSV0 : std_logic_vector(3 downto 0) := "1011"; -- B |
constant IO_RSV1 : std_logic_vector(3 downto 0) := "1100"; -- C |
constant IO_STRT : std_logic_vector(3 downto 0) := "1101"; -- D |
constant IO_IDLE : std_logic_vector(3 downto 0) := "1110"; -- E |
constant IO_SYNC : std_logic_vector(3 downto 0) := "1111"; -- F |
constant IO_BIT0 : std_logic_vector(3 downto 0) := "0000"; -- 0 |
constant IO_BIT1 : std_logic_vector(3 downto 0) := "0001"; -- 1 |
constant IO_BIT2 : std_logic_vector(3 downto 0) := "0010"; -- 2 |
constant IO_BIT3 : std_logic_vector(3 downto 0) := "0011"; -- 3 |
constant IO_BIT4 : std_logic_vector(3 downto 0) := "0100"; -- 4 |
constant IO_BIT5 : std_logic_vector(3 downto 0) := "0101"; -- 5 |
constant IO_BIT6 : std_logic_vector(3 downto 0) := "0110"; -- 6 |
constant IO_BIT7 : std_logic_vector(3 downto 0) := "0111"; -- 7 |
constant IO_PARI : std_logic_vector(3 downto 0) := "1000"; -- 8 |
constant IO_STOP : std_logic_vector(3 downto 0) := "1001"; -- 9 |
constant IO_DONE : std_logic_vector(3 downto 0) := "1010"; -- A |
|
begin |
|
Rx_Perr <= Rx_PErr_int; |
|
UART_Regs: process( Clock, Reset ) |
begin |
if( Reset = Reset_Level )then |
Rx_In_SR <= (others => '0'); |
Rx_State <= IO_IDLE; |
Rx_Baud_Cntr <= (others => '0'); |
Rx_Buffer <= (others => '0'); |
Rx_Parity <= '0'; |
Rx_Data <= (others => '0'); |
Rx_Valid <= '0'; |
Rx_PErr_int <= '0'; |
elsif( rising_edge(Clock) )then |
Rx_In_SR <= Rx_In_SR(2 downto 0) & Rx_In; |
|
Rx_Valid <= '0'; |
case( Rx_State )is |
when IO_STRT => |
if( Rx_In_Q = '1' )then |
Rx_State <= Rx_State + 1; |
end if; |
|
when IO_IDLE => |
Rx_Baud_Cntr <= HALF_PERIOD; |
Rx_Parity <= Parity_Odd_Even_n; |
if( Rx_In_Q = '0' )then |
Rx_State <= Rx_State + 1; |
end if; |
|
when IO_SYNC => |
Rx_Baud_Cntr <= Rx_Baud_Cntr - 1; |
if( Rx_Baud_Cntr = 0)then |
Rx_Baud_Cntr <= FULL_PERIOD; |
Rx_State <= Rx_State + 1; |
if( Rx_In_Q = '1' )then -- RxD going low was spurious |
Rx_State <= IO_IDLE; |
end if; |
end if; |
|
when IO_BIT0 | IO_BIT1 | IO_BIT2 | IO_BIT3 | |
IO_BIT4 | IO_BIT5 | IO_BIT6 | IO_BIT7 => |
Rx_Baud_Cntr <= Rx_Baud_Cntr - 1; |
if( Rx_Baud_Cntr = 0 )then |
Rx_Baud_Cntr <= FULL_PERIOD; |
Rx_Buffer(conv_integer(Rx_Bit_Sel)) <= Rx_In_Q; |
if( Enable_Parity )then |
Rx_Parity <= Rx_Parity xor Rx_In_Q; |
Rx_State <= Rx_State + 1; |
else |
Rx_PErr_int <= '0'; |
Rx_State <= Rx_State + 2; |
end if; |
end if; |
|
when IO_PARI => |
Rx_Baud_Cntr <= Rx_Baud_Cntr - 1; |
if( Rx_Baud_Cntr = 0 )then |
Rx_Baud_Cntr <= FULL_PERIOD; |
Rx_PErr_int <= Rx_Parity xor Rx_In_Q; |
Rx_State <= Rx_State + 1; |
end if; |
|
when IO_STOP => |
Rx_Baud_Cntr <= Rx_Baud_Cntr - 1; |
if( Rx_Baud_Cntr = 0 )then |
Rx_State <= Rx_State + 1; |
end if; |
|
when IO_DONE => |
Rx_Data <= Rx_Buffer; |
Rx_Valid <= not Rx_PErr_int; |
Rx_State <= Rx_State + 1; |
|
when others => |
Rx_State <= IO_IDLE; |
|
end case; |
|
end if; |
end process; |
|
end architecture; |
/async_ser_tx.vhd
0,0 → 1,167
-- Copyright (c)2006, 2016, 2019 Jeremy Seth Henry |
-- All rights reserved. |
-- |
-- Redistribution and use in source and binary forms, with or without |
-- modification, are permitted provided that the following conditions are met: |
-- * Redistributions of source code must retain the above copyright |
-- notice, this list of conditions and the following disclaimer. |
-- * Redistributions in binary form must reproduce the above copyright |
-- notice, this list of conditions and the following disclaimer in the |
-- documentation and/or other materials provided with the distribution, |
-- where applicable (as part of a user interface, debugging port, etc.) |
-- |
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY |
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY |
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
-- |
-- VHDL Units : async_ser_tx |
-- Description: Asynchronous transmitter wired for 8[N/E/O]1 data. Parity mode |
-- and bit rate are set with generics. |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_unsigned.all; |
use ieee.std_logic_arith.all; |
use ieee.std_logic_misc.all; |
|
library work; |
use work.open8_pkg.all; |
|
entity async_ser_tx is |
generic( |
Reset_Level : std_logic; |
Enable_Parity : boolean; |
Parity_Odd_Even_n : std_logic; |
Clock_Divider : integer |
); |
port( |
Clock : in std_logic; |
Reset : in std_logic; |
-- |
Tx_Data : in std_logic_vector(7 downto 0); |
Tx_Valid : in std_logic; |
-- |
Tx_Out : out std_logic; |
Tx_Done : out std_logic |
); |
end entity; |
|
architecture behave of async_ser_tx is |
|
constant Tick_Base : integer := Clock_Divider - 1; |
constant Tick_Bits : integer := ceil_log2(Tick_Base); |
constant TICK_DIV : std_logic_vector(Tick_Bits - 1 downto 0) := |
conv_std_logic_vector(Tick_Base, Tick_Bits); |
|
signal Tick_Cntr : std_logic_vector(Tick_Bits - 1 downto 0); |
signal Tick_Trig : std_logic; |
|
signal Tx_Enable : std_logic; |
signal Tx_Buffer : std_logic_vector(7 downto 0); |
signal Tx_Parity : std_logic; |
|
signal Tx_State : std_logic_vector(3 downto 0); |
alias Tx_Bit_Sel is Tx_State(2 downto 0); |
|
-- State machine definitions |
constant IO_RSV0 : std_logic_vector(3 downto 0) := "1011"; -- B |
constant IO_RSV1 : std_logic_vector(3 downto 0) := "1100"; -- C |
constant IO_RSV2 : std_logic_vector(3 downto 0) := "1101"; -- D |
constant IO_IDLE : std_logic_vector(3 downto 0) := "1110"; -- E |
constant IO_STRT : std_logic_vector(3 downto 0) := "1111"; -- F |
constant IO_BIT0 : std_logic_vector(3 downto 0) := "0000"; -- 0 |
constant IO_BIT1 : std_logic_vector(3 downto 0) := "0001"; -- 1 |
constant IO_BIT2 : std_logic_vector(3 downto 0) := "0010"; -- 2 |
constant IO_BIT3 : std_logic_vector(3 downto 0) := "0011"; -- 3 |
constant IO_BIT4 : std_logic_vector(3 downto 0) := "0100"; -- 4 |
constant IO_BIT5 : std_logic_vector(3 downto 0) := "0101"; -- 5 |
constant IO_BIT6 : std_logic_vector(3 downto 0) := "0110"; -- 6 |
constant IO_BIT7 : std_logic_vector(3 downto 0) := "0111"; -- 7 |
constant IO_PARI : std_logic_vector(3 downto 0) := "1000"; -- 8 |
constant IO_STOP : std_logic_vector(3 downto 0) := "1001"; -- 9 |
constant IO_DONE : std_logic_vector(3 downto 0) := "1010"; -- A |
|
begin |
|
UART_Regs: process( Clock, Reset ) |
begin |
if( Reset = Reset_Level )then |
Tick_Cntr <= (others => '0'); |
Tick_Trig <= '0'; |
Tx_State <= IO_IDLE; |
Tx_Enable <= '0'; |
Tx_Buffer <= (others => '0'); |
if( Enable_Parity )then |
Tx_Parity <= '0'; |
end if; |
Tx_Out <= '1'; |
Tx_Done <= '0'; |
elsif( rising_edge(Clock) )then |
Tick_Cntr <= (others => '0'); |
Tick_Trig <= '0'; |
|
if( Tx_Enable = '1' )then |
Tick_Cntr <= Tick_Cntr - 1; |
Tick_Trig <= '0'; |
if( or_reduce(Tick_Cntr) = '0' )then |
Tick_Cntr <= TICK_DIV; |
Tick_Trig <= '1'; |
end if; |
end if; |
|
if( Tx_Valid = '1' )then |
Tx_Buffer <= Tx_Data; |
Tx_Enable <= '1'; |
end if; |
|
Tx_State <= Tx_State + Tick_Trig; |
Tx_Done <= '0'; |
Tx_Out <= '1'; |
|
case( Tx_State )is |
when IO_IDLE => |
if( Enable_Parity )then |
Tx_Parity <= Parity_Odd_Even_n; |
end if; |
|
when IO_STRT => |
Tx_Out <= '0'; |
|
when IO_BIT0 | IO_BIT1 | IO_BIT2 | IO_BIT3 | |
IO_BIT4 | IO_BIT5 | IO_BIT6 | IO_BIT7 => |
Tx_Out <= Tx_Buffer(conv_integer(Tx_Bit_Sel)); |
if( Tick_Trig = '1' and Enable_Parity )then |
Tx_Parity <= Tx_Parity xor Tx_Buffer(conv_integer(Tx_Bit_Sel)); |
end if; |
|
when IO_PARI => |
if( Enable_Parity )then |
Tx_Out <= Tx_Parity; |
end if; |
|
when IO_STOP => |
|
when IO_DONE => |
Tx_Done <= '1'; |
Tx_Enable <= '0'; |
Tx_State <= IO_IDLE; |
|
when others => |
|
end case; |
|
if( Tx_Enable = '0' )then |
Tx_State <= IO_IDLE; |
end if; |
|
end if; |
end process; |
|
end architecture; |
/fifo_1k_core.vhd
0,0 → 1,194
-- megafunction wizard: %FIFO% |
-- GENERATION: STANDARD |
-- VERSION: WM1.0 |
-- MODULE: scfifo |
|
-- ============================================================ |
-- File Name: fifo_1k_core.vhd |
-- Megafunction Name(s): |
-- scfifo |
-- |
-- Simulation Library Files(s): |
-- altera_mf |
-- ============================================================ |
-- ************************************************************ |
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! |
-- |
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition |
-- ************************************************************ |
|
|
--Copyright (C) 1991-2013 Altera Corporation |
--Your use of Altera Corporation's design tools, logic functions |
--and other software and tools, and its AMPP partner logic |
--functions, and any output files from any of the foregoing |
--(including device programming or simulation files), and any |
--associated documentation or information are expressly subject |
--to the terms and conditions of the Altera Program License |
--Subscription Agreement, Altera MegaCore Function License |
--Agreement, or other applicable license agreement, including, |
--without limitation, that your use is for the sole purpose of |
--programming logic devices manufactured by Altera and sold by |
--Altera or its authorized distributors. Please refer to the |
--applicable agreement for further details. |
|
|
LIBRARY ieee; |
USE ieee.std_logic_1164.all; |
|
LIBRARY altera_mf; |
USE altera_mf.all; |
|
ENTITY fifo_1k_core IS |
PORT |
( |
aclr : IN STD_LOGIC ; |
clock : IN STD_LOGIC ; |
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); |
rdreq : IN STD_LOGIC ; |
wrreq : IN STD_LOGIC ; |
almost_full : OUT STD_LOGIC ; |
empty : OUT STD_LOGIC ; |
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) |
); |
END fifo_1k_core; |
|
|
ARCHITECTURE SYN OF fifo_1k_core IS |
|
SIGNAL sub_wire0 : STD_LOGIC ; |
SIGNAL sub_wire1 : STD_LOGIC ; |
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (7 DOWNTO 0); |
|
|
|
COMPONENT scfifo |
GENERIC ( |
add_ram_output_register : STRING; |
almost_full_value : NATURAL; |
intended_device_family : STRING; |
lpm_numwords : NATURAL; |
lpm_showahead : STRING; |
lpm_type : STRING; |
lpm_width : NATURAL; |
lpm_widthu : NATURAL; |
overflow_checking : STRING; |
underflow_checking : STRING; |
use_eab : STRING |
); |
PORT ( |
aclr : IN STD_LOGIC ; |
almost_full : OUT STD_LOGIC ; |
clock : IN STD_LOGIC ; |
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); |
rdreq : IN STD_LOGIC ; |
empty : OUT STD_LOGIC ; |
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); |
wrreq : IN STD_LOGIC |
); |
END COMPONENT; |
|
BEGIN |
almost_full <= sub_wire0; |
empty <= sub_wire1; |
q <= sub_wire2(7 DOWNTO 0); |
|
scfifo_component : scfifo |
GENERIC MAP ( |
add_ram_output_register => "OFF", |
almost_full_value => 922, |
intended_device_family => "Cyclone IV GX", |
lpm_numwords => 1024, |
lpm_showahead => "OFF", |
lpm_type => "scfifo", |
lpm_width => 8, |
lpm_widthu => 10, |
overflow_checking => "ON", |
underflow_checking => "ON", |
use_eab => "ON" |
) |
PORT MAP ( |
aclr => aclr, |
clock => clock, |
data => data, |
rdreq => rdreq, |
wrreq => wrreq, |
almost_full => sub_wire0, |
empty => sub_wire1, |
q => sub_wire2 |
); |
|
|
|
END SYN; |
|
-- ============================================================ |
-- CNX file retrieval info |
-- ============================================================ |
-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" |
-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" |
-- Retrieval info: PRIVATE: AlmostFull NUMERIC "1" |
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "922" |
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1" |
-- Retrieval info: PRIVATE: Clock NUMERIC "0" |
-- Retrieval info: PRIVATE: Depth NUMERIC "1024" |
-- Retrieval info: PRIVATE: Empty NUMERIC "1" |
-- Retrieval info: PRIVATE: Full NUMERIC "0" |
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX" |
-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" |
-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" |
-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" |
-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" |
-- Retrieval info: PRIVATE: Optimize NUMERIC "2" |
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" |
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" |
-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" |
-- Retrieval info: PRIVATE: UsedW NUMERIC "0" |
-- Retrieval info: PRIVATE: Width NUMERIC "8" |
-- Retrieval info: PRIVATE: dc_aclr NUMERIC "0" |
-- Retrieval info: PRIVATE: diff_widths NUMERIC "0" |
-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0" |
-- Retrieval info: PRIVATE: output_width NUMERIC "8" |
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1" |
-- Retrieval info: PRIVATE: rsFull NUMERIC "0" |
-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0" |
-- Retrieval info: PRIVATE: sc_aclr NUMERIC "1" |
-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0" |
-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0" |
-- Retrieval info: PRIVATE: wsFull NUMERIC "1" |
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0" |
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all |
-- Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" |
-- Retrieval info: CONSTANT: ALMOST_FULL_VALUE NUMERIC "922" |
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX" |
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024" |
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" |
-- Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo" |
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8" |
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10" |
-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" |
-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" |
-- Retrieval info: CONSTANT: USE_EAB STRING "ON" |
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr" |
-- Retrieval info: USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL "almost_full" |
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock" |
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" |
-- Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty" |
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" |
-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq" |
-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq" |
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 |
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 |
-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0 |
-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 |
-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 |
-- Retrieval info: CONNECT: almost_full 0 0 0 0 @almost_full 0 0 0 0 |
-- Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0 |
-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0 |
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1k_core.vhd TRUE |
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1k_core.inc FALSE |
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1k_core.cmp FALSE |
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1k_core.bsf FALSE |
-- Retrieval info: GEN_FILE: TYPE_NORMAL o8_sync_xmit_fifo_inst.vhd FALSE |
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1k_core_inst.vhd FALSE |
-- Retrieval info: LIB_FILE: altera_mf |
/o8_async_serial.vhd
0,0 → 1,236
-- Copyright (c)2020 Jeremy Seth Henry |
-- All rights reserved. |
-- |
-- Redistribution and use in source and binary forms, with or without |
-- modification, are permitted provided that the following conditions are met: |
-- * Redistributions of source code must retain the above copyright |
-- notice, this list of conditions and the following disclaimer. |
-- * Redistributions in binary form must reproduce the above copyright |
-- notice, this list of conditions and the following disclaimer in the |
-- documentation and/or other materials provided with the distribution, |
-- where applicable (as part of a user interface, debugging port, etc.) |
-- |
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY |
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY |
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
-- |
-- VHDL Units : o8_async_serial |
-- Description: Provides a single 8-bit, asynchronous transceiver. While the |
-- width is fixed at 8-bits, the bit rate and parity controls |
-- are settable via generics. |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_unsigned.all; |
use ieee.std_logic_arith.all; |
use ieee.std_logic_misc.all; |
|
library work; |
use work.open8_pkg.all; |
|
entity o8_async_serial is |
generic( |
Bit_Rate : real; |
Enable_Parity : boolean; |
Parity_Odd_Even_n : std_logic; |
Sys_Freq : real; |
Reset_Level : std_logic; |
Address : ADDRESS_TYPE |
); |
port( |
Clock : in std_logic; |
Reset : in std_logic; |
-- |
Bus_Address : in ADDRESS_TYPE; |
Wr_Enable : in std_logic; |
Wr_Data : in DATA_TYPE; |
Rd_Enable : in std_logic; |
Rd_Data : out DATA_TYPE; |
-- |
TX_Out : out std_logic; |
CTS_In : in std_logic; |
RX_In : in std_logic; |
RTS_Out : out std_logic |
); |
end entity; |
|
architecture behave of o8_async_serial is |
|
signal FIFO_Reset : std_logic := '0'; |
|
constant User_Addr : std_logic_vector(15 downto 1) := |
Address(15 downto 1); |
alias Comp_Addr is Bus_Address(15 downto 1); |
signal Addr_Match : std_logic := '0'; |
|
alias Reg_Addr is Bus_Address(0); |
signal Reg_Sel : std_logic := '0'; |
signal Rd_En : std_logic := '0'; |
|
signal TX_FIFO_Wr_En : std_logic := '0'; |
alias TX_FIFO_Wr_Data is Wr_Data; |
signal TX_FIFO_Rd_En : std_logic := '0'; |
signal TX_FIFO_Empty : std_logic := '0'; |
signal TX_FIFO_AFull : std_logic := '0'; |
signal TX_FIFO_Rd_Data : DATA_TYPE := x"00"; |
|
alias Tx_Data is TX_FIFO_Rd_Data; |
|
type TX_CTRL_STATES is (IDLE, TX_BYTE, TX_START, TX_WAIT ); |
signal TX_Ctrl : TX_CTRL_STATES := IDLE; |
|
signal TX_Xmit : std_logic := '0'; |
signal TX_Done : std_logic := '0'; |
|
constant BAUD_RATE_DIV : integer := integer(Sys_Freq / Bit_Rate); |
|
signal CTS_sr : std_logic_vector(3 downto 0) := "0000"; |
alias CTS_Okay is CTS_sr(3); |
|
signal RX_FIFO_Wr_En : std_logic := '0'; |
signal RX_FIFO_Wr_Data : DATA_TYPE; |
signal RX_FIFO_Rd_En : std_logic; |
signal RX_FIFO_Empty : std_logic; |
signal RX_FIFO_AFull : std_logic; |
signal RX_FIFO_Rd_Data : DATA_TYPE; |
|
begin |
|
Addr_Match <= '1' when Comp_Addr = User_Addr else '0'; |
|
io_reg: process( Clock, Reset ) |
begin |
if( Reset = Reset_Level )then |
Rd_En <= '0'; |
Rd_Data <= OPEN8_NULLBUS; |
RTS_Out <= '0'; |
elsif( rising_edge( Clock ) )then |
Rd_Data <= OPEN8_NULLBUS; |
Rd_En <= Rd_Enable and Addr_Match; |
Reg_Sel <= Reg_Addr; |
if( Rd_En = '1' and Reg_Sel = '1' )then |
Rd_Data(4) <= RX_FIFO_Empty; |
Rd_Data(5) <= RX_FIFO_AFull; |
Rd_Data(6) <= TX_FIFO_Empty; |
Rd_Data(7) <= TX_FIFO_AFull; |
end if; |
if( Rd_En = '1' and Reg_Sel = '0' )then |
Rd_Data <= RX_FIFO_Rd_Data; |
end if; |
RTS_Out <= not RX_FIFO_AFull; |
end if; |
end process; |
|
TX_FIFO_Wr_En <= Wr_Enable and Addr_Match and not Reg_Addr; |
|
FIFO_Reset <= '1' when Reset = Reset_Level else '0'; |
|
U_TX_FIFO : entity work.fifo_1k_core |
port map( |
aclr => FIFO_Reset, |
clock => Clock, |
data => TX_FIFO_Wr_Data, |
rdreq => TX_FIFO_Rd_En, |
wrreq => TX_FIFO_Wr_En, |
empty => TX_FIFO_Empty, |
almost_full => TX_FIFO_AFull, |
q => TX_FIFO_Rd_Data |
); |
|
tx_FSM: process( Clock, Reset ) |
begin |
if( Reset = Reset_Level )then |
TX_Ctrl <= IDLE; |
TX_Xmit <= '0'; |
TX_FIFO_Rd_En <= '0'; |
CTS_sr <= (others => '0'); |
elsif( rising_edge(Clock) )then |
TX_Xmit <= '0'; |
TX_FIFO_Rd_En <= '0'; |
CTS_sr <= CTS_sr(2 downto 0) & CTS_In; |
|
case( TX_Ctrl )is |
when IDLE => |
if( TX_FIFO_Empty = '0' and CTS_Okay = '1' )then |
TX_FIFO_Rd_En <= '1'; |
TX_Ctrl <= TX_BYTE; |
end if; |
|
when TX_BYTE => |
TX_Xmit <= '1'; |
TX_Ctrl <= TX_START; |
|
when TX_START => |
if( Tx_Done = '0' )then |
TX_Ctrl <= TX_WAIT; |
end if; |
|
when TX_WAIT => |
if( Tx_Done = '1' )then |
TX_Ctrl <= IDLE; |
end if; |
|
when others => null; |
end case; |
|
end if; |
end process; |
|
U_TX : entity work.async_ser_tx |
generic map( |
Reset_Level => Reset_Level, |
Enable_Parity => Enable_Parity, |
Parity_Odd_Even_n => Parity_Odd_Even_n, |
Clock_Divider => BAUD_RATE_DIV |
) |
port map( |
Clock => Clock, |
Reset => Reset, |
-- |
Tx_Data => Tx_Data, |
Tx_Valid => TX_Xmit, |
-- |
Tx_Out => TX_Out, |
Tx_Done => Tx_Done |
); |
|
U_RX : entity work.async_ser_rx |
generic map( |
Reset_Level => Reset_Level, |
Enable_Parity => Enable_Parity, |
Parity_Odd_Even_n => Parity_Odd_Even_n, |
Clock_Divider => BAUD_RATE_DIV |
) |
port map( |
Clock => Clock, |
Reset => Reset, |
-- |
Rx_In => RX_In, |
-- |
Rx_Data => RX_FIFO_Wr_Data, |
Rx_Valid => RX_FIFO_Wr_En, |
Rx_PErr => open |
); |
|
RX_FIFO_Rd_En <= Rd_Enable and Addr_Match and not Reg_Addr; |
|
U_RX_FIFO : entity work.fifo_1k_core |
port map( |
aclr => FIFO_Reset, |
clock => Clock, |
data => RX_FIFO_Wr_Data, |
rdreq => RX_FIFO_Rd_En, |
wrreq => RX_FIFO_Wr_En, |
empty => RX_FIFO_Empty, |
almost_full => RX_FIFO_AFull, |
q => RX_FIFO_Rd_Data |
); |
|
end architecture; |