URL
https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk
Subversion Repositories open8_urisc
Compare Revisions
- This comparison shows the changes necessary to convert path
/open8_urisc/trunk/VHDL
- from Rev 218 to Rev 217
- ↔ Reverse comparison
Rev 218 → Rev 217
/vdsm8.vhd
File deleted
/async_ser_tx.vhd
1,4 → 1,4
-- Copyright (c)2006, 2016, 2020 Jeremy Seth Henry |
-- Copyright (c)2006, 2016, 2019 Jeremy Seth Henry |
-- All rights reserved. |
-- |
-- Redistribution and use in source and binary forms, with or without |
30,11 → 30,6
-- ensure the receiver can successfully receive. With a sufficiently |
-- high core clock, this is generally achievable for common PC serial |
-- data rates. |
-- |
-- Revision History |
-- Author Date Change |
------------------ -------- --------------------------------------------------- |
-- Seth Henry 04/14/20 Code cleanup and revision section added |
|
library ieee; |
use ieee.std_logic_1164.all; |
/async_ser_rx.vhd
25,16 → 25,12
-- Description: Asynchronous receiver wired for 8[N/E/O]1 data. Parity mode |
-- and bit rate are set with generics. |
-- |
-- |
-- Note: The baud rate generator will produce an approximate frequency. The |
-- final bit rate should be within +/- 1% of the true bit rate to |
-- ensure the receiver can successfully receive. With a sufficiently |
-- high core clock, this is generally achievable for common PC serial |
-- data rates. |
-- |
-- Revision History |
-- Author Date Change |
------------------ -------- --------------------------------------------------- |
-- Seth Henry 04/14/20 Code cleanup and revision section added |
|
library ieee; |
use ieee.std_logic_1164.all; |
/button_db.vhd
24,11 → 24,6
-- VHDL Units : button_db |
-- Description: Debounces a single button/switch and provides a change of |
-- state signal as well as registered level. |
-- |
-- Revision History |
-- Author Date Change |
------------------ -------- --------------------------------------------------- |
-- Seth Henry 04/14/20 Code cleanup and revision section added |
|
library ieee; |
use ieee.std_logic_1164.all; |