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URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

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  • This comparison shows the changes necessary to convert path 
    /open8_urisc/trunk/VHDL
    from Rev 251 to Rev 250
    ↔ Reverse comparison
  •

Rev 251 → Rev 250

/status_led.vhd
25,11 → 25,11
-- Description: Provides a multi-state status LED controller
--
-- LED Modes:
-- 0x0 - LED is fully off
-- 0x1 - LED is fully on
-- 0x2 - LED is dimmed to 50%
-- 0x3 - LED Toggles at 1Hz
-- 0x4 - LED fades in and out
-- 0x00 - LED is fully off
-- 0x01 - LED is fully on
-- 0x02 - LED is dimmed to 50%
-- 0x03 - LED Toggles at 1Hz
-- 0x04 - LED fades in and out
--
-- Revision History
-- Author Date Change
44,7 → 44,6
 
entity status_led is
generic(
Sys_Freq : real;
Reset_Level : std_logic
);
port(
57,38 → 56,18
 
architecture behave of status_led is
 
-- hold the supplied integer.
function ceil_log2 (x : in natural) return natural is
variable retval : natural;
begin
retval := 1;
while ((2**retval) - 1) < x loop
retval := retval + 1;
end loop;
return retval;
end function;
signal Dim50Pct_Out : std_logic;
 
signal Dim50Pct_Out : std_logic := '0';
signal Half_Hz_Timer : std_logic_vector(15 downto 0);
constant HALF_HZ_PRD : std_logic_vector(15 downto 0) :=
conv_std_logic_vector(500000,16);
signal One_Hz_Out : std_logic;
 
constant TAP1 : integer := 16;
constant TAP2 : integer := 21;
constant TAP3 : integer := 22;
constant TAP4 : integer := 23;
 
constant Init_Seed : std_logic_vector(23 downto 0) := x"000001";
 
signal d0 : std_logic := '0';
signal LFSR_poly : std_logic_vector(23 downto 0) := (others => '0');
 
signal Cycle_Toggle : std_logic;
 
constant TIMER_MSB : integer range 9 to 20 := 18;
 
signal Fade_Timer1 : std_logic_vector(TIMER_MSB downto 0) :=
(others => '0');
signal Fade_Timer2 : std_logic_vector(TIMER_MSB downto 0) :=
(others => '0');
signal Fade_Out : std_logic := '0';
signal Fade_Timer1 : std_logic_vector(TIMER_MSB downto 0);
signal Fade_Timer2 : std_logic_vector(TIMER_MSB downto 0);
signal Fade_Out : std_logic;
 
begin
 
104,7 → 83,7
when "010" =>
LED_Out <= Dim50Pct_Out;
when "011" =>
LED_Out <= Cycle_Toggle;
LED_Out <= One_Hz_Out;
when "100" =>
LED_Out <= Fade_out;
when others => null;
112,15 → 91,12
end if;
end process;
 
d0 <= LFSR_poly(TAP4) xnor LFSR_poly(TAP3) xnor
LFSR_poly(TAP2) xnor LFSR_poly(TAP1);
 
Timer_proc: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Dim50Pct_Out <= '0';
LFSR_poly <= Init_Seed;
Cycle_Toggle <= '0';
Half_Hz_Timer <= (others => '0');
One_Hz_Out <= '0';
Fade_Timer1 <= (others => '0');
Fade_Timer2 <= (others => '0');
Fade_out <= '0';
127,9 → 103,10
elsif( rising_edge(Clock) )then
Dim50Pct_Out <= not Dim50Pct_Out;
 
LFSR_poly <= LFSR_poly(22 downto 0) & d0;
if( LFSR_poly = Init_Seed )then
Cycle_Toggle <= not Cycle_Toggle;
Half_Hz_Timer <= Half_Hz_Timer - 1;
if( Half_Hz_Timer = 0 )then
Half_Hz_Timer <= HALF_HZ_PRD;
One_Hz_Out <= not One_Hz_Out;
end if;
 
Fade_Timer1 <= Fade_Timer1 - 1;
/o8_ram_1k.vhd
60,8 → 60,7
);
port(
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE;
Write_Fault : out std_logic
Rd_Data : out DATA_TYPE
);
end entity;
 
111,8 → 110,6
signal RAM_Rd_En_q : std_logic := '0';
signal RAM_Rd_Data : DATA_TYPE := OPEN8_NULLBUS;
 
signal Write_Fault_d : std_logic := '0';
 
begin
 
Write_Protect_On : if( Write_Protect )generate
129,8 → 126,6
RAM_Rd_En_d <= RAM_Addr_Match and Rd_En;
RAM_Wr_En_d <= RAM_Addr_Match and RAM_Region_Match and Wr_En;
 
Write_Fault_d <= RAM_Addr_Match and (not RAM_Region_Match) and Wr_En;
 
RAM_proc: process( Reset, Clock )
begin
if( Reset = Reset_Level )then
144,9 → 139,6
 
RAM_Rd_En_q <= '0';
Rd_Data <= OPEN8_NULLBUS;
 
Write_Fault <= '0';
 
elsif( rising_edge(Clock) )then
WPR_Reg_Sel_q <= WPR_Reg_Sel_d;
 
179,9 → 171,6
null;
end case;
end if;
 
Write_Fault <= Write_Fault_d;
 
end if;
end process;
 
/o8_ram_4k.vhd
62,8 → 62,7
);
port(
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE;
Write_Fault : out std_logic
Rd_Data : out DATA_TYPE
);
end entity;
 
116,8 → 115,6
signal RAM_Rd_En_q : std_logic := '0';
signal RAM_Rd_Data : DATA_TYPE := OPEN8_NULLBUS;
 
signal Write_Fault_d : std_logic := '0';
 
begin
 
Write_Protect_On : if( Write_Protect )generate
134,8 → 131,6
RAM_Rd_En_d <= RAM_Addr_Match and Rd_En;
RAM_Wr_En_d <= RAM_Addr_Match and RAM_Region_Match and Wr_En;
 
Write_Fault_d <= RAM_Addr_Match and (not RAM_Region_Match) and Wr_En;
 
RAM_proc: process( Reset, Clock )
begin
if( Reset = Reset_Level )then
150,9 → 145,6
 
RAM_Rd_En_q <= '0';
Rd_Data <= OPEN8_NULLBUS;
 
Write_Fault <= '0';
 
elsif( rising_edge(Clock) )then
WPR_Reg_Sel_q <= WPR_Reg_Sel_d;
 
193,9 → 185,6
null;
end case;
end if;
 
Write_Fault <= Write_Fault_d;
 
end if;
end process;
 
/Open8_pkg.vhd
197,9 → 197,9
BRN_C1, DBNZ_C1, JMP_C1, JMP_C2,
-- Loads
LDA_C1, LDA_C2, LDA_C3, LDA_C4, LDI_C1,
LDO_C1, LDO_C2, LDX_C1, LDX_C2, LDX_C3, LDX_C4,
LDO_C1, LDX_C1, LDX_C2, LDX_C3, LDX_C4,
-- Stores
STA_C1, STA_C2, STA_C3, STO_C1, STO_C2, STO_C3, STX_C1, STX_C2,
STA_C1, STA_C2, STA_C3, STO_C1, STO_C2, STX_C1, STX_C2,
-- 2-cycle math
MUL_C1, UPP_C1,
-- Stack

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