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    /open8_urisc/trunk/VHDL
    from Rev 267 to Rev 268
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Rev 267 → Rev 268

/o8_int_mgr16.vhd
0,0 → 1,235
-- Copyright (c)2020 Jeremy Seth Henry
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution,
-- where applicable (as part of a user interface, debugging port, etc.)
--
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- VHDL Units : o8_int_mgr16
-- Description: Provides an 8-bit microsecond resolution timer for generating
-- : periodic interrupts for the Open8 CPU as well as providing a
-- : second level interrupt manager for I/O interrupts
--
-- Register Map:
-- Offset Bitfield Description Read/Write
-- 0x00 AAAAAAAA PIT Timer Interval (0 = disabled) (RW)
-- 0x01 -------- (unused)
-- 0x02 AAAAAAAA External Interrupt Mask (lower) (RW)
-- 0x03 AAAAAAAA External Interrupt Mask (upper) (RW)
-- 0x04 AAAAAAAA Pending External Ints* (lower) (RW)
-- 0x05 AAAAAAAA Pending External Ints* (upper) (RW)
-- 0x06 -------- (unused)
-- 0x07 A------- Interrupt Requested (write to clear) (RW)
--
-- Note: Each bit in the pending register is individually clearable by writing
-- a '1' to it, allowing interrupts to be cleared individually
--
-- Revision History
-- Author Date Change
------------------ -------- ---------------------------------------------------
-- Seth Henry 05/21/20 Design Start
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
 
library work;
use work.open8_pkg.all;
 
entity o8_int_mgr16 is
generic(
Default_Int_Mask : ADDRESS_TYPE := x"0000";
Address : ADDRESS_TYPE
);
port(
Open8_Bus : in OPEN8_BUS_TYPE;
Interrupts : in ADDRESS_TYPE := x"0000";
Rd_Data : out DATA_TYPE;
PIT_Interrupt : out std_logic;
EXT_Interrupt : out std_logic
);
end entity;
 
architecture behave of o8_int_mgr16 is
 
alias Clock is Open8_Bus.Clock;
alias Reset is Open8_Bus.Reset;
alias uSec_Tick is Open8_Bus.uSec_Tick;
alias CPU_ISR_En is Open8_Bus.GP_Flags(EXT_ISR);
alias CPU_Wr_En is Open8_Bus.Wr_En;
alias CPU_Rd_En is Open8_Bus.Rd_En;
 
constant User_Addr : std_logic_vector(15 downto 3) :=
Address(15 downto 3);
alias Comp_Addr is Open8_Bus.Address(15 downto 3);
signal Addr_Match : std_logic := '0';
 
alias Reg_Sel_d is Open8_Bus.Address(2 downto 0);
signal Reg_Sel_q : std_logic_vector(2 downto 0);
signal Wr_En_d : std_logic;
signal Wr_En_q : std_logic := '0';
alias Wr_Data_d is Open8_Bus.Wr_Data;
signal Wr_Data_q : DATA_TYPE := x"00";
signal Rd_En_d : std_logic := '0';
signal Rd_En_q : std_logic := '0';
 
signal Interval : DATA_TYPE := x"00";
signal Update_Interval : std_logic;
signal Timer_Cnt : DATA_TYPE := x"00";
 
signal Int_Mask : ADDRESS_TYPE := x"0000";
alias Int_Mask_l is Int_Mask(7 downto 0);
alias Int_Mask_h is Int_Mask(15 downto 8);
 
signal Clear_Pending : ADDRESS_TYPE := x"0000";
alias Clear_Pending_l is Clear_Pending(7 downto 0);
alias Clear_Pending_h is Clear_Pending(15 downto 8);
 
signal Ack_IO_Ints : std_logic;
 
signal Pending : ADDRESS_TYPE := x"0000";
alias Pending_l is Pending(7 downto 0);
alias Pending_h is Pending(15 downto 8);
signal Pending_q : ADDRESS_TYPE := x"0000";
signal Pending_RE : ADDRESS_TYPE := x"0000";
 
signal IO_Int_Pending : std_logic;
 
begin
 
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
Wr_En_d <= Addr_Match and CPU_Wr_En and CPU_ISR_En;
Rd_En_d <= Addr_Match and CPU_Rd_En;
 
io_reg: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Reg_Sel_q <= (others => '0');
Wr_En_q <= '0';
Wr_Data_q <= x"00";
Rd_En_q <= '0';
Rd_Data <= OPEN8_NULLBUS;
Interval <= x"00";
Update_Interval <= '0';
Int_Mask <= Default_Int_Mask;
Clear_Pending <= x"0000";
Ack_IO_Ints <= '0';
elsif( rising_edge( Clock ) )then
Reg_Sel_q <= Reg_Sel_d;
Wr_En_q <= Wr_En_d;
Wr_Data_q <= Wr_Data_d;
 
Update_Interval <= Wr_En_q;
Clear_Pending <= x"0000";
Ack_IO_Ints <= '0';
if( Wr_En_q = '1' )then
case( Reg_Sel_q )is
when "000" =>
Interval <= Wr_Data_q;
when "010" =>
Int_Mask_l <= Wr_Data_q;
when "011" =>
Int_Mask_h <= Wr_Data_q;
 
when "100" =>
Clear_Pending_l <= Wr_Data_q;
when "101" =>
Clear_Pending_h <= Wr_Data_q;
 
when "111" =>
Ack_IO_Ints <= '1';
when others =>
null;
end case;
end if;
 
Rd_Data <= (others => '0');
Rd_En_q <= Rd_En_d;
if( Rd_En_q = '1' )then
case( Reg_Sel_q )is
when "000" =>
Rd_Data <= Interval;
when "010" =>
Rd_Data <= Int_Mask_l;
when "011" =>
Rd_Data <= Int_Mask_h;
when "100" =>
Rd_Data <= Pending_l;
when "101" =>
Rd_Data <= Pending_h;
when "111" =>
Rd_Data <= IO_Int_Pending & "0000000";
when others =>
null;
end case;
end if;
end if;
end process;
 
Interval_proc: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Timer_Cnt <= x"00";
PIT_Interrupt <= '0';
elsif( rising_edge(Clock) )then
PIT_Interrupt <= '0';
Timer_Cnt <= Timer_Cnt - uSec_Tick;
if( Update_Interval = '1' )then
Timer_Cnt <= Interval;
elsif( or_reduce(Timer_Cnt) = '0' )then
Timer_Cnt <= Interval;
PIT_Interrupt <= or_reduce(Interval); -- Only trigger on Int > 0
end if;
end if;
end process;
 
Interrupt_proc: process( Clock, Reset )
variable i : integer := 0;
begin
if( Reset = Reset_Level )then
Pending <= x"0000";
Pending_q <= x"0000";
Pending_RE <= x"0000";
IO_Int_Pending <= '0';
EXT_Interrupt <= '0';
elsif( rising_edge(Clock) )then
for i in 0 to 15 loop
if( Interrupts(i) = '1' and Int_Mask(i) = '1' )then
Pending(i) <= '1';
elsif( Clear_Pending(i) = '1' )then
Pending(i) <= '0';
end if;
Pending_q(i) <= Pending(i);
Pending_RE(i) <= Pending(i) and not Pending_q(i);
end loop;
 
EXT_Interrupt <= '0';
if( or_reduce(Pending_RE) = '1' and IO_Int_Pending = '0' )then
IO_Int_Pending <= '1';
EXT_Interrupt <= '1';
elsif( Ack_IO_Ints = '1' )then
IO_Int_Pending <= '0';
end if;
 
end if;
end process;
 
end architecture;
/o8_spi_16b_tx.vhd
0,0 → 1,253
-- Copyright (c) 2020 Jeremy Seth Henry
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution,
-- where applicable (as part of a user interface, debugging port, etc.)
--
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- VHDL units : o8_spi_16b_tx
-- Description: Transmits (only) a 16-bit word using a synchronous interface
-- Clock_Polarity sets the clock state at idle
-- Clock_Phase sets the clock edge data is shifted on
-- Half_Period_Clks sets the number of CPU clocks used to generate
-- a half-period tick that runs the transmit state machine.
-- (Note that 2x this value is the full SPI period in CPU clocks)
--
-- Register Map:
-- Offset Bitfield Description Read/Write
-- 0x0 AAAAAAAA Pending Word (7:0) (R/W)
-- 0x1 AAAAAAAA Pending Word (11:8) (R/W)
-- 0x2 A------- Busy Flag / TX on Write (R/W)
--
-- Revision History
-- Author Date Change
------------------ -------- ---------------------------------------------------
-- Seth Henry 09/16/20 Initial version
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
 
library work;
use work.open8_pkg.all;
 
entity o8_spi_16b_tx is
generic(
Clock_Polarity : std_logic;
Clock_Phase : std_logic;
Half_Period_Clks : integer range 1 to integer'high;
Address : ADDRESS_TYPE
);
port(
Open8_Bus : in OPEN8_BUS_TYPE;
Write_Qual : in std_logic;
Rd_Data : out DATA_TYPE;
-- SPI
DOUT : out std_logic;
SCLK : out std_logic;
SYNC : out std_logic
);
end entity;
 
architecture behave of o8_spi_16b_tx is
 
alias Clock is Open8_Bus.Clock;
alias Reset is Open8_Bus.Reset;
alias uSec_Tick is Open8_Bus.uSec_Tick;
 
constant Clk_Div_i : integer := Half_Period_Clks - 1;
constant Clk_Div_Bits : integer := ceil_log2(Clk_Div_i);
constant CLK_DIV_VAL : std_logic_vector(Clk_Div_Bits - 1 downto 0) :=
conv_std_logic_vector(Clk_Div_i,Clk_Div_Bits);
signal HT_Cntr : std_logic_vector(Clk_Div_Bits - 1 downto 0);
signal HT_Tick : std_logic := '0';
 
constant User_Addr : std_logic_vector(15 downto 2) := Address(15 downto 2);
alias Comp_Addr is Open8_Bus.Address(15 downto 2);
signal Addr_Match : std_logic;
alias Reg_Sel_d is Open8_Bus.Address(1 downto 0);
signal Reg_Sel_q : std_logic_vector(1 downto 0);
signal Wr_En_d : std_logic := '0';
signal Wr_En_q : std_logic := '0';
alias Wr_Data_d is Open8_Bus.Wr_Data;
signal Wr_Data_q : DATA_TYPE := x"00";
signal Rd_En_d : std_logic := '0';
signal Rd_En_q : std_logic := '0';
 
signal spi_xmit : std_logic := '0';
 
type SPI_STATES is ( IDLE, ALIGN, SYNC_START, CLK_SETUP, CLK_HOLD, CLK_END, SYNC_END );
signal spi_state : SPI_STATES;
 
signal spi_buffer : std_logic_vector(15 downto 0) := x"0000";
alias spi_buffer_lb is spi_buffer(7 downto 0);
alias spi_buffer_ub is spi_buffer(15 downto 8);
signal bit_cntr : std_logic_vector(3 downto 0) := x"0";
signal spi_busy : std_logic := '0';
 
begin
 
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
Wr_En_d <= Addr_Match and Open8_Bus.Wr_En;
Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
 
io_reg: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Reg_Sel_q <= "00";
Wr_En_q <= '0';
Wr_Data_q <= x"00";
Rd_En_q <= '0';
Rd_Data <= OPEN8_NULLBUS;
 
spi_buffer <= (others => '0');
spi_xmit <= '0';
 
elsif( rising_edge( Clock ) )then
Reg_Sel_q <= Reg_Sel_d;
 
Wr_En_q <= Wr_En_d;
Wr_Data_q <= Wr_Data_d;
 
spi_xmit <= '0';
if( Wr_En_q = '1' and Write_Qual = '1' )then
case( Reg_Sel_q )is
when "00" =>
spi_buffer_lb <= Wr_Data_q;
when "01" =>
spi_buffer_ub <= Wr_Data_q;
when "10" | "11" =>
spi_xmit <= '1';
when others =>
null;
end case;
end if;
 
Rd_En_q <= Rd_En_d;
Rd_Data <= OPEN8_NULLBUS;
if( Rd_En_q = '1' )then
case( Reg_Sel_q )is
when "00" =>
Rd_Data <= spi_buffer_lb;
when "01" =>
Rd_Data <= spi_buffer_ub;
when "10" | "11" =>
Rd_Data <= spi_busy & "0000000";
when others =>
null;
end case;
end if;
end if;
end process;
 
ADC_IO_FSM: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
spi_state <= IDLE;
bit_cntr <= (others => '0');
spi_busy <= '0';
 
HT_Cntr <= (others => '0');
HT_Tick <= '0';
 
DOUT <= '0';
SCLK <= '0';
SYNC <= '1';
elsif( rising_edge(Clock) )then
 
HT_Cntr <= HT_Cntr - 1;
HT_Tick <= '0';
if( HT_Cntr = 0 )then
HT_Cntr <= CLK_DIV_VAL;
HT_Tick <= '1';
end if;
 
case( spi_state )is
when IDLE =>
DOUT <= '0';
SCLK <= Clock_Polarity;
SYNC <= '1';
bit_cntr <= x"F";
spi_busy <= '0';
if( spi_xmit = '1' )then
spi_busy <= '1';
spi_state <= ALIGN;
end if;
 
when ALIGN =>
if( HT_Tick = '1' )then
spi_state <= CLK_SETUP;
if( Clock_Phase = '1' )then
spi_state <= SYNC_START;
end if;
end if;
 
when SYNC_START =>
SYNC <= '0';
if( HT_Tick = '1' )then
spi_state <= CLK_SETUP;
end if;
 
when CLK_SETUP =>
SCLK <= Clock_Polarity xor Clock_Phase;
DOUT <= spi_buffer(conv_integer(bit_cntr));
SYNC <= '0';
if( HT_Tick = '1' )then
spi_state <= CLK_HOLD;
end if;
 
when CLK_HOLD =>
SCLK <= (not Clock_Polarity) xor Clock_Phase;
DOUT <= spi_buffer(conv_integer(bit_cntr));
if( HT_Tick = '1' )then
bit_cntr <= bit_cntr - 1;
spi_state <= CLK_SETUP;
if( bit_cntr = 0 )then
spi_state <= CLK_END;
end if;
end if;
 
when CLK_END =>
SCLK <= Clock_Polarity;
if( Clock_Phase = '1' )then
SYNC <= '1';
end if;
if( HT_Tick = '1' )then
spi_state <= SYNC_END;
if( Clock_Phase = '1' )then
spi_state <= IDLE;
end if;
end if;
 
when SYNC_END =>
SYNC <= '1';
if( HT_Tick = '1' )then
spi_state <= IDLE;
end if;
 
when others =>
null;
end case;
 
end if;
end process;
 
end architecture;
/o8_vdsm12.vhd
43,6 → 43,7
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
 
library work;
use work.open8_pkg.all;
49,6 → 50,7
 
entity o8_vdsm12 is
generic(
Invert_Output : boolean := FALSE;
Default_Value : std_logic_vector(11 downto 0) := x"000";
Address : ADDRESS_TYPE
);
303,9 → 305,13
Period_Ctr <= Period_Ctr - 1;
Width_Ctr <= Width_Ctr - 1;
 
DACOut <= '1';
if( Invert_Output )then
DACOut <= or_reduce(Width_Ctr);
else
DACOut <= nor_reduce(Width_Ctr);
end if;
 
if( Width_Ctr = 0 )then
DACOut <= '0';
Width_Ctr <= (others => '0');
end if;
 
/o8_vdsm8.vhd
47,6 → 47,7
 
entity o8_vdsm8 is
generic(
Invert_Output : boolean := FALSE;
Default_Value : DATA_TYPE := x"00";
Address : ADDRESS_TYPE
);
77,6 → 78,8
 
signal Reg_Out : DATA_TYPE;
 
signal DACout_pre : std_logic;
 
begin
 
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
114,7 → 117,10
Clock => Clock,
Reset => Reset,
DACin => Reg_Out,
DACout => DACout
DACout => DACout_pre
);
 
DACout <= (not DACout_pre) when Invert_Output else
DACout_pre;
 
end architecture;
/vector_tx.vhd
65,28 → 65,45
signal Button_Pressed : std_logic := '0';
signal Button_CoS : std_logic := '0';
 
type VEC_ARG_TYPE is array(0 to 15) of std_logic_vector(15 downto 0);
type VEC_ARG_TYPE is array(0 to 31) of std_logic_vector(15 downto 0);
constant VEC_ARGS : VEC_ARG_TYPE := (
x"0000",
x"1111",
x"2222",
x"3333",
x"4444",
x"5555",
x"6666",
x"7777",
x"8888",
x"9999",
x"AAAA",
x"BBBB",
x"CCCC",
x"DDDD",
x"EEEE",
x"0001",
x"0002",
x"0003",
x"0004",
x"0005",
x"0006",
x"0007",
x"0008",
x"0009",
x"000A",
x"000B",
x"000C",
x"000D",
x"000E",
x"000F",
 
x"0800",
x"0866",
x"0975",
x"00AE",
x"DEAD",
x"BEEF",
x"CAFE",
x"BABE",
x"DECA",
x"A5A5",
x"C3C3",
x"0123",
x"4567",
x"89AB",
x"CDEF",
x"FFFF"
);
 
alias Vector_Arg_Sel is Switches(9 downto 6);
alias Vector_Cmd_Sel is Switches(5 downto 0);
alias Vector_Arg_Sel is Switches(9 downto 5);
alias Vector_Cmd_Sel is Switches(4 downto 0);
 
signal Vector_Cmd : std_logic_vector(7 downto 0);
 
139,7 → 156,7
Vector_Cmd <= x"00";
Vector_Arg <= x"0000";
elsif( rising_edge(Clock) )then
Vector_Cmd <= "00" & Vector_Cmd_Sel;
Vector_Cmd <= "000" & Vector_Cmd_Sel;
Vector_Arg <= VEC_ARGS(conv_integer(Vector_Arg_Sel));
end if;
end process;

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