URL
https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk
Subversion Repositories open8_urisc
Compare Revisions
- This comparison shows the changes necessary to convert path
/open8_urisc/trunk/VHDL
- from Rev 268 to Rev 267
- ↔ Reverse comparison
Rev 268 → Rev 267
/o8_int_mgr16.vhd
File deleted
/o8_spi_16b_tx.vhd
File deleted
\ No newline at end of file
/o8_vdsm12.vhd
43,7 → 43,6
use ieee.std_logic_1164.all; |
use ieee.std_logic_unsigned.all; |
use ieee.std_logic_arith.all; |
use ieee.std_logic_misc.all; |
|
library work; |
use work.open8_pkg.all; |
50,7 → 49,6
|
entity o8_vdsm12 is |
generic( |
Invert_Output : boolean := FALSE; |
Default_Value : std_logic_vector(11 downto 0) := x"000"; |
Address : ADDRESS_TYPE |
); |
305,13 → 303,9
Period_Ctr <= Period_Ctr - 1; |
Width_Ctr <= Width_Ctr - 1; |
|
if( Invert_Output )then |
DACOut <= or_reduce(Width_Ctr); |
else |
DACOut <= nor_reduce(Width_Ctr); |
end if; |
|
DACOut <= '1'; |
if( Width_Ctr = 0 )then |
DACOut <= '0'; |
Width_Ctr <= (others => '0'); |
end if; |
|
/o8_vdsm8.vhd
47,7 → 47,6
|
entity o8_vdsm8 is |
generic( |
Invert_Output : boolean := FALSE; |
Default_Value : DATA_TYPE := x"00"; |
Address : ADDRESS_TYPE |
); |
78,8 → 77,6
|
signal Reg_Out : DATA_TYPE; |
|
signal DACout_pre : std_logic; |
|
begin |
|
Addr_Match <= '1' when Comp_Addr = User_Addr else '0'; |
117,10 → 114,7
Clock => Clock, |
Reset => Reset, |
DACin => Reg_Out, |
DACout => DACout_pre |
DACout => DACout |
); |
|
DACout <= (not DACout_pre) when Invert_Output else |
DACout_pre; |
|
end architecture; |
/vector_tx.vhd
65,45 → 65,28
signal Button_Pressed : std_logic := '0'; |
signal Button_CoS : std_logic := '0'; |
|
type VEC_ARG_TYPE is array(0 to 31) of std_logic_vector(15 downto 0); |
type VEC_ARG_TYPE is array(0 to 15) of std_logic_vector(15 downto 0); |
constant VEC_ARGS : VEC_ARG_TYPE := ( |
x"0000", |
x"0001", |
x"0002", |
x"0003", |
x"0004", |
x"0005", |
x"0006", |
x"0007", |
x"0008", |
x"0009", |
x"000A", |
x"000B", |
x"000C", |
x"000D", |
x"000E", |
x"000F", |
|
x"0800", |
x"0866", |
x"0975", |
x"00AE", |
x"DEAD", |
x"BEEF", |
x"CAFE", |
x"BABE", |
x"DECA", |
x"A5A5", |
x"C3C3", |
x"0123", |
x"4567", |
x"89AB", |
x"CDEF", |
x"1111", |
x"2222", |
x"3333", |
x"4444", |
x"5555", |
x"6666", |
x"7777", |
x"8888", |
x"9999", |
x"AAAA", |
x"BBBB", |
x"CCCC", |
x"DDDD", |
x"EEEE", |
x"FFFF" |
); |
|
alias Vector_Arg_Sel is Switches(9 downto 5); |
alias Vector_Cmd_Sel is Switches(4 downto 0); |
alias Vector_Arg_Sel is Switches(9 downto 6); |
alias Vector_Cmd_Sel is Switches(5 downto 0); |
|
signal Vector_Cmd : std_logic_vector(7 downto 0); |
|
156,7 → 139,7
Vector_Cmd <= x"00"; |
Vector_Arg <= x"0000"; |
elsif( rising_edge(Clock) )then |
Vector_Cmd <= "000" & Vector_Cmd_Sel; |
Vector_Cmd <= "00" & Vector_Cmd_Sel; |
Vector_Arg <= VEC_ARGS(conv_integer(Vector_Arg_Sel)); |
end if; |
end process; |