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Rev 246 → Rev 245

/VHDL/o8_sys_timer.vhd
1,163 → 1,134
-- Copyright (c)2006, 2016, 2019, 2020 Jeremy Seth Henry
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution,
-- where applicable (as part of a user interface, debugging port, etc.)
--
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- VHDL Units : o8_sys_timer
-- Description: Provides an 8-bit microsecond resolution timer for generating
-- : periodic interrupts for the Open8 CPU.
--
--
-- Revision History
-- Author Date Change
------------------ -------- ---------------------------------------------------
-- Seth Henry 07/28/11 Design Start
-- Seth Henry 12/19/19 Renamed Tmr_Out to Interrupt
-- Seth Henry 04/09/20 Modified timer update logic to reset the timer on
-- interval write.
-- Seth Henry 04/16/20 Modified to use Open8 bus record
-- Seth Henry 05/18/20 Added write qualification input
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
 
library work;
use work.open8_pkg.all;
 
entity o8_sys_timer is
generic(
mSec_Resolution : boolean := FALSE;
Address : ADDRESS_TYPE
);
port(
Open8_Bus : in OPEN8_BUS_TYPE;
Write_Qual : in std_logic := '1';
Rd_Data : out DATA_TYPE;
Interrupt : out std_logic
);
end entity;
 
architecture behave of o8_sys_timer is
 
alias Clock is Open8_Bus.Clock;
alias Reset is Open8_Bus.Reset;
alias uSec_Tick is Open8_Bus.uSec_Tick;
 
constant User_Addr : ADDRESS_TYPE := Address;
alias Comp_Addr is Open8_Bus.Address(15 downto 0);
signal Addr_Match : std_logic := '0';
 
signal Wr_En_d : std_logic;
signal Wr_En_q : std_logic := '0';
alias Wr_Data_d is Open8_Bus.Wr_Data;
signal Wr_Data_q : DATA_TYPE := x"00";
signal Rd_En_d : std_logic := '0';
signal Rd_En_q : std_logic := '0';
 
signal Interval : DATA_TYPE := x"00";
signal Update_Interval : std_logic;
signal Timer_Cnt : DATA_TYPE := x"00";
 
constant MSEC_DELAY : std_logic_vector(9 downto 0) :=
conv_std_logic_vector(1000,10);
 
signal mSec_Timer : std_logic_vector(9 downto 0) := (others => '0');
 
signal Timer_Tick : std_logic := '0';
 
begin
 
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
Wr_En_d <= Addr_Match and Open8_Bus.Wr_En;
Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
 
mSec_Resolution_enabled : if( mSec_Resolution )generate
 
mSec_Tick_proc: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
mSec_Timer <= (others => '0');
Timer_Tick <= '0';
elsif( rising_edge(Clock) )then
mSec_Timer <= mSec_Timer - uSec_Tick;
Timer_Tick <= '0';
if( mSec_Timer = 0 )then
mSec_Timer <= MSEC_DELAY;
Timer_Tick <= '1';
end if;
end if;
end process;
 
end generate;
 
uSec_Resolution_enabled : if( not mSec_Resolution )generate
 
Timer_Tick <= uSec_Tick;
 
end generate;
 
io_reg: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Wr_En_q <= '0';
Wr_Data_q <= x"00";
Rd_En_q <= '0';
Rd_Data <= OPEN8_NULLBUS;
Interval <= x"00";
Update_Interval <= '0';
elsif( rising_edge( Clock ) )then
Wr_En_q <= Wr_En_d;
Wr_Data_q <= Wr_Data_d;
 
Update_Interval <= Wr_En_q and Write_Qual;
if( Wr_En_q = '1' and Write_Qual = '1' )then
Interval <= Wr_Data_q;
end if;
 
Rd_Data <= (others => '0');
Rd_En_q <= Rd_En_d;
if( Rd_En_q = '1' )then
Rd_Data <= Interval;
end if;
end if;
end process;
 
Interval_proc: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Timer_Cnt <= x"00";
Interrupt <= '0';
elsif( rising_edge(Clock) )then
Interrupt <= '0';
Timer_Cnt <= Timer_Cnt - Timer_Tick;
if( Update_Interval = '1' )then
Timer_Cnt <= Interval;
elsif( or_reduce(Timer_Cnt) = '0' )then
Timer_Cnt <= Interval;
Interrupt <= or_reduce(Interval); -- Only trigger on Int > 0
end if;
end if;
end process;
 
end architecture;
-- Copyright (c)2006, 2016, 2019, 2020 Jeremy Seth Henry
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution,
-- where applicable (as part of a user interface, debugging port, etc.)
--
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- VHDL Units : o8_sys_timer
-- Description: Provides an 8-bit microsecond resolution timer for generating
-- : periodic interrupts for the Open8 CPU.
--
-- Notes : It is possible to set the value to zero, resulting in the
-- : output staying high indefinitely. This may cause an issue if
-- : the output is connected to an interrupt input.
-- : Also provides uSec_Tick as an output
--
-- Revision History
-- Author Date Change
------------------ -------- ---------------------------------------------------
-- Seth Henry 07/28/11 Design Start
-- Seth Henry 12/19/19 Renamed Tmr_Out to Interrupt
-- Seth Henry 04/09/20 Modified timer update logic to reset the timer on
-- interval write.
-- Seth Henry 04/16/20 Modified to use Open8 bus record
-- Seth Henry 05/18/20 Added write qualification input
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
 
library work;
use work.open8_pkg.all;
 
entity o8_sys_timer is
generic(
Address : ADDRESS_TYPE
);
port(
Open8_Bus : in OPEN8_BUS_TYPE;
Write_Qual : in std_logic := '1';
Rd_Data : out DATA_TYPE;
Interrupt : out std_logic
);
end entity;
 
architecture behave of o8_sys_timer is
 
alias Clock is Open8_Bus.Clock;
alias Reset is Open8_Bus.Reset;
alias uSec_Tick is Open8_Bus.uSec_Tick;
 
constant User_Addr : ADDRESS_TYPE := Address;
alias Comp_Addr is Open8_Bus.Address(15 downto 0);
signal Addr_Match : std_logic := '0';
 
signal Wr_En_d : std_logic;
signal Wr_En_q : std_logic := '0';
alias Wr_Data_d is Open8_Bus.Wr_Data;
signal Wr_Data_q : DATA_TYPE := x"00";
signal Rd_En_d : std_logic := '0';
signal Rd_En_q : std_logic := '0';
 
signal Interval : DATA_TYPE := x"00";
signal Update_Interval : std_logic;
signal Timer_Cnt : DATA_TYPE := x"00";
 
begin
 
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
Wr_En_d <= Addr_Match and Open8_Bus.Wr_En;
Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
 
io_reg: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Wr_En_q <= '0';
Wr_Data_q <= x"00";
Rd_En_q <= '0';
Rd_Data <= OPEN8_NULLBUS;
Interval <= x"00";
Update_Interval <= '0';
elsif( rising_edge( Clock ) )then
Wr_En_q <= Wr_En_d;
Wr_Data_q <= Wr_Data_d;
 
Update_Interval <= Wr_En_q and Write_Qual;
if( Wr_En_q = '1' and Write_Qual = '1' )then
Interval <= Wr_Data_q;
end if;
 
Rd_Data <= (others => '0');
Rd_En_q <= Rd_En_d;
if( Rd_En_q = '1' )then
Rd_Data <= Interval;
end if;
end if;
end process;
 
Interval_proc: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Timer_Cnt <= x"00";
Interrupt <= '0';
elsif( rising_edge(Clock) )then
Interrupt <= '0';
Timer_Cnt <= Timer_Cnt - uSec_Tick;
if( Update_Interval = '1' )then
Timer_Cnt <= Interval;
elsif( or_reduce(Timer_Cnt) = '0' )then
Timer_Cnt <= Interval;
Interrupt <= or_reduce(Interval); -- Only trigger on Int > 0
end if;
end if;
end process;
 
end architecture;
/VHDL/o8_vector_rx.vhd
40,7 → 40,6
-- Seth Henry 04/16/20 Modified to make use of Open8 bus record
-- Seth Henry 05/06/20 Modified to eliminate request line and detect idle
-- conditions instead
-- Seth Henry 05/23/20 Added the parallel interface
 
library ieee;
use ieee.std_logic_1164.all;
63,12 → 62,8
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE;
Interrupt : out std_logic;
-- Parallel Interface
Vec_Req : in std_logic;
Vec_Index : in std_logic_vector(5 downto 0);
Vec_Data : in std_logic_vector(15 downto 0);
-- Serial Interface
Vec_Rx : in std_logic
--
Rx_In : in std_logic
);
end entity;
 
100,24 → 95,21
(others => '0');
signal Rx_Baud_Tick : std_logic;
 
signal Vec_Rx_SR : std_logic_vector(2 downto 0);
alias Vec_Rx_MS is Vec_Rx_SR(2);
signal Rx_In_SR : std_logic_vector(2 downto 0);
alias Rx_In_MS is Rx_In_SR(2);
signal Rx_Idle_Cntr : std_logic_vector(3 downto 0);
signal RX_Idle : std_logic;
signal Rx_Data : DATA_TYPE := x"00";
signal Rx_Valid : std_logic;
 
type VECTOR_RX_STATES is ( GET_VECTOR_CMD, GET_VECTOR_ARG_LB, GET_VECTOR_ARG_UB,
SEND_INTERRUPT );
signal Vector_State : VECTOR_RX_STATES := GET_VECTOR_CMD;
 
signal Vec_Req_SR : std_logic_vector(2 downto 0);
alias Vec_Req_MS is Vec_Rx_SR(2);
signal Vector_Cmd : DATA_TYPE := x"00";
signal Vector_Arg_LB : DATA_TYPE := x"00";
signal Vector_Arg_UB : DATA_TYPE := x"00";
 
signal Vector_Index : DATA_TYPE := x"00";
signal Vector_Data : ADDRESS_TYPE := x"0000";
alias Vector_Data_LB is Vector_Data(7 downto 0);
alias Vector_Data_UB is Vector_Data(15 downto 8);
signal Rx_Data : DATA_TYPE := x"00";
signal Rx_Valid : std_logic;
 
begin
 
127,22 → 119,22
io_reg: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Reg_Sel_q <= (others => '0');
Rd_En_q <= '0';
Rd_Data <= OPEN8_NULLBUS;
Reg_Sel_q <= (others => '0');
Rd_En_q <= '0';
Rd_Data <= OPEN8_NULLBUS;
elsif( rising_edge( Clock ) )then
Reg_Sel_q <= Reg_Sel_d;
Reg_Sel_q <= Reg_Sel_d;
 
Rd_Data <= OPEN8_NULLBUS;
Rd_En_q <= Rd_En_d;
Rd_Data <= OPEN8_NULLBUS;
Rd_En_q <= Rd_En_d;
if( Rd_En_q = '1' )then
case( Reg_Sel_q )is
when "00" =>
Rd_Data <= Vector_Index;
Rd_Data <= Vector_Cmd;
when "01" =>
Rd_Data <= Vector_Data_LB;
Rd_Data <= Vector_Arg_LB;
when "10" =>
Rd_Data <= Vector_Data_UB;
Rd_Data <= Vector_Arg_UB;
when others =>
null;
end case;
153,28 → 145,28
RX_Idle_proc: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Rx_Baud_Cntr <= (others => '0');
Rx_Baud_Tick <= '0';
Vec_Rx_SR <= (others => '1');
Rx_Idle_Cntr <= (others => '0');
Rx_Idle <= '0';
Rx_Baud_Cntr <= (others => '0');
Rx_Baud_Tick <= '0';
Rx_In_SR <= (others => '1');
Rx_Idle_Cntr <= (others => '0');
Rx_Idle <= '0';
elsif( rising_edge(Clock) )then
Rx_Baud_Cntr <= Rx_Baud_Cntr - 1;
Rx_Baud_Tick <= '0';
Rx_Baud_Cntr <= Rx_Baud_Cntr - 1;
Rx_Baud_Tick <= '0';
if( Rx_Baud_Cntr = 0 )then
Rx_Baud_Cntr <= FULL_PERIOD;
Rx_Baud_Tick <= '1';
Rx_Baud_Cntr <= FULL_PERIOD;
Rx_Baud_Tick <= '1';
end if;
 
Vec_Rx_SR <= Vec_Rx_SR(1 downto 0) & Vec_Rx;
Rx_Idle_Cntr <= Rx_Idle_Cntr - Rx_Baud_Tick;
if( Vec_Rx_MS = '0' )then
Rx_Idle_Cntr <= (others => '1');
Rx_In_SR <= Rx_In_SR(1 downto 0) & Rx_In;
Rx_Idle_Cntr <= Rx_Idle_Cntr - Rx_Baud_Tick;
if( Rx_In_MS = '0' )then
Rx_Idle_Cntr <= (others => '1');
elsif( Rx_Idle_Cntr = 0 )then
Rx_Idle_Cntr <= (others => '0');
Rx_Idle_Cntr <= (others => '0');
end if;
 
Rx_Idle <= nor_reduce(Rx_Idle_Cntr);
Rx_Idle <= nor_reduce(Rx_Idle_Cntr);
end if;
end process;
 
189,7 → 181,7
Clock => Clock,
Reset => Reset,
--
RX_In => Vec_Rx,
Rx_In => RX_In,
--
Rx_Data => RX_Data,
Rx_Valid => RX_Valid,
199,38 → 191,29
Vector_RX_proc: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Vec_Req_SR <= (others => '0');
Vector_State <= GET_VECTOR_CMD;
Vector_Index <= x"00";
Vector_Data <= x"0000";
Vector_Cmd <= x"00";
Vector_Arg_LB <= x"00";
Vector_Arg_UB <= x"00";
Interrupt <= '0';
elsif( rising_edge(Clock) )then
Vec_Req_SR <= Vec_Req_SR(1 downto 0) & Vec_Req;
 
Interrupt <= '0';
 
if( Vec_Req_MS = '1' )then
Vector_Index <= "00" & Vec_Index;
Vector_Data <= Vec_Data;
Interrupt <= '1';
end if;
 
case( Vector_State )is
when GET_VECTOR_CMD =>
if( Rx_Valid = '1' )then
Vector_Index <= "00" & Rx_Data(5 downto 0);
Vector_Cmd <= Rx_Data;
Vector_State <= GET_VECTOR_ARG_LB;
end if;
 
when GET_VECTOR_ARG_LB =>
if( Rx_Valid = '1' )then
Vector_Data_LB <= Rx_Data;
Vector_Arg_LB <= Rx_Data;
Vector_State <= GET_VECTOR_ARG_UB;
end if;
 
when GET_VECTOR_ARG_UB =>
if( Rx_Valid = '1' )then
Vector_Data_UB <= Rx_Data;
Vector_Arg_UB <= Rx_Data;
Vector_State <= SEND_INTERRUPT;
end if;
 

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